hw/gt64xxx.c

   1 /*
   2  * QEMU GT64120 PCI host
   3  *
   4  * Copyright (c) 2006,2007 Aurelien Jarno
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "vl.h"
  26 typedef target_phys_addr_t pci_addr_t;
  27 #include "pci_host.h"
  28
  29 #define GT_REGS                 (0x1000 >> 2)
  30
  31 /* CPU Configuration */
  32 #define GT_CPU                  (0x000 >> 2)
  33 #define GT_MULTI                (0x120 >> 2)
  34
  35 /* CPU Address Decode */
  36 #define GT_SCS10LD              (0x008 >> 2)
  37 #define GT_SCS10HD              (0x010 >> 2)
  38 #define GT_SCS32LD              (0x018 >> 2)
  39 #define GT_SCS32HD              (0x020 >> 2)
  40 #define GT_CS20LD               (0x028 >> 2)
  41 #define GT_CS20HD               (0x030 >> 2)
  42 #define GT_CS3BOOTLD            (0x038 >> 2)
  43 #define GT_CS3BOOTHD            (0x040 >> 2)
  44 #define GT_PCI0IOLD             (0x048 >> 2)
  45 #define GT_PCI0IOHD             (0x050 >> 2)
  46 #define GT_PCI0M0LD             (0x058 >> 2)
  47 #define GT_PCI0M0HD             (0x060 >> 2)
  48 #define GT_ISD                  (0x068 >> 2)
  49
  50 #define GT_PCI0M1LD             (0x080 >> 2)
  51 #define GT_PCI0M1HD             (0x088 >> 2)
  52 #define GT_PCI1IOLD             (0x090 >> 2)
  53 #define GT_PCI1IOHD             (0x098 >> 2)
  54 #define GT_PCI1M0LD             (0x0a0 >> 2)
  55 #define GT_PCI1M0HD             (0x0a8 >> 2)
  56 #define GT_PCI1M1LD             (0x0b0 >> 2)
  57 #define GT_PCI1M1HD             (0x0b8 >> 2)
  58 #define GT_PCI1M1LD             (0x0b0 >> 2)
  59 #define GT_PCI1M1HD             (0x0b8 >> 2)
  60
  61 #define GT_SCS10AR              (0x0d0 >> 2)
  62 #define GT_SCS32AR              (0x0d8 >> 2)
  63 #define GT_CS20R                (0x0e0 >> 2)
  64 #define GT_CS3BOOTR             (0x0e8 >> 2)
  65
  66 #define GT_PCI0IOREMAP          (0x0f0 >> 2)
  67 #define GT_PCI0M0REMAP          (0x0f8 >> 2)
  68 #define GT_PCI0M1REMAP          (0x100 >> 2)
  69 #define GT_PCI1IOREMAP          (0x108 >> 2)
  70 #define GT_PCI1M0REMAP          (0x110 >> 2)
  71 #define GT_PCI1M1REMAP          (0x118 >> 2)
  72
  73 /* CPU Error Report */
  74 #define GT_CPUERR_ADDRLO        (0x070 >> 2)
  75 #define GT_CPUERR_ADDRHI        (0x078 >> 2)
  76 #define GT_CPUERR_DATALO        (0x128 >> 2)            /* GT-64120A only  */
  77 #define GT_CPUERR_DATAHI        (0x130 >> 2)            /* GT-64120A only  */
  78 #define GT_CPUERR_PARITY        (0x138 >> 2)            /* GT-64120A only  */
  79
  80 /* CPU Sync Barrier */
  81 #define GT_PCI0SYNC             (0x0c0 >> 2)
  82 #define GT_PCI1SYNC             (0x0c8 >> 2)
  83
  84 /* SDRAM and Device Address Decode */
  85 #define GT_SCS0LD               (0x400 >> 2)
  86 #define GT_SCS0HD               (0x404 >> 2)
  87 #define GT_SCS1LD               (0x408 >> 2)
  88 #define GT_SCS1HD               (0x40c >> 2)
  89 #define GT_SCS2LD               (0x410 >> 2)
  90 #define GT_SCS2HD               (0x414 >> 2)
  91 #define GT_SCS3LD               (0x418 >> 2)
  92 #define GT_SCS3HD               (0x41c >> 2)
  93 #define GT_CS0LD                (0x420 >> 2)
  94 #define GT_CS0HD                (0x424 >> 2)
  95 #define GT_CS1LD                (0x428 >> 2)
  96 #define GT_CS1HD                (0x42c >> 2)
  97 #define GT_CS2LD                (0x430 >> 2)
  98 #define GT_CS2HD                (0x434 >> 2)
  99 #define GT_CS3LD                (0x438 >> 2)
 100 #define GT_CS3HD                (0x43c >> 2)
 101 #define GT_BOOTLD               (0x440 >> 2)
 102 #define GT_BOOTHD               (0x444 >> 2)
 103 #define GT_ADERR                (0x470 >> 2)
 104
 105 /* SDRAM Configuration */
 106 #define GT_SDRAM_CFG            (0x448 >> 2)
 107 #define GT_SDRAM_OPMODE         (0x474 >> 2)
 108 #define GT_SDRAM_BM             (0x478 >> 2)
 109 #define GT_SDRAM_ADDRDECODE     (0x47c >> 2)
 110
 111 /* SDRAM Parameters */
 112 #define GT_SDRAM_B0             (0x44c >> 2)
 113 #define GT_SDRAM_B1             (0x450 >> 2)
 114 #define GT_SDRAM_B2             (0x454 >> 2)
 115 #define GT_SDRAM_B3             (0x458 >> 2)
 116
 117 /* Device Parameters */
 118 #define GT_DEV_B0               (0x45c >> 2)
 119 #define GT_DEV_B1               (0x460 >> 2)
 120 #define GT_DEV_B2               (0x464 >> 2)
 121 #define GT_DEV_B3               (0x468 >> 2)
 122 #define GT_DEV_BOOT             (0x46c >> 2)
 123
 124 /* ECC */
 125 #define GT_ECC_ERRDATALO        (0x480 >> 2)            /* GT-64120A only  */
 126 #define GT_ECC_ERRDATAHI        (0x484 >> 2)            /* GT-64120A only  */
 127 #define GT_ECC_MEM              (0x488 >> 2)            /* GT-64120A only  */
 128 #define GT_ECC_CALC             (0x48c >> 2)            /* GT-64120A only  */
 129 #define GT_ECC_ERRADDR          (0x490 >> 2)            /* GT-64120A only  */
 130
 131 /* DMA Record */
 132 #define GT_DMA0_CNT             (0x800 >> 2)
 133 #define GT_DMA1_CNT             (0x804 >> 2)
 134 #define GT_DMA2_CNT             (0x808 >> 2)
 135 #define GT_DMA3_CNT             (0x80c >> 2)
 136 #define GT_DMA0_SA              (0x810 >> 2)
 137 #define GT_DMA1_SA              (0x814 >> 2)
 138 #define GT_DMA2_SA              (0x818 >> 2)
 139 #define GT_DMA3_SA              (0x81c >> 2)
 140 #define GT_DMA0_DA              (0x820 >> 2)
 141 #define GT_DMA1_DA              (0x824 >> 2)
 142 #define GT_DMA2_DA              (0x828 >> 2)
 143 #define GT_DMA3_DA              (0x82c >> 2)
 144 #define GT_DMA0_NEXT            (0x830 >> 2)
 145 #define GT_DMA1_NEXT            (0x834 >> 2)
 146 #define GT_DMA2_NEXT            (0x838 >> 2)
 147 #define GT_DMA3_NEXT            (0x83c >> 2)
 148 #define GT_DMA0_CUR             (0x870 >> 2)
 149 #define GT_DMA1_CUR             (0x874 >> 2)
 150 #define GT_DMA2_CUR             (0x878 >> 2)
 151 #define GT_DMA3_CUR             (0x87c >> 2)
 152
 153 /* DMA Channel Control */
 154 #define GT_DMA0_CTRL            (0x840 >> 2)
 155 #define GT_DMA1_CTRL            (0x844 >> 2)
 156 #define GT_DMA2_CTRL            (0x848 >> 2)
 157 #define GT_DMA3_CTRL            (0x84c >> 2)
 158
 159 /* DMA Arbiter */
 160 #define GT_DMA_ARB              (0x860 >> 2)
 161
 162 /* Timer/Counter */
 163 #define GT_TC0                  (0x850 >> 2)
 164 #define GT_TC1                  (0x854 >> 2)
 165 #define GT_TC2                  (0x858 >> 2)
 166 #define GT_TC3                  (0x85c >> 2)
 167 #define GT_TC_CONTROL           (0x864 >> 2)
 168
 169 /* PCI Internal */
 170 #define GT_PCI0_CMD             (0xc00 >> 2)
 171 #define GT_PCI0_TOR             (0xc04 >> 2)
 172 #define GT_PCI0_BS_SCS10        (0xc08 >> 2)
 173 #define GT_PCI0_BS_SCS32        (0xc0c >> 2)
 174 #define GT_PCI0_BS_CS20         (0xc10 >> 2)
 175 #define GT_PCI0_BS_CS3BT        (0xc14 >> 2)
 176 #define GT_PCI1_IACK            (0xc30 >> 2)
 177 #define GT_PCI0_IACK            (0xc34 >> 2)
 178 #define GT_PCI0_BARE            (0xc3c >> 2)
 179 #define GT_PCI0_PREFMBR         (0xc40 >> 2)
 180 #define GT_PCI0_SCS10_BAR       (0xc48 >> 2)
 181 #define GT_PCI0_SCS32_BAR       (0xc4c >> 2)
 182 #define GT_PCI0_CS20_BAR        (0xc50 >> 2)
 183 #define GT_PCI0_CS3BT_BAR       (0xc54 >> 2)
 184 #define GT_PCI0_SSCS10_BAR      (0xc58 >> 2)
 185 #define GT_PCI0_SSCS32_BAR      (0xc5c >> 2)
 186 #define GT_PCI0_SCS3BT_BAR      (0xc64 >> 2)
 187 #define GT_PCI1_CMD             (0xc80 >> 2)
 188 #define GT_PCI1_TOR             (0xc84 >> 2)
 189 #define GT_PCI1_BS_SCS10        (0xc88 >> 2)
 190 #define GT_PCI1_BS_SCS32        (0xc8c >> 2)
 191 #define GT_PCI1_BS_CS20         (0xc90 >> 2)
 192 #define GT_PCI1_BS_CS3BT        (0xc94 >> 2)
 193 #define GT_PCI1_BARE            (0xcbc >> 2)
 194 #define GT_PCI1_PREFMBR         (0xcc0 >> 2)
 195 #define GT_PCI1_SCS10_BAR       (0xcc8 >> 2)
 196 #define GT_PCI1_SCS32_BAR       (0xccc >> 2)
 197 #define GT_PCI1_CS20_BAR        (0xcd0 >> 2)
 198 #define GT_PCI1_CS3BT_BAR       (0xcd4 >> 2)
 199 #define GT_PCI1_SSCS10_BAR      (0xcd8 >> 2)
 200 #define GT_PCI1_SSCS32_BAR      (0xcdc >> 2)
 201 #define GT_PCI1_SCS3BT_BAR      (0xce4 >> 2)
 202 #define GT_PCI1_CFGADDR         (0xcf0 >> 2)
 203 #define GT_PCI1_CFGDATA         (0xcf4 >> 2)
 204 #define GT_PCI0_CFGADDR         (0xcf8 >> 2)
 205 #define GT_PCI0_CFGDATA         (0xcfc >> 2)
 206
 207 /* Interrupts */
 208 #define GT_INTRCAUSE            (0xc18 >> 2)
 209 #define GT_INTRMASK             (0xc1c >> 2)
 210 #define GT_PCI0_ICMASK          (0xc24 >> 2)
 211 #define GT_PCI0_SERR0MASK       (0xc28 >> 2)
 212 #define GT_CPU_INTSEL           (0xc70 >> 2)
 213 #define GT_PCI0_INTSEL          (0xc74 >> 2)
 214 #define GT_HINTRCAUSE           (0xc98 >> 2)
 215 #define GT_HINTRMASK            (0xc9c >> 2)
 216 #define GT_PCI0_HICMASK         (0xca4 >> 2)
 217 #define GT_PCI1_SERR1MASK       (0xca8 >> 2)
 218
 219
 220 typedef PCIHostState GT64120PCIState;
 221
 222 typedef struct GT64120State {
 223     GT64120PCIState *pci;
 224     uint32_t regs[GT_REGS];
 225     target_phys_addr_t PCI0IO_start;
 226     target_phys_addr_t PCI0IO_length;
 227 } GT64120State;
 228
 229 static void gt64120_pci_mapping(GT64120State *s)
 230 {
 231     /* Update IO mapping */
 232     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
 233     {
 234       /* Unmap old IO address */
 235       if (s->PCI0IO_length)
 236       {
 237         cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
 238       }
 239       /* Map new IO address */
 240       s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
 241       s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
 242       isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
 243     }
 244 }
 245
 246 static void gt64120_writel (void *opaque, target_phys_addr_t addr,
 247                             uint32_t val)
 248 {
 249     GT64120State *s = opaque;
 250     uint32_t saddr;
 251
 252 #ifdef TARGET_WORDS_BIGENDIAN
 253     val = bswap32(val);
 254 #endif
 255
 256     saddr = (addr & 0xfff) >> 2;
 257     switch (saddr) {
 258
 259     /* CPU Configuration */
 260     case GT_CPU:
 261         s->regs[GT_CPU] = val;
 262         break;
 263     case GT_MULTI:
 264         /* Read-only register as only one GT64xxx is present on the CPU bus */
 265         break;
 266
 267     /* CPU Address Decode */
 268     case GT_PCI0IOLD:
 269         s->regs[GT_PCI0IOLD]    = val & 0x00007fff;
 270         s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
 271         gt64120_pci_mapping(s);
 272         break;
 273     case GT_PCI0M0LD:
 274         s->regs[GT_PCI0M0LD]    = val & 0x00007fff;
 275         s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
 276         gt64120_pci_mapping(s);
 277         break;
 278     case GT_PCI0M1LD:
 279         s->regs[GT_PCI0M1LD]    = val & 0x00007fff;
 280         s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
 281         gt64120_pci_mapping(s);
 282         break;
 283     case GT_PCI1IOLD:
 284         s->regs[GT_PCI1IOLD]    = val & 0x00007fff;
 285         s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
 286         gt64120_pci_mapping(s);
 287         break;
 288     case GT_PCI1M0LD:
 289         s->regs[GT_PCI1M0LD]    = val & 0x00007fff;
 290         s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
 291         gt64120_pci_mapping(s);
 292         break;
 293     case GT_PCI1M1LD:
 294         s->regs[GT_PCI1M1LD]    = val & 0x00007fff;
 295         s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
 296         gt64120_pci_mapping(s);
 297         break;
 298     case GT_PCI0IOHD:
 299     case GT_PCI0M0HD:
 300     case GT_PCI0M1HD:
 301     case GT_PCI1IOHD:
 302     case GT_PCI1M0HD:
 303     case GT_PCI1M1HD:
 304         s->regs[saddr] = val & 0x0000007f;
 305         gt64120_pci_mapping(s);
 306         break;
 307     case GT_PCI0IOREMAP:
 308     case GT_PCI0M0REMAP:
 309     case GT_PCI0M1REMAP:
 310     case GT_PCI1IOREMAP:
 311     case GT_PCI1M0REMAP:
 312     case GT_PCI1M1REMAP:
 313         s->regs[saddr] = val & 0x000007ff;
 314         gt64120_pci_mapping(s);
 315         break;
 316
 317     /* CPU Error Report */
 318     case GT_CPUERR_ADDRLO:
 319     case GT_CPUERR_ADDRHI:
 320     case GT_CPUERR_DATALO:
 321     case GT_CPUERR_DATAHI:
 322     case GT_CPUERR_PARITY:
 323         /* Read-only registers, do nothing */
 324         break;
 325
 326     /* CPU Sync Barrier */
 327     case GT_PCI0SYNC:
 328     case GT_PCI1SYNC:
 329         /* Read-only registers, do nothing */
 330         break;
 331
 332     /* ECC */
 333     case GT_ECC_ERRDATALO:
 334     case GT_ECC_ERRDATAHI:
 335     case GT_ECC_MEM:
 336     case GT_ECC_CALC:
 337     case GT_ECC_ERRADDR:
 338         /* Read-only registers, do nothing */
 339         break;
 340
 341     /* PCI Internal */
 342     case GT_PCI0_CMD:
 343     case GT_PCI1_CMD:
 344         s->regs[saddr] = val & 0x0401fc0f;
 345         break;
 346     case GT_PCI0_CFGADDR:
 347         s->pci->config_reg = val & 0x80fffffc;
 348         break;
 349     case GT_PCI0_CFGDATA:
 350         pci_host_data_writel(s->pci, 0, val);
 351         break;
 352
 353     /* SDRAM Parameters */
 354     case GT_SDRAM_B0:
 355     case GT_SDRAM_B1:
 356     case GT_SDRAM_B2:
 357     case GT_SDRAM_B3:
 358         /* We don't simulate electrical parameters of the SDRAM.
 359            Accept, but ignore the values. */
 360         s->regs[saddr] = val;
 361         break;
 362
 363     default:
 364 #if 0
 365         printf ("gt64120_writel: Bad register offset 0x%x\n", (int)addr);
 366 #endif
 367         break;
 368     }
 369 }
 370
 371 static uint32_t gt64120_readl (void *opaque,
 372                                target_phys_addr_t addr)
 373 {
 374     GT64120State *s = opaque;
 375     uint32_t val;
 376     uint32_t saddr;
 377
 378     val = 0;
 379     saddr = (addr & 0xfff) >> 2;
 380
 381     switch (saddr) {
 382
 383     /* CPU Configuration */
 384     case GT_MULTI:
 385         /* Only one GT64xxx is present on the CPU bus, return
 386            the initial value */
 387         val = s->regs[saddr];
 388         break;
 389
 390     /* CPU Error Report */
 391     case GT_CPUERR_ADDRLO:
 392     case GT_CPUERR_ADDRHI:
 393     case GT_CPUERR_DATALO:
 394     case GT_CPUERR_DATAHI:
 395     case GT_CPUERR_PARITY:
 396         /* Emulated memory has no error, always return the initial
 397            values */
 398         val = s->regs[saddr];
 399         break;
 400
 401     /* CPU Sync Barrier */
 402     case GT_PCI0SYNC:
 403     case GT_PCI1SYNC:
 404         /* Reading those register should empty all FIFO on the PCI
 405            bus, which are not emulated. The return value should be
 406            a random value that should be ignored. */
 407         val = 0xc000ffee;
 408         break;
 409
 410     /* ECC */
 411     case GT_ECC_ERRDATALO:
 412     case GT_ECC_ERRDATAHI:
 413     case GT_ECC_MEM:
 414     case GT_ECC_CALC:
 415     case GT_ECC_ERRADDR:
 416         /* Emulated memory has no error, always return the initial
 417            values */
 418         val = s->regs[saddr];
 419         break;
 420
 421     case GT_CPU:
 422     case GT_PCI0IOLD:
 423     case GT_PCI0M0LD:
 424     case GT_PCI0M1LD:
 425     case GT_PCI1IOLD:
 426     case GT_PCI1M0LD:
 427     case GT_PCI1M1LD:
 428     case GT_PCI0IOHD:
 429     case GT_PCI0M0HD:
 430     case GT_PCI0M1HD:
 431     case GT_PCI1IOHD:
 432     case GT_PCI1M0HD:
 433     case GT_PCI1M1HD:
 434     case GT_PCI0_CMD:
 435     case GT_PCI1_CMD:
 436     case GT_PCI0IOREMAP:
 437     case GT_PCI0M0REMAP:
 438     case GT_PCI0M1REMAP:
 439     case GT_PCI1IOREMAP:
 440     case GT_PCI1M0REMAP:
 441     case GT_PCI1M1REMAP:
 442         val = s->regs[saddr];
 443         break;
 444     case GT_PCI0_IACK:
 445         /* Read the IRQ number */
 446         val = pic_read_irq(isa_pic);
 447         break;
 448
 449     /* SDRAM Parameters */
 450     case GT_SDRAM_B0:
 451     case GT_SDRAM_B1:
 452     case GT_SDRAM_B2:
 453     case GT_SDRAM_B3:
 454         /* We don't simulate electrical parameters of the SDRAM.
 455            Just return the last written value. */
 456         val = s->regs[saddr];
 457         break;
 458
 459     /* PCI Internal */
 460     case GT_PCI0_CFGADDR:
 461         val = s->pci->config_reg;
 462         break;
 463     case GT_PCI0_CFGDATA:
 464         val = pci_host_data_readl(s->pci, 0);
 465         break;
 466
 467     default:
 468         val = s->regs[saddr];
 469 #if 0
 470         printf ("gt64120_readl: Bad register offset 0x%x\n", (int)addr);
 471 #endif
 472         break;
 473     }
 474
 475 #ifdef TARGET_WORDS_BIGENDIAN
 476     return bswap32(val);
 477 #else
 478     return val;
 479 #endif
 480 }
 481
 482 static CPUWriteMemoryFunc *gt64120_write[] = {
 483     &gt64120_writel,
 484     &gt64120_writel,
 485     &gt64120_writel,
 486 };
 487
 488 static CPUReadMemoryFunc *gt64120_read[] = {
 489     &gt64120_readl,
 490     &gt64120_readl,
 491     &gt64120_readl,
 492 };
 493
 494 static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
 495 {
 496     int slot;
 497
 498     slot = (pci_dev->devfn >> 3);
 499
 500     switch (slot) {
 501       /* PIIX4 USB */
 502       case 10:
 503         return 3;
 504       /* AMD 79C973 Ethernet */
 505       case 11:
 506         return 0;
 507       /* Crystal 4281 Sound */
 508       case 12:
 509         return 0;
 510       /* PCI slot 1 to 4 */
 511       case 18 ... 21:
 512         return ((slot - 18) + irq_num) & 0x03;
 513       /* Unknown device, don't do any translation */
 514       default:
 515         return irq_num;
 516     }
 517 }
 518
 519 extern PCIDevice *piix4_dev;
 520 static int pci_irq_levels[4];
 521
 522 static void pci_gt64120_set_irq(void *pic, int irq_num, int level)
 523 {
 524     int i, pic_irq, pic_level;
 525
 526     pci_irq_levels[irq_num] = level;
 527
 528     /* now we change the pic irq level according to the piix irq mappings */
 529     /* XXX: optimize */
 530     pic_irq = piix4_dev->config[0x60 + irq_num];
 531     if (pic_irq < 16) {
 532         /* The pic level is the logical OR of all the PCI irqs mapped
 533            to it */
 534         pic_level = 0;
 535         for (i = 0; i < 4; i++) {
 536             if (pic_irq == piix4_dev->config[0x60 + i])
 537                 pic_level |= pci_irq_levels[i];
 538         }
 539         pic_set_irq(pic_irq, pic_level);
 540     }
 541 }
 542
 543
 544 void gt64120_reset(void *opaque)
 545 {
 546     GT64120State *s = opaque;
 547
 548     /* CPU Configuration */
 549 #ifdef TARGET_WORDS_BIGENDIAN
 550     s->regs[GT_CPU]           = 0x00000000;
 551 #else
 552     s->regs[GT_CPU]           = 0x00000800;
 553 #endif
 554     s->regs[GT_MULTI]         = 0x00000000;
 555
 556     /* CPU Address decode FIXME: not complete*/
 557     s->regs[GT_PCI0IOLD]      = 0x00000080;
 558     s->regs[GT_PCI0IOHD]      = 0x0000000f;
 559     s->regs[GT_PCI0M0LD]      = 0x00000090;
 560     s->regs[GT_PCI0M0HD]      = 0x0000001f;
 561     s->regs[GT_PCI0M1LD]      = 0x00000790;
 562     s->regs[GT_PCI0M1HD]      = 0x0000001f;
 563     s->regs[GT_PCI1IOLD]      = 0x00000100;
 564     s->regs[GT_PCI1IOHD]      = 0x0000000f;
 565     s->regs[GT_PCI1M0LD]      = 0x00000110;
 566     s->regs[GT_PCI1M0HD]      = 0x0000001f;
 567     s->regs[GT_PCI1M1LD]      = 0x00000120;
 568     s->regs[GT_PCI1M1HD]      = 0x0000002f;
 569     s->regs[GT_PCI0IOREMAP]   = 0x00000080;
 570     s->regs[GT_PCI0M0REMAP]   = 0x00000090;
 571     s->regs[GT_PCI0M1REMAP]   = 0x00000790;
 572     s->regs[GT_PCI1IOREMAP]   = 0x00000100;
 573     s->regs[GT_PCI1M0REMAP]   = 0x00000110;
 574     s->regs[GT_PCI1M1REMAP]   = 0x00000120;
 575
 576     /* CPU Error Report */
 577     s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
 578     s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
 579     s->regs[GT_CPUERR_DATALO] = 0xffffffff;
 580     s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
 581     s->regs[GT_CPUERR_PARITY] = 0x000000ff;
 582
 583     /* ECC */
 584     s->regs[GT_ECC_ERRDATALO] = 0x00000000;
 585     s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
 586     s->regs[GT_ECC_MEM]       = 0x00000000;
 587     s->regs[GT_ECC_CALC]      = 0x00000000;
 588     s->regs[GT_ECC_ERRADDR]   = 0x00000000;
 589
 590     /* SDRAM Parameters */
 591     s->regs[GT_SDRAM_B0]      = 0x00000005;
 592     s->regs[GT_SDRAM_B1]      = 0x00000005;
 593     s->regs[GT_SDRAM_B2]      = 0x00000005;
 594     s->regs[GT_SDRAM_B3]      = 0x00000005;
 595
 596     /* PCI Internal FIXME: not complete*/
 597 #ifdef TARGET_WORDS_BIGENDIAN
 598     s->regs[GT_PCI0_CMD]      = 0x00000000;
 599     s->regs[GT_PCI1_CMD]      = 0x00000000;
 600 #else
 601     s->regs[GT_PCI0_CMD]      = 0x00010001;
 602     s->regs[GT_PCI1_CMD]      = 0x00010001;
 603 #endif
 604     s->regs[GT_PCI0_IACK]     = 0x00000000;
 605     s->regs[GT_PCI1_IACK]     = 0x00000000;
 606
 607     gt64120_pci_mapping(s);
 608 }
 609
 610 PCIBus *pci_gt64120_init(void *pic)
 611 {
 612     GT64120State *s;
 613     PCIDevice *d;
 614     int gt64120;
 615
 616     s = qemu_mallocz(sizeof(GT64120State));
 617     s->pci = qemu_mallocz(sizeof(GT64120PCIState));
 618     gt64120_reset(s);
 619
 620     s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
 621                                    pic, 144, 4);
 622
 623     gt64120 = cpu_register_io_memory(0, gt64120_read,
 624                                      gt64120_write, s);
 625     cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120);
 626
 627     d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
 628                             0, NULL, NULL);
 629
 630     d->config[0x00] = 0xab; // vendor_id
 631     d->config[0x01] = 0x11;
 632     d->config[0x02] = 0x46; // device_id
 633     d->config[0x03] = 0x20;
 634     d->config[0x04] = 0x06;
 635     d->config[0x05] = 0x00;
 636     d->config[0x06] = 0x80;
 637     d->config[0x07] = 0xa2;
 638     d->config[0x08] = 0x10;
 639     d->config[0x09] = 0x00;
 640     d->config[0x0A] = 0x80;
 641     d->config[0x0B] = 0x05;
 642     d->config[0x0C] = 0x08;
 643     d->config[0x0D] = 0x40;
 644     d->config[0x0E] = 0x00;
 645     d->config[0x0F] = 0x00;
 646     d->config[0x17] = 0x08;
 647     d->config[0x1B] = 0x1c;
 648     d->config[0x1F] = 0x1f;
 649     d->config[0x23] = 0x14;
 650     d->config[0x27] = 0x14;
 651     d->config[0x3D] = 0x01;
 652
 653     return s->pci->bus;
 654 }