hw/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "sysbus.h"
  21 #include "arm-misc.h"
  22 #include "devices.h"
  23 #include "loader.h"
  24 #include "net.h"
  25 #include "sysemu.h"
  26 #include "boards.h"
  27 #include "sysbus.h"
  28 #include "blockdev.h"
  29 #include "exec-memory.h"
  30
  31 #define SMP_BOOT_ADDR 0x100
  32 #define SMP_BOOT_REG  0x40
  33 #define GIC_BASE_ADDR 0xfff10000
  34
  35 #define NIRQ_GIC      160
  36
  37 /* Board init.  */
  38 static void highbank_cpu_reset(void *opaque)
  39 {
  40     CPUState *env = opaque;
  41
  42     env->cp15.c15_config_base_address = GIC_BASE_ADDR;
  43 }
  44
  45 static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
  46 {
  47     int n;
  48     uint32_t smpboot[] = {
  49         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  50         0xe210000f, /* ands r0, r0, #0x0f */
  51         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  52         0xe0830200, /* add r0, r3, r0, lsl #4 */
  53         0xe59f2018, /* ldr r2, privbase */
  54         0xe3a01001, /* mov r1, #1 */
  55         0xe5821100, /* str r1, [r2, #256] */
  56         0xe320f003, /* wfi */
  57         0xe5901000, /* ldr     r1, [r0] */
  58         0xe1110001, /* tst     r1, r1 */
  59         0x0afffffb, /* beq     <wfi> */
  60         0xe12fff11, /* bx      r1 */
  61         GIC_BASE_ADDR      /* privbase: gic address.  */
  62     };
  63     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  64         smpboot[n] = tswap32(smpboot[n]);
  65     }
  66     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  67 }
  68
  69 static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)
  70 {
  71     switch (info->nb_cpus) {
  72     case 4:
  73         stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
  74     case 3:
  75         stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
  76     case 2:
  77         stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
  78         env->regs[15] = SMP_BOOT_ADDR;
  79         break;
  80     default:
  81         break;
  82     }
  83 }
  84
  85 #define NUM_REGS      0x200
  86 static void hb_regs_write(void *opaque, target_phys_addr_t offset,
  87                           uint64_t value, unsigned size)
  88 {
  89     uint32_t *regs = opaque;
  90
  91     if (offset == 0xf00) {
  92         if (value == 1 || value == 2) {
  93             qemu_system_reset_request();
  94         } else if (value == 3) {
  95             qemu_system_shutdown_request();
  96         }
  97     }
  98
  99     regs[offset/4] = value;
 100 }
 101
 102 static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset,
 103                              unsigned size)
 104 {
 105     uint32_t *regs = opaque;
 106     uint32_t value = regs[offset/4];
 107
 108     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 109         value |= 0x30000000;
 110     }
 111
 112     return value;
 113 }
 114
 115 static const MemoryRegionOps hb_mem_ops = {
 116     .read = hb_regs_read,
 117     .write = hb_regs_write,
 118     .endianness = DEVICE_NATIVE_ENDIAN,
 119 };
 120
 121 typedef struct {
 122     SysBusDevice busdev;
 123     MemoryRegion *iomem;
 124     uint32_t regs[NUM_REGS];
 125 } HighbankRegsState;
 126
 127 static VMStateDescription vmstate_highbank_regs = {
 128     .name = "highbank-regs",
 129     .version_id = 0,
 130     .minimum_version_id = 0,
 131     .minimum_version_id_old = 0,
 132     .fields = (VMStateField[]) {
 133         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 134         VMSTATE_END_OF_LIST(),
 135     },
 136 };
 137
 138 static void highbank_regs_reset(DeviceState *dev)
 139 {
 140     SysBusDevice *sys_dev = sysbus_from_qdev(dev);
 141     HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev);
 142
 143     s->regs[0x40] = 0x05F20121;
 144     s->regs[0x41] = 0x2;
 145     s->regs[0x42] = 0x05F30121;
 146     s->regs[0x43] = 0x05F40121;
 147 }
 148
 149 static int highbank_regs_init(SysBusDevice *dev)
 150 {
 151     HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
 152
 153     s->iomem = g_new(MemoryRegion, 1);
 154     memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
 155                           0x1000);
 156     sysbus_init_mmio(dev, s->iomem);
 157
 158     return 0;
 159 }
 160
 161 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 162 {
 163     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 164     DeviceClass *dc = DEVICE_CLASS(klass);
 165
 166     sbc->init = highbank_regs_init;
 167     dc->desc = "Calxeda Highbank registers";
 168     dc->vmsd = &vmstate_highbank_regs;
 169     dc->reset = highbank_regs_reset;
 170 }
 171
 172 static TypeInfo highbank_regs_info = {
 173     .name          = "highbank-regs",
 174     .parent        = TYPE_SYS_BUS_DEVICE,
 175     .instance_size = sizeof(HighbankRegsState),
 176     .class_init    = highbank_regs_class_init,
 177 };
 178
 179 static void highbank_regs_register_types(void)
 180 {
 181     type_register_static(&highbank_regs_info);
 182 }
 183
 184 type_init(highbank_regs_register_types)
 185
 186 static struct arm_boot_info highbank_binfo;
 187
 188 /* ram_size must be set to match the upper bound of memory in the
 189  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 190  * normally 0xff900000 or -m 4089. When running this board on a
 191  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 192  * device tree and pass -m 2047 to QEMU.
 193  */
 194 static void highbank_init(ram_addr_t ram_size,
 195                      const char *boot_device,
 196                      const char *kernel_filename, const char *kernel_cmdline,
 197                      const char *initrd_filename, const char *cpu_model)
 198 {
 199     CPUState *env = NULL;
 200     DeviceState *dev;
 201     SysBusDevice *busdev;
 202     qemu_irq *irqp;
 203     qemu_irq pic[128];
 204     int n;
 205     qemu_irq cpu_irq[4];
 206     MemoryRegion *sysram;
 207     MemoryRegion *dram;
 208     MemoryRegion *sysmem;
 209     char *sysboot_filename;
 210
 211     if (!cpu_model) {
 212         cpu_model = "cortex-a9";
 213     }
 214
 215     for (n = 0; n < smp_cpus; n++) {
 216         env = cpu_init(cpu_model);
 217         if (!env) {
 218             fprintf(stderr, "Unable to find CPU definition\n");
 219             exit(1);
 220         }
 221         irqp = arm_pic_init_cpu(env);
 222         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 223         qemu_register_reset(highbank_cpu_reset, env);
 224     }
 225
 226     sysmem = get_system_memory();
 227     dram = g_new(MemoryRegion, 1);
 228     memory_region_init_ram(dram, "highbank.dram", ram_size);
 229     /* SDRAM at address zero.  */
 230     memory_region_add_subregion(sysmem, 0, dram);
 231
 232     sysram = g_new(MemoryRegion, 1);
 233     memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
 234     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 235     if (bios_name != NULL) {
 236         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 237         if (sysboot_filename != NULL) {
 238             uint32_t filesize = get_image_size(sysboot_filename);
 239             if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
 240                 hw_error("Unable to load %s\n", bios_name);
 241             }
 242         } else {
 243            hw_error("Unable to find %s\n", bios_name);
 244         }
 245     }
 246
 247     dev = qdev_create(NULL, "a9mpcore_priv");
 248     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 249     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 250     qdev_init_nofail(dev);
 251     busdev = sysbus_from_qdev(dev);
 252     sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
 253     for (n = 0; n < smp_cpus; n++) {
 254         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 255     }
 256
 257     for (n = 0; n < 128; n++) {
 258         pic[n] = qdev_get_gpio_in(dev, n);
 259     }
 260
 261     dev = qdev_create(NULL, "l2x0");
 262     qdev_init_nofail(dev);
 263     busdev = sysbus_from_qdev(dev);
 264     sysbus_mmio_map(busdev, 0, 0xfff12000);
 265
 266     dev = qdev_create(NULL, "sp804");
 267     qdev_prop_set_uint32(dev, "freq0", 150000000);
 268     qdev_prop_set_uint32(dev, "freq1", 150000000);
 269     qdev_init_nofail(dev);
 270     busdev = sysbus_from_qdev(dev);
 271     sysbus_mmio_map(busdev, 0, 0xfff34000);
 272     sysbus_connect_irq(busdev, 0, pic[18]);
 273     sysbus_create_simple("pl011", 0xfff36000, pic[20]);
 274
 275     dev = qdev_create(NULL, "highbank-regs");
 276     qdev_init_nofail(dev);
 277     busdev = sysbus_from_qdev(dev);
 278     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 279
 280     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 281     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 282     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 283     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 284     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 285     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 286
 287     sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
 288
 289     if (nd_table[0].vlan) {
 290         qemu_check_nic_model(&nd_table[0], "xgmac");
 291         dev = qdev_create(NULL, "xgmac");
 292         qdev_set_nic_properties(dev, &nd_table[0]);
 293         qdev_init_nofail(dev);
 294         sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff50000);
 295         sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[77]);
 296         sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[78]);
 297         sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[79]);
 298
 299         qemu_check_nic_model(&nd_table[1], "xgmac");
 300         dev = qdev_create(NULL, "xgmac");
 301         qdev_set_nic_properties(dev, &nd_table[1]);
 302         qdev_init_nofail(dev);
 303         sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff51000);
 304         sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[80]);
 305         sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[81]);
 306         sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[82]);
 307     }
 308
 309     highbank_binfo.ram_size = ram_size;
 310     highbank_binfo.kernel_filename = kernel_filename;
 311     highbank_binfo.kernel_cmdline = kernel_cmdline;
 312     highbank_binfo.initrd_filename = initrd_filename;
 313     /* highbank requires a dtb in order to boot, and the dtb will override
 314      * the board ID. The following value is ignored, so set it to -1 to be
 315      * clear that the value is meaningless.
 316      */
 317     highbank_binfo.board_id = -1;
 318     highbank_binfo.nb_cpus = smp_cpus;
 319     highbank_binfo.loader_start = 0;
 320     highbank_binfo.write_secondary_boot = hb_write_secondary;
 321     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 322     arm_load_kernel(first_cpu, &highbank_binfo);
 323 }
 324
 325 static QEMUMachine highbank_machine = {
 326     .name = "highbank",
 327     .desc = "Calxeda Highbank (ECX-1000)",
 328     .init = highbank_init,
 329     .use_scsi = 1,
 330     .max_cpus = 4,
 331 };
 332
 333 static void highbank_machine_init(void)
 334 {
 335     qemu_register_machine(&highbank_machine);
 336 }
 337
 338 machine_init(highbank_machine_init);