hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33 #include "mc146818rtc.h"
  34
  35 //#define HPET_DEBUG
  36 #ifdef HPET_DEBUG
  37 #define DPRINTF printf
  38 #else
  39 #define DPRINTF(...)
  40 #endif
  41
  42 #define HPET_MSI_SUPPORT        0
  43
  44 struct HPETState;
  45 typedef struct HPETTimer {  /* timers */
  46     uint8_t tn;             /*timer number*/
  47     QEMUTimer *qemu_timer;
  48     struct HPETState *state;
  49     /* Memory-mapped, software visible timer registers */
  50     uint64_t config;        /* configuration/cap */
  51     uint64_t cmp;           /* comparator */
  52     uint64_t fsb;           /* FSB route */
  53     /* Hidden register state */
  54     uint64_t period;        /* Last value written to comparator */
  55     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  56                              * mode. Next pop will be actual timer expiration.
  57                              */
  58 } HPETTimer;
  59
  60 typedef struct HPETState {
  61     SysBusDevice busdev;
  62     MemoryRegion iomem;
  63     uint64_t hpet_offset;
  64     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  65     uint32_t flags;
  66     uint8_t rtc_irq_level;
  67     uint8_t num_timers;
  68     HPETTimer timer[HPET_MAX_TIMERS];
  69
  70     /* Memory-mapped, software visible registers */
  71     uint64_t capability;        /* capabilities */
  72     uint64_t config;            /* configuration */
  73     uint64_t isr;               /* interrupt status reg */
  74     uint64_t hpet_counter;      /* main counter */
  75     uint8_t  hpet_id;           /* instance id */
  76 } HPETState;
  77
  78 static uint32_t hpet_in_legacy_mode(HPETState *s)
  79 {
  80     return s->config & HPET_CFG_LEGACY;
  81 }
  82
  83 static uint32_t timer_int_route(struct HPETTimer *timer)
  84 {
  85     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  86 }
  87
  88 static uint32_t timer_fsb_route(HPETTimer *t)
  89 {
  90     return t->config & HPET_TN_FSB_ENABLE;
  91 }
  92
  93 static uint32_t hpet_enabled(HPETState *s)
  94 {
  95     return s->config & HPET_CFG_ENABLE;
  96 }
  97
  98 static uint32_t timer_is_periodic(HPETTimer *t)
  99 {
 100     return t->config & HPET_TN_PERIODIC;
 101 }
 102
 103 static uint32_t timer_enabled(HPETTimer *t)
 104 {
 105     return t->config & HPET_TN_ENABLE;
 106 }
 107
 108 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 109 {
 110     return ((int32_t)(b) - (int32_t)(a) < 0);
 111 }
 112
 113 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 114 {
 115     return ((int64_t)(b) - (int64_t)(a) < 0);
 116 }
 117
 118 static uint64_t ticks_to_ns(uint64_t value)
 119 {
 120     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 121 }
 122
 123 static uint64_t ns_to_ticks(uint64_t value)
 124 {
 125     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 126 }
 127
 128 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 129 {
 130     new &= mask;
 131     new |= old & ~mask;
 132     return new;
 133 }
 134
 135 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 136 {
 137     return (!(old & mask) && (new & mask));
 138 }
 139
 140 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 141 {
 142     return ((old & mask) && !(new & mask));
 143 }
 144
 145 static uint64_t hpet_get_ticks(HPETState *s)
 146 {
 147     return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
 148 }
 149
 150 /*
 151  * calculate diff between comparator value and current ticks
 152  */
 153 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 154 {
 155
 156     if (t->config & HPET_TN_32BIT) {
 157         uint32_t diff, cmp;
 158
 159         cmp = (uint32_t)t->cmp;
 160         diff = cmp - (uint32_t)current;
 161         diff = (int32_t)diff > 0 ? diff : (uint32_t)1;
 162         return (uint64_t)diff;
 163     } else {
 164         uint64_t diff, cmp;
 165
 166         cmp = t->cmp;
 167         diff = cmp - current;
 168         diff = (int64_t)diff > 0 ? diff : (uint64_t)1;
 169         return diff;
 170     }
 171 }
 172
 173 static void update_irq(struct HPETTimer *timer, int set)
 174 {
 175     uint64_t mask;
 176     HPETState *s;
 177     int route;
 178
 179     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 180         /* if LegacyReplacementRoute bit is set, HPET specification requires
 181          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 182          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 183          */
 184         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 185     } else {
 186         route = timer_int_route(timer);
 187     }
 188     s = timer->state;
 189     mask = 1 << timer->tn;
 190     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 191         s->isr &= ~mask;
 192         if (!timer_fsb_route(timer)) {
 193             qemu_irq_lower(s->irqs[route]);
 194         }
 195     } else if (timer_fsb_route(timer)) {
 196         stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
 197     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 198         s->isr |= mask;
 199         qemu_irq_raise(s->irqs[route]);
 200     } else {
 201         s->isr &= ~mask;
 202         qemu_irq_pulse(s->irqs[route]);
 203     }
 204 }
 205
 206 static void hpet_pre_save(void *opaque)
 207 {
 208     HPETState *s = opaque;
 209
 210     /* save current counter value */
 211     s->hpet_counter = hpet_get_ticks(s);
 212 }
 213
 214 static int hpet_pre_load(void *opaque)
 215 {
 216     HPETState *s = opaque;
 217
 218     /* version 1 only supports 3, later versions will load the actual value */
 219     s->num_timers = HPET_MIN_TIMERS;
 220     return 0;
 221 }
 222
 223 static int hpet_post_load(void *opaque, int version_id)
 224 {
 225     HPETState *s = opaque;
 226
 227     /* Recalculate the offset between the main counter and guest time */
 228     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
 229
 230     /* Push number of timers into capability returned via HPET_ID */
 231     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 232     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 233     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 234
 235     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 236     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 237     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 238         s->flags |= 1 << HPET_MSI_SUPPORT;
 239     }
 240     return 0;
 241 }
 242
 243 static bool hpet_rtc_irq_level_needed(void *opaque)
 244 {
 245     HPETState *s = opaque;
 246
 247     return s->rtc_irq_level != 0;
 248 }
 249
 250 static const VMStateDescription vmstate_hpet_rtc_irq_level = {
 251     .name = "hpet/rtc_irq_level",
 252     .version_id = 1,
 253     .minimum_version_id = 1,
 254     .minimum_version_id_old = 1,
 255     .fields      = (VMStateField[]) {
 256         VMSTATE_UINT8(rtc_irq_level, HPETState),
 257         VMSTATE_END_OF_LIST()
 258     }
 259 };
 260
 261 static const VMStateDescription vmstate_hpet_timer = {
 262     .name = "hpet_timer",
 263     .version_id = 1,
 264     .minimum_version_id = 1,
 265     .minimum_version_id_old = 1,
 266     .fields      = (VMStateField []) {
 267         VMSTATE_UINT8(tn, HPETTimer),
 268         VMSTATE_UINT64(config, HPETTimer),
 269         VMSTATE_UINT64(cmp, HPETTimer),
 270         VMSTATE_UINT64(fsb, HPETTimer),
 271         VMSTATE_UINT64(period, HPETTimer),
 272         VMSTATE_UINT8(wrap_flag, HPETTimer),
 273         VMSTATE_TIMER(qemu_timer, HPETTimer),
 274         VMSTATE_END_OF_LIST()
 275     }
 276 };
 277
 278 static const VMStateDescription vmstate_hpet = {
 279     .name = "hpet",
 280     .version_id = 2,
 281     .minimum_version_id = 1,
 282     .minimum_version_id_old = 1,
 283     .pre_save = hpet_pre_save,
 284     .pre_load = hpet_pre_load,
 285     .post_load = hpet_post_load,
 286     .fields      = (VMStateField []) {
 287         VMSTATE_UINT64(config, HPETState),
 288         VMSTATE_UINT64(isr, HPETState),
 289         VMSTATE_UINT64(hpet_counter, HPETState),
 290         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 291         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 292                                     vmstate_hpet_timer, HPETTimer),
 293         VMSTATE_END_OF_LIST()
 294     },
 295     .subsections = (VMStateSubsection[]) {
 296         {
 297             .vmsd = &vmstate_hpet_rtc_irq_level,
 298             .needed = hpet_rtc_irq_level_needed,
 299         }, {
 300             /* empty */
 301         }
 302     }
 303 };
 304
 305 /*
 306  * timer expiration callback
 307  */
 308 static void hpet_timer(void *opaque)
 309 {
 310     HPETTimer *t = opaque;
 311     uint64_t diff;
 312
 313     uint64_t period = t->period;
 314     uint64_t cur_tick = hpet_get_ticks(t->state);
 315
 316     if (timer_is_periodic(t) && period != 0) {
 317         if (t->config & HPET_TN_32BIT) {
 318             while (hpet_time_after(cur_tick, t->cmp)) {
 319                 t->cmp = (uint32_t)(t->cmp + t->period);
 320             }
 321         } else {
 322             while (hpet_time_after64(cur_tick, t->cmp)) {
 323                 t->cmp += period;
 324             }
 325         }
 326         diff = hpet_calculate_diff(t, cur_tick);
 327         qemu_mod_timer(t->qemu_timer,
 328                        qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
 329     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 330         if (t->wrap_flag) {
 331             diff = hpet_calculate_diff(t, cur_tick);
 332             qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
 333                            (int64_t)ticks_to_ns(diff));
 334             t->wrap_flag = 0;
 335         }
 336     }
 337     update_irq(t, 1);
 338 }
 339
 340 static void hpet_set_timer(HPETTimer *t)
 341 {
 342     uint64_t diff;
 343     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 344     uint64_t cur_tick = hpet_get_ticks(t->state);
 345
 346     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 347     t->wrap_flag = 0;
 348     diff = hpet_calculate_diff(t, cur_tick);
 349
 350     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 351      * counter wraps in addition to an interrupt with comparator match.
 352      */
 353     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 354         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 355         if (wrap_diff < (uint32_t)diff) {
 356             diff = wrap_diff;
 357             t->wrap_flag = 1;
 358         }
 359     }
 360     qemu_mod_timer(t->qemu_timer,
 361                    qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
 362 }
 363
 364 static void hpet_del_timer(HPETTimer *t)
 365 {
 366     qemu_del_timer(t->qemu_timer);
 367     update_irq(t, 0);
 368 }
 369
 370 #ifdef HPET_DEBUG
 371 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 372 {
 373     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 374     return 0;
 375 }
 376
 377 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 378 {
 379     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 380     return 0;
 381 }
 382 #endif
 383
 384 static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
 385                               unsigned size)
 386 {
 387     HPETState *s = opaque;
 388     uint64_t cur_tick, index;
 389
 390     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 391     index = addr;
 392     /*address range of all TN regs*/
 393     if (index >= 0x100 && index <= 0x3ff) {
 394         uint8_t timer_id = (addr - 0x100) / 0x20;
 395         HPETTimer *timer = &s->timer[timer_id];
 396
 397         if (timer_id > s->num_timers) {
 398             DPRINTF("qemu: timer id out of range\n");
 399             return 0;
 400         }
 401
 402         switch ((addr - 0x100) % 0x20) {
 403         case HPET_TN_CFG:
 404             return timer->config;
 405         case HPET_TN_CFG + 4: // Interrupt capabilities
 406             return timer->config >> 32;
 407         case HPET_TN_CMP: // comparator register
 408             return timer->cmp;
 409         case HPET_TN_CMP + 4:
 410             return timer->cmp >> 32;
 411         case HPET_TN_ROUTE:
 412             return timer->fsb;
 413         case HPET_TN_ROUTE + 4:
 414             return timer->fsb >> 32;
 415         default:
 416             DPRINTF("qemu: invalid hpet_ram_readl\n");
 417             break;
 418         }
 419     } else {
 420         switch (index) {
 421         case HPET_ID:
 422             return s->capability;
 423         case HPET_PERIOD:
 424             return s->capability >> 32;
 425         case HPET_CFG:
 426             return s->config;
 427         case HPET_CFG + 4:
 428             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
 429             return 0;
 430         case HPET_COUNTER:
 431             if (hpet_enabled(s)) {
 432                 cur_tick = hpet_get_ticks(s);
 433             } else {
 434                 cur_tick = s->hpet_counter;
 435             }
 436             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 437             return cur_tick;
 438         case HPET_COUNTER + 4:
 439             if (hpet_enabled(s)) {
 440                 cur_tick = hpet_get_ticks(s);
 441             } else {
 442                 cur_tick = s->hpet_counter;
 443             }
 444             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 445             return cur_tick >> 32;
 446         case HPET_STATUS:
 447             return s->isr;
 448         default:
 449             DPRINTF("qemu: invalid hpet_ram_readl\n");
 450             break;
 451         }
 452     }
 453     return 0;
 454 }
 455
 456 static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
 457                            uint64_t value, unsigned size)
 458 {
 459     int i;
 460     HPETState *s = opaque;
 461     uint64_t old_val, new_val, val, index;
 462
 463     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 464     index = addr;
 465     old_val = hpet_ram_read(opaque, addr, 4);
 466     new_val = value;
 467
 468     /*address range of all TN regs*/
 469     if (index >= 0x100 && index <= 0x3ff) {
 470         uint8_t timer_id = (addr - 0x100) / 0x20;
 471         HPETTimer *timer = &s->timer[timer_id];
 472
 473         DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
 474         if (timer_id > s->num_timers) {
 475             DPRINTF("qemu: timer id out of range\n");
 476             return;
 477         }
 478         switch ((addr - 0x100) % 0x20) {
 479         case HPET_TN_CFG:
 480             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 481             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 482                 update_irq(timer, 0);
 483             }
 484             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 485             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 486             if (new_val & HPET_TN_32BIT) {
 487                 timer->cmp = (uint32_t)timer->cmp;
 488                 timer->period = (uint32_t)timer->period;
 489             }
 490             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 491                 hpet_set_timer(timer);
 492             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 493                 hpet_del_timer(timer);
 494             }
 495             break;
 496         case HPET_TN_CFG + 4: // Interrupt capabilities
 497             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 498             break;
 499         case HPET_TN_CMP: // comparator register
 500             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
 501             if (timer->config & HPET_TN_32BIT) {
 502                 new_val = (uint32_t)new_val;
 503             }
 504             if (!timer_is_periodic(timer)
 505                 || (timer->config & HPET_TN_SETVAL)) {
 506                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 507             }
 508             if (timer_is_periodic(timer)) {
 509                 /*
 510                  * FIXME: Clamp period to reasonable min value?
 511                  * Clamp period to reasonable max value
 512                  */
 513                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 514                 timer->period =
 515                     (timer->period & 0xffffffff00000000ULL) | new_val;
 516             }
 517             timer->config &= ~HPET_TN_SETVAL;
 518             if (hpet_enabled(s)) {
 519                 hpet_set_timer(timer);
 520             }
 521             break;
 522         case HPET_TN_CMP + 4: // comparator register high order
 523             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 524             if (!timer_is_periodic(timer)
 525                 || (timer->config & HPET_TN_SETVAL)) {
 526                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 527             } else {
 528                 /*
 529                  * FIXME: Clamp period to reasonable min value?
 530                  * Clamp period to reasonable max value
 531                  */
 532                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 533                 timer->period =
 534                     (timer->period & 0xffffffffULL) | new_val << 32;
 535                 }
 536                 timer->config &= ~HPET_TN_SETVAL;
 537                 if (hpet_enabled(s)) {
 538                     hpet_set_timer(timer);
 539                 }
 540                 break;
 541         case HPET_TN_ROUTE:
 542             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 543             break;
 544         case HPET_TN_ROUTE + 4:
 545             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 546             break;
 547         default:
 548             DPRINTF("qemu: invalid hpet_ram_writel\n");
 549             break;
 550         }
 551         return;
 552     } else {
 553         switch (index) {
 554         case HPET_ID:
 555             return;
 556         case HPET_CFG:
 557             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 558             s->config = (s->config & 0xffffffff00000000ULL) | val;
 559             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 560                 /* Enable main counter and interrupt generation. */
 561                 s->hpet_offset =
 562                     ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
 563                 for (i = 0; i < s->num_timers; i++) {
 564                     if ((&s->timer[i])->cmp != ~0ULL) {
 565                         hpet_set_timer(&s->timer[i]);
 566                     }
 567                 }
 568             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 569                 /* Halt main counter and disable interrupt generation. */
 570                 s->hpet_counter = hpet_get_ticks(s);
 571                 for (i = 0; i < s->num_timers; i++) {
 572                     hpet_del_timer(&s->timer[i]);
 573                 }
 574             }
 575             /* i8254 and RTC are disabled when HPET is in legacy mode */
 576             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 577                 hpet_pit_disable();
 578                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 579             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 580                 hpet_pit_enable();
 581                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 582             }
 583             break;
 584         case HPET_CFG + 4:
 585             DPRINTF("qemu: invalid HPET_CFG+4 write\n");
 586             break;
 587         case HPET_STATUS:
 588             val = new_val & s->isr;
 589             for (i = 0; i < s->num_timers; i++) {
 590                 if (val & (1 << i)) {
 591                     update_irq(&s->timer[i], 0);
 592                 }
 593             }
 594             break;
 595         case HPET_COUNTER:
 596             if (hpet_enabled(s)) {
 597                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 598             }
 599             s->hpet_counter =
 600                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 601             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 602                     value, s->hpet_counter);
 603             break;
 604         case HPET_COUNTER + 4:
 605             if (hpet_enabled(s)) {
 606                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 607             }
 608             s->hpet_counter =
 609                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 610             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 611                     value, s->hpet_counter);
 612             break;
 613         default:
 614             DPRINTF("qemu: invalid hpet_ram_writel\n");
 615             break;
 616         }
 617     }
 618 }
 619
 620 static const MemoryRegionOps hpet_ram_ops = {
 621     .read = hpet_ram_read,
 622     .write = hpet_ram_write,
 623     .valid = {
 624         .min_access_size = 4,
 625         .max_access_size = 4,
 626     },
 627     .endianness = DEVICE_NATIVE_ENDIAN,
 628 };
 629
 630 static void hpet_reset(DeviceState *d)
 631 {
 632     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 633     int i;
 634     static int count = 0;
 635
 636     for (i = 0; i < s->num_timers; i++) {
 637         HPETTimer *timer = &s->timer[i];
 638
 639         hpet_del_timer(timer);
 640         timer->cmp = ~0ULL;
 641         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 642         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 643             timer->config |= HPET_TN_FSB_CAP;
 644         }
 645         /* advertise availability of ioapic inti2 */
 646         timer->config |=  0x00000004ULL << 32;
 647         timer->period = 0ULL;
 648         timer->wrap_flag = 0;
 649     }
 650
 651     s->hpet_counter = 0ULL;
 652     s->hpet_offset = 0ULL;
 653     s->config = 0ULL;
 654     if (count > 0) {
 655         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 656          * because hpet is taking over for pit here. On subsequent invocations,
 657          * hpet_reset is called due to system reset. At this point control must
 658          * be returned to pit until SW reenables hpet.
 659          */
 660         hpet_pit_enable();
 661     }
 662     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 663     hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
 664     count = 1;
 665
 666     /* to document that the RTC lowers its output on reset as well */
 667     s->rtc_irq_level = 0;
 668 }
 669
 670 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
 671 {
 672     HPETState *s = FROM_SYSBUS(HPETState, opaque);
 673
 674     s->rtc_irq_level = level;
 675     if (!hpet_in_legacy_mode(s)) {
 676         qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 677     }
 678 }
 679
 680 static int hpet_init(SysBusDevice *dev)
 681 {
 682     HPETState *s = FROM_SYSBUS(HPETState, dev);
 683     int i;
 684     HPETTimer *timer;
 685
 686     if (hpet_cfg.count == UINT8_MAX) {
 687         /* first instance */
 688         hpet_cfg.count = 0;
 689     }
 690
 691     if (hpet_cfg.count == 8) {
 692         fprintf(stderr, "Only 8 instances of HPET is allowed\n");
 693         return -1;
 694     }
 695
 696     s->hpet_id = hpet_cfg.count++;
 697
 698     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 699         sysbus_init_irq(dev, &s->irqs[i]);
 700     }
 701
 702     if (s->num_timers < HPET_MIN_TIMERS) {
 703         s->num_timers = HPET_MIN_TIMERS;
 704     } else if (s->num_timers > HPET_MAX_TIMERS) {
 705         s->num_timers = HPET_MAX_TIMERS;
 706     }
 707     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 708         timer = &s->timer[i];
 709         timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
 710         timer->tn = i;
 711         timer->state = s;
 712     }
 713
 714     /* 64-bit main counter; LegacyReplacementRoute. */
 715     s->capability = 0x8086a001ULL;
 716     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 717     s->capability |= ((HPET_CLK_PERIOD) << 32);
 718
 719     qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
 720
 721     /* HPET Area */
 722     memory_region_init_io(&s->iomem, &hpet_ram_ops, s, "hpet", 0x400);
 723     sysbus_init_mmio(dev, &s->iomem);
 724     return 0;
 725 }
 726
 727 static Property hpet_device_properties[] = {
 728     DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 729     DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 730     DEFINE_PROP_END_OF_LIST(),
 731 };
 732
 733 static void hpet_device_class_init(ObjectClass *klass, void *data)
 734 {
 735     DeviceClass *dc = DEVICE_CLASS(klass);
 736     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 737
 738     k->init = hpet_init;
 739     dc->no_user = 1;
 740     dc->reset = hpet_reset;
 741     dc->vmsd = &vmstate_hpet;
 742     dc->props = hpet_device_properties;
 743 }
 744
 745 static TypeInfo hpet_device_info = {
 746     .name          = "hpet",
 747     .parent        = TYPE_SYS_BUS_DEVICE,
 748     .instance_size = sizeof(HPETState),
 749     .class_init    = hpet_device_class_init,
 750 };
 751
 752 static void hpet_register_types(void)
 753 {
 754     type_register_static(&hpet_device_info);
 755 }
 756
 757 type_init(hpet_register_types)