hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32
  33 //#define HPET_DEBUG
  34 #ifdef HPET_DEBUG
  35 #define DPRINTF printf
  36 #else
  37 #define DPRINTF(...)
  38 #endif
  39
  40 struct HPETState;
  41 typedef struct HPETTimer {  /* timers */
  42     uint8_t tn;             /*timer number*/
  43     QEMUTimer *qemu_timer;
  44     struct HPETState *state;
  45     /* Memory-mapped, software visible timer registers */
  46     uint64_t config;        /* configuration/cap */
  47     uint64_t cmp;           /* comparator */
  48     uint64_t fsb;           /* FSB route, not supported now */
  49     /* Hidden register state */
  50     uint64_t period;        /* Last value written to comparator */
  51     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  52                              * mode. Next pop will be actual timer expiration.
  53                              */
  54 } HPETTimer;
  55
  56 typedef struct HPETState {
  57     uint64_t hpet_offset;
  58     qemu_irq *irqs;
  59     HPETTimer timer[HPET_NUM_TIMERS];
  60
  61     /* Memory-mapped, software visible registers */
  62     uint64_t capability;        /* capabilities */
  63     uint64_t config;            /* configuration */
  64     uint64_t isr;               /* interrupt status reg */
  65     uint64_t hpet_counter;      /* main counter */
  66 } HPETState;
  67
  68 static HPETState *hpet_statep;
  69
  70 uint32_t hpet_in_legacy_mode(void)
  71 {
  72     if (!hpet_statep) {
  73         return 0;
  74     }
  75     return hpet_statep->config & HPET_CFG_LEGACY;
  76 }
  77
  78 static uint32_t timer_int_route(struct HPETTimer *timer)
  79 {
  80     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  81 }
  82
  83 static uint32_t hpet_enabled(void)
  84 {
  85     return hpet_statep->config & HPET_CFG_ENABLE;
  86 }
  87
  88 static uint32_t timer_is_periodic(HPETTimer *t)
  89 {
  90     return t->config & HPET_TN_PERIODIC;
  91 }
  92
  93 static uint32_t timer_enabled(HPETTimer *t)
  94 {
  95     return t->config & HPET_TN_ENABLE;
  96 }
  97
  98 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
  99 {
 100     return ((int32_t)(b) - (int32_t)(a) < 0);
 101 }
 102
 103 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 104 {
 105     return ((int64_t)(b) - (int64_t)(a) < 0);
 106 }
 107
 108 static uint64_t ticks_to_ns(uint64_t value)
 109 {
 110     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 111 }
 112
 113 static uint64_t ns_to_ticks(uint64_t value)
 114 {
 115     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 116 }
 117
 118 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 119 {
 120     new &= mask;
 121     new |= old & ~mask;
 122     return new;
 123 }
 124
 125 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 126 {
 127     return (!(old & mask) && (new & mask));
 128 }
 129
 130 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 131 {
 132     return ((old & mask) && !(new & mask));
 133 }
 134
 135 static uint64_t hpet_get_ticks(void)
 136 {
 137     return ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
 138 }
 139
 140 /*
 141  * calculate diff between comparator value and current ticks
 142  */
 143 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 144 {
 145
 146     if (t->config & HPET_TN_32BIT) {
 147         uint32_t diff, cmp;
 148
 149         cmp = (uint32_t)t->cmp;
 150         diff = cmp - (uint32_t)current;
 151         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 152         return (uint64_t)diff;
 153     } else {
 154         uint64_t diff, cmp;
 155
 156         cmp = t->cmp;
 157         diff = cmp - current;
 158         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 159         return diff;
 160     }
 161 }
 162
 163 static void update_irq(struct HPETTimer *timer)
 164 {
 165     int route;
 166
 167     if (timer->tn <= 1 && hpet_in_legacy_mode()) {
 168         /* if LegacyReplacementRoute bit is set, HPET specification requires
 169          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 170          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 171          */
 172         route = (timer->tn == 0) ? 0 : 8;
 173     } else {
 174         route = timer_int_route(timer);
 175     }
 176     if (!timer_enabled(timer) || !hpet_enabled()) {
 177         return;
 178     }
 179     qemu_irq_pulse(timer->state->irqs[route]);
 180 }
 181
 182 static void hpet_pre_save(void *opaque)
 183 {
 184     HPETState *s = opaque;
 185
 186     /* save current counter value */
 187     s->hpet_counter = hpet_get_ticks();
 188 }
 189
 190 static int hpet_post_load(void *opaque, int version_id)
 191 {
 192     HPETState *s = opaque;
 193
 194     /* Recalculate the offset between the main counter and guest time */
 195     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 196     return 0;
 197 }
 198
 199 static const VMStateDescription vmstate_hpet_timer = {
 200     .name = "hpet_timer",
 201     .version_id = 1,
 202     .minimum_version_id = 1,
 203     .minimum_version_id_old = 1,
 204     .fields      = (VMStateField []) {
 205         VMSTATE_UINT8(tn, HPETTimer),
 206         VMSTATE_UINT64(config, HPETTimer),
 207         VMSTATE_UINT64(cmp, HPETTimer),
 208         VMSTATE_UINT64(fsb, HPETTimer),
 209         VMSTATE_UINT64(period, HPETTimer),
 210         VMSTATE_UINT8(wrap_flag, HPETTimer),
 211         VMSTATE_TIMER(qemu_timer, HPETTimer),
 212         VMSTATE_END_OF_LIST()
 213     }
 214 };
 215
 216 static const VMStateDescription vmstate_hpet = {
 217     .name = "hpet",
 218     .version_id = 1,
 219     .minimum_version_id = 1,
 220     .minimum_version_id_old = 1,
 221     .pre_save = hpet_pre_save,
 222     .post_load = hpet_post_load,
 223     .fields      = (VMStateField []) {
 224         VMSTATE_UINT64(config, HPETState),
 225         VMSTATE_UINT64(isr, HPETState),
 226         VMSTATE_UINT64(hpet_counter, HPETState),
 227         VMSTATE_STRUCT_ARRAY(timer, HPETState, HPET_NUM_TIMERS, 0,
 228                              vmstate_hpet_timer, HPETTimer),
 229         VMSTATE_END_OF_LIST()
 230     }
 231 };
 232
 233 /*
 234  * timer expiration callback
 235  */
 236 static void hpet_timer(void *opaque)
 237 {
 238     HPETTimer *t = opaque;
 239     uint64_t diff;
 240
 241     uint64_t period = t->period;
 242     uint64_t cur_tick = hpet_get_ticks();
 243
 244     if (timer_is_periodic(t) && period != 0) {
 245         if (t->config & HPET_TN_32BIT) {
 246             while (hpet_time_after(cur_tick, t->cmp)) {
 247                 t->cmp = (uint32_t)(t->cmp + t->period);
 248             }
 249         } else {
 250             while (hpet_time_after64(cur_tick, t->cmp)) {
 251                 t->cmp += period;
 252             }
 253         }
 254         diff = hpet_calculate_diff(t, cur_tick);
 255         qemu_mod_timer(t->qemu_timer,
 256                        qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 257     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 258         if (t->wrap_flag) {
 259             diff = hpet_calculate_diff(t, cur_tick);
 260             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
 261                            (int64_t)ticks_to_ns(diff));
 262             t->wrap_flag = 0;
 263         }
 264     }
 265     update_irq(t);
 266 }
 267
 268 static void hpet_set_timer(HPETTimer *t)
 269 {
 270     uint64_t diff;
 271     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 272     uint64_t cur_tick = hpet_get_ticks();
 273
 274     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 275     t->wrap_flag = 0;
 276     diff = hpet_calculate_diff(t, cur_tick);
 277
 278     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 279      * counter wraps in addition to an interrupt with comparator match.
 280      */
 281     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 282         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 283         if (wrap_diff < (uint32_t)diff) {
 284             diff = wrap_diff;
 285             t->wrap_flag = 1;
 286         }
 287     }
 288     qemu_mod_timer(t->qemu_timer,
 289                    qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 290 }
 291
 292 static void hpet_del_timer(HPETTimer *t)
 293 {
 294     qemu_del_timer(t->qemu_timer);
 295 }
 296
 297 #ifdef HPET_DEBUG
 298 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 299 {
 300     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 301     return 0;
 302 }
 303
 304 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 305 {
 306     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 307     return 0;
 308 }
 309 #endif
 310
 311 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 312 {
 313     HPETState *s = opaque;
 314     uint64_t cur_tick, index;
 315
 316     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 317     index = addr;
 318     /*address range of all TN regs*/
 319     if (index >= 0x100 && index <= 0x3ff) {
 320         uint8_t timer_id = (addr - 0x100) / 0x20;
 321         HPETTimer *timer = &s->timer[timer_id];
 322
 323         if (timer_id > HPET_NUM_TIMERS - 1) {
 324             DPRINTF("qemu: timer id out of range\n");
 325             return 0;
 326         }
 327
 328         switch ((addr - 0x100) % 0x20) {
 329         case HPET_TN_CFG:
 330             return timer->config;
 331         case HPET_TN_CFG + 4: // Interrupt capabilities
 332             return timer->config >> 32;
 333         case HPET_TN_CMP: // comparator register
 334             return timer->cmp;
 335         case HPET_TN_CMP + 4:
 336             return timer->cmp >> 32;
 337         case HPET_TN_ROUTE:
 338             return timer->fsb >> 32;
 339         default:
 340             DPRINTF("qemu: invalid hpet_ram_readl\n");
 341             break;
 342         }
 343     } else {
 344         switch (index) {
 345         case HPET_ID:
 346             return s->capability;
 347         case HPET_PERIOD:
 348             return s->capability >> 32;
 349         case HPET_CFG:
 350             return s->config;
 351         case HPET_CFG + 4:
 352             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 353             return 0;
 354         case HPET_COUNTER:
 355             if (hpet_enabled()) {
 356                 cur_tick = hpet_get_ticks();
 357             } else {
 358                 cur_tick = s->hpet_counter;
 359             }
 360             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 361             return cur_tick;
 362         case HPET_COUNTER + 4:
 363             if (hpet_enabled()) {
 364                 cur_tick = hpet_get_ticks();
 365             } else {
 366                 cur_tick = s->hpet_counter;
 367             }
 368             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 369             return cur_tick >> 32;
 370         case HPET_STATUS:
 371             return s->isr;
 372         default:
 373             DPRINTF("qemu: invalid hpet_ram_readl\n");
 374             break;
 375         }
 376     }
 377     return 0;
 378 }
 379
 380 #ifdef HPET_DEBUG
 381 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 382                             uint32_t value)
 383 {
 384     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 385            addr, value);
 386 }
 387
 388 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 389                             uint32_t value)
 390 {
 391     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 392            addr, value);
 393 }
 394 #endif
 395
 396 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 397                             uint32_t value)
 398 {
 399     int i;
 400     HPETState *s = opaque;
 401     uint64_t old_val, new_val, val, index;
 402
 403     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 404     index = addr;
 405     old_val = hpet_ram_readl(opaque, addr);
 406     new_val = value;
 407
 408     /*address range of all TN regs*/
 409     if (index >= 0x100 && index <= 0x3ff) {
 410         uint8_t timer_id = (addr - 0x100) / 0x20;
 411         HPETTimer *timer = &s->timer[timer_id];
 412
 413         DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 414         if (timer_id > HPET_NUM_TIMERS - 1) {
 415             DPRINTF("qemu: timer id out of range\n");
 416             return;
 417         }
 418         switch ((addr - 0x100) % 0x20) {
 419         case HPET_TN_CFG:
 420             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 421             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 422             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 423             if (new_val & HPET_TN_32BIT) {
 424                 timer->cmp = (uint32_t)timer->cmp;
 425                 timer->period = (uint32_t)timer->period;
 426             }
 427             if (new_val & HPET_TN_TYPE_LEVEL) {
 428                 printf("qemu: level-triggered hpet not supported\n");
 429                 exit (-1);
 430             }
 431             break;
 432         case HPET_TN_CFG + 4: // Interrupt capabilities
 433             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 434             break;
 435         case HPET_TN_CMP: // comparator register
 436             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
 437             if (timer->config & HPET_TN_32BIT) {
 438                 new_val = (uint32_t)new_val;
 439             }
 440             if (!timer_is_periodic(timer)
 441                 || (timer->config & HPET_TN_SETVAL)) {
 442                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 443             }
 444             if (timer_is_periodic(timer)) {
 445                 /*
 446                  * FIXME: Clamp period to reasonable min value?
 447                  * Clamp period to reasonable max value
 448                  */
 449                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 450                 timer->period =
 451                     (timer->period & 0xffffffff00000000ULL) | new_val;
 452             }
 453             timer->config &= ~HPET_TN_SETVAL;
 454             if (hpet_enabled()) {
 455                 hpet_set_timer(timer);
 456             }
 457             break;
 458         case HPET_TN_CMP + 4: // comparator register high order
 459             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 460             if (!timer_is_periodic(timer)
 461                 || (timer->config & HPET_TN_SETVAL)) {
 462                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 463             } else {
 464                 /*
 465                  * FIXME: Clamp period to reasonable min value?
 466                  * Clamp period to reasonable max value
 467                  */
 468                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 469                 timer->period =
 470                     (timer->period & 0xffffffffULL) | new_val << 32;
 471                 }
 472                 timer->config &= ~HPET_TN_SETVAL;
 473                 if (hpet_enabled()) {
 474                     hpet_set_timer(timer);
 475                 }
 476                 break;
 477         case HPET_TN_ROUTE + 4:
 478             DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
 479             break;
 480         default:
 481             DPRINTF("qemu: invalid hpet_ram_writel\n");
 482             break;
 483         }
 484         return;
 485     } else {
 486         switch (index) {
 487         case HPET_ID:
 488             return;
 489         case HPET_CFG:
 490             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 491             s->config = (s->config & 0xffffffff00000000ULL) | val;
 492             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 493                 /* Enable main counter and interrupt generation. */
 494                 s->hpet_offset =
 495                     ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 496                 for (i = 0; i < HPET_NUM_TIMERS; i++) {
 497                     if ((&s->timer[i])->cmp != ~0ULL) {
 498                         hpet_set_timer(&s->timer[i]);
 499                     }
 500                 }
 501             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 502                 /* Halt main counter and disable interrupt generation. */
 503                 s->hpet_counter = hpet_get_ticks();
 504                 for (i = 0; i < HPET_NUM_TIMERS; i++) {
 505                     hpet_del_timer(&s->timer[i]);
 506                 }
 507             }
 508             /* i8254 and RTC are disabled when HPET is in legacy mode */
 509             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 510                 hpet_pit_disable();
 511             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 512                 hpet_pit_enable();
 513             }
 514             break;
 515         case HPET_CFG + 4:
 516             DPRINTF("qemu: invalid HPET_CFG+4 write \n");
 517             break;
 518         case HPET_STATUS:
 519             /* FIXME: need to handle level-triggered interrupts */
 520             break;
 521         case HPET_COUNTER:
 522             if (hpet_enabled()) {
 523                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 524             }
 525             s->hpet_counter =
 526                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 527             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 528                     value, s->hpet_counter);
 529             break;
 530         case HPET_COUNTER + 4:
 531             if (hpet_enabled()) {
 532                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 533             }
 534             s->hpet_counter =
 535                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 536             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 537                     value, s->hpet_counter);
 538             break;
 539         default:
 540             DPRINTF("qemu: invalid hpet_ram_writel\n");
 541             break;
 542         }
 543     }
 544 }
 545
 546 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 547 #ifdef HPET_DEBUG
 548     hpet_ram_readb,
 549     hpet_ram_readw,
 550 #else
 551     NULL,
 552     NULL,
 553 #endif
 554     hpet_ram_readl,
 555 };
 556
 557 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 558 #ifdef HPET_DEBUG
 559     hpet_ram_writeb,
 560     hpet_ram_writew,
 561 #else
 562     NULL,
 563     NULL,
 564 #endif
 565     hpet_ram_writel,
 566 };
 567
 568 static void hpet_reset(void *opaque)
 569 {
 570     HPETState *s = opaque;
 571     int i;
 572     static int count = 0;
 573
 574     for (i = 0; i < HPET_NUM_TIMERS; i++) {
 575         HPETTimer *timer = &s->timer[i];
 576
 577         hpet_del_timer(timer);
 578         timer->cmp = ~0ULL;
 579         timer->config =  HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 580         /* advertise availability of ioapic inti2 */
 581         timer->config |=  0x00000004ULL << 32;
 582         timer->period = 0ULL;
 583         timer->wrap_flag = 0;
 584     }
 585
 586     s->hpet_counter = 0ULL;
 587     s->hpet_offset = 0ULL;
 588     /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
 589     s->capability = 0x8086a201ULL;
 590     s->capability |= ((HPET_CLK_PERIOD) << 32);
 591     s->config = 0ULL;
 592     if (count > 0) {
 593         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 594          * because hpet is taking over for pit here. On subsequent invocations,
 595          * hpet_reset is called due to system reset. At this point control must
 596          * be returned to pit until SW reenables hpet.
 597          */
 598         hpet_pit_enable();
 599     }
 600     count = 1;
 601 }
 602
 603
 604 void hpet_init(qemu_irq *irq)
 605 {
 606     int i, iomemtype;
 607     HPETTimer *timer;
 608     HPETState *s;
 609
 610     DPRINTF ("hpet_init\n");
 611
 612     s = qemu_mallocz(sizeof(HPETState));
 613     hpet_statep = s;
 614     s->irqs = irq;
 615     for (i = 0; i < HPET_NUM_TIMERS; i++) {
 616         timer = &s->timer[i];
 617         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 618         timer->tn = i;
 619         timer->state = s;
 620     }
 621     vmstate_register(-1, &vmstate_hpet, s);
 622     qemu_register_reset(hpet_reset, s);
 623     /* HPET Area */
 624     iomemtype = cpu_register_io_memory(hpet_ram_read,
 625                                        hpet_ram_write, s);
 626     cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
 627 }