hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33 #include "mc146818rtc.h"
  34
  35 //#define HPET_DEBUG
  36 #ifdef HPET_DEBUG
  37 #define DPRINTF printf
  38 #else
  39 #define DPRINTF(...)
  40 #endif
  41
  42 #define HPET_MSI_SUPPORT        0
  43
  44 struct HPETState;
  45 typedef struct HPETTimer {  /* timers */
  46     uint8_t tn;             /*timer number*/
  47     QEMUTimer *qemu_timer;
  48     struct HPETState *state;
  49     /* Memory-mapped, software visible timer registers */
  50     uint64_t config;        /* configuration/cap */
  51     uint64_t cmp;           /* comparator */
  52     uint64_t fsb;           /* FSB route */
  53     /* Hidden register state */
  54     uint64_t period;        /* Last value written to comparator */
  55     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  56                              * mode. Next pop will be actual timer expiration.
  57                              */
  58 } HPETTimer;
  59
  60 typedef struct HPETState {
  61     SysBusDevice busdev;
  62     uint64_t hpet_offset;
  63     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  64     uint32_t flags;
  65     uint8_t rtc_irq_level;
  66     uint8_t num_timers;
  67     HPETTimer timer[HPET_MAX_TIMERS];
  68
  69     /* Memory-mapped, software visible registers */
  70     uint64_t capability;        /* capabilities */
  71     uint64_t config;            /* configuration */
  72     uint64_t isr;               /* interrupt status reg */
  73     uint64_t hpet_counter;      /* main counter */
  74 } HPETState;
  75
  76 static uint32_t hpet_in_legacy_mode(HPETState *s)
  77 {
  78     return s->config & HPET_CFG_LEGACY;
  79 }
  80
  81 static uint32_t timer_int_route(struct HPETTimer *timer)
  82 {
  83     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  84 }
  85
  86 static uint32_t timer_fsb_route(HPETTimer *t)
  87 {
  88     return t->config & HPET_TN_FSB_ENABLE;
  89 }
  90
  91 static uint32_t hpet_enabled(HPETState *s)
  92 {
  93     return s->config & HPET_CFG_ENABLE;
  94 }
  95
  96 static uint32_t timer_is_periodic(HPETTimer *t)
  97 {
  98     return t->config & HPET_TN_PERIODIC;
  99 }
 100
 101 static uint32_t timer_enabled(HPETTimer *t)
 102 {
 103     return t->config & HPET_TN_ENABLE;
 104 }
 105
 106 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 107 {
 108     return ((int32_t)(b) - (int32_t)(a) < 0);
 109 }
 110
 111 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 112 {
 113     return ((int64_t)(b) - (int64_t)(a) < 0);
 114 }
 115
 116 static uint64_t ticks_to_ns(uint64_t value)
 117 {
 118     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 119 }
 120
 121 static uint64_t ns_to_ticks(uint64_t value)
 122 {
 123     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 124 }
 125
 126 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 127 {
 128     new &= mask;
 129     new |= old & ~mask;
 130     return new;
 131 }
 132
 133 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 134 {
 135     return (!(old & mask) && (new & mask));
 136 }
 137
 138 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 139 {
 140     return ((old & mask) && !(new & mask));
 141 }
 142
 143 static uint64_t hpet_get_ticks(HPETState *s)
 144 {
 145     return ns_to_ticks(qemu_get_clock(vm_clock) + s->hpet_offset);
 146 }
 147
 148 /*
 149  * calculate diff between comparator value and current ticks
 150  */
 151 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 152 {
 153
 154     if (t->config & HPET_TN_32BIT) {
 155         uint32_t diff, cmp;
 156
 157         cmp = (uint32_t)t->cmp;
 158         diff = cmp - (uint32_t)current;
 159         diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
 160         return (uint64_t)diff;
 161     } else {
 162         uint64_t diff, cmp;
 163
 164         cmp = t->cmp;
 165         diff = cmp - current;
 166         diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
 167         return diff;
 168     }
 169 }
 170
 171 static void update_irq(struct HPETTimer *timer, int set)
 172 {
 173     uint64_t mask;
 174     HPETState *s;
 175     int route;
 176
 177     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 178         /* if LegacyReplacementRoute bit is set, HPET specification requires
 179          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 180          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 181          */
 182         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 183     } else {
 184         route = timer_int_route(timer);
 185     }
 186     s = timer->state;
 187     mask = 1 << timer->tn;
 188     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 189         s->isr &= ~mask;
 190         if (!timer_fsb_route(timer)) {
 191             qemu_irq_lower(s->irqs[route]);
 192         }
 193     } else if (timer_fsb_route(timer)) {
 194         stl_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
 195     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 196         s->isr |= mask;
 197         qemu_irq_raise(s->irqs[route]);
 198     } else {
 199         s->isr &= ~mask;
 200         qemu_irq_pulse(s->irqs[route]);
 201     }
 202 }
 203
 204 static void hpet_pre_save(void *opaque)
 205 {
 206     HPETState *s = opaque;
 207
 208     /* save current counter value */
 209     s->hpet_counter = hpet_get_ticks(s);
 210 }
 211
 212 static int hpet_pre_load(void *opaque)
 213 {
 214     HPETState *s = opaque;
 215
 216     /* version 1 only supports 3, later versions will load the actual value */
 217     s->num_timers = HPET_MIN_TIMERS;
 218     return 0;
 219 }
 220
 221 static int hpet_post_load(void *opaque, int version_id)
 222 {
 223     HPETState *s = opaque;
 224
 225     /* Recalculate the offset between the main counter and guest time */
 226     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 227
 228     /* Push number of timers into capability returned via HPET_ID */
 229     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 230     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 231
 232     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 233     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 234     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 235         s->flags |= 1 << HPET_MSI_SUPPORT;
 236     }
 237     return 0;
 238 }
 239
 240 static const VMStateDescription vmstate_hpet_timer = {
 241     .name = "hpet_timer",
 242     .version_id = 1,
 243     .minimum_version_id = 1,
 244     .minimum_version_id_old = 1,
 245     .fields      = (VMStateField []) {
 246         VMSTATE_UINT8(tn, HPETTimer),
 247         VMSTATE_UINT64(config, HPETTimer),
 248         VMSTATE_UINT64(cmp, HPETTimer),
 249         VMSTATE_UINT64(fsb, HPETTimer),
 250         VMSTATE_UINT64(period, HPETTimer),
 251         VMSTATE_UINT8(wrap_flag, HPETTimer),
 252         VMSTATE_TIMER(qemu_timer, HPETTimer),
 253         VMSTATE_END_OF_LIST()
 254     }
 255 };
 256
 257 static const VMStateDescription vmstate_hpet = {
 258     .name = "hpet",
 259     .version_id = 2,
 260     .minimum_version_id = 1,
 261     .minimum_version_id_old = 1,
 262     .pre_save = hpet_pre_save,
 263     .pre_load = hpet_pre_load,
 264     .post_load = hpet_post_load,
 265     .fields      = (VMStateField []) {
 266         VMSTATE_UINT64(config, HPETState),
 267         VMSTATE_UINT64(isr, HPETState),
 268         VMSTATE_UINT64(hpet_counter, HPETState),
 269         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 270         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 271                                     vmstate_hpet_timer, HPETTimer),
 272         VMSTATE_END_OF_LIST()
 273     }
 274 };
 275
 276 /*
 277  * timer expiration callback
 278  */
 279 static void hpet_timer(void *opaque)
 280 {
 281     HPETTimer *t = opaque;
 282     uint64_t diff;
 283
 284     uint64_t period = t->period;
 285     uint64_t cur_tick = hpet_get_ticks(t->state);
 286
 287     if (timer_is_periodic(t) && period != 0) {
 288         if (t->config & HPET_TN_32BIT) {
 289             while (hpet_time_after(cur_tick, t->cmp)) {
 290                 t->cmp = (uint32_t)(t->cmp + t->period);
 291             }
 292         } else {
 293             while (hpet_time_after64(cur_tick, t->cmp)) {
 294                 t->cmp += period;
 295             }
 296         }
 297         diff = hpet_calculate_diff(t, cur_tick);
 298         qemu_mod_timer(t->qemu_timer,
 299                        qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 300     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 301         if (t->wrap_flag) {
 302             diff = hpet_calculate_diff(t, cur_tick);
 303             qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) +
 304                            (int64_t)ticks_to_ns(diff));
 305             t->wrap_flag = 0;
 306         }
 307     }
 308     update_irq(t, 1);
 309 }
 310
 311 static void hpet_set_timer(HPETTimer *t)
 312 {
 313     uint64_t diff;
 314     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 315     uint64_t cur_tick = hpet_get_ticks(t->state);
 316
 317     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 318     t->wrap_flag = 0;
 319     diff = hpet_calculate_diff(t, cur_tick);
 320
 321     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 322      * counter wraps in addition to an interrupt with comparator match.
 323      */
 324     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 325         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 326         if (wrap_diff < (uint32_t)diff) {
 327             diff = wrap_diff;
 328             t->wrap_flag = 1;
 329         }
 330     }
 331     qemu_mod_timer(t->qemu_timer,
 332                    qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff));
 333 }
 334
 335 static void hpet_del_timer(HPETTimer *t)
 336 {
 337     qemu_del_timer(t->qemu_timer);
 338     update_irq(t, 0);
 339 }
 340
 341 #ifdef HPET_DEBUG
 342 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 343 {
 344     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 345     return 0;
 346 }
 347
 348 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 349 {
 350     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 351     return 0;
 352 }
 353 #endif
 354
 355 static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
 356 {
 357     HPETState *s = opaque;
 358     uint64_t cur_tick, index;
 359
 360     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 361     index = addr;
 362     /*address range of all TN regs*/
 363     if (index >= 0x100 && index <= 0x3ff) {
 364         uint8_t timer_id = (addr - 0x100) / 0x20;
 365         HPETTimer *timer = &s->timer[timer_id];
 366
 367         if (timer_id > s->num_timers) {
 368             DPRINTF("qemu: timer id out of range\n");
 369             return 0;
 370         }
 371
 372         switch ((addr - 0x100) % 0x20) {
 373         case HPET_TN_CFG:
 374             return timer->config;
 375         case HPET_TN_CFG + 4: // Interrupt capabilities
 376             return timer->config >> 32;
 377         case HPET_TN_CMP: // comparator register
 378             return timer->cmp;
 379         case HPET_TN_CMP + 4:
 380             return timer->cmp >> 32;
 381         case HPET_TN_ROUTE:
 382             return timer->fsb;
 383         case HPET_TN_ROUTE + 4:
 384             return timer->fsb >> 32;
 385         default:
 386             DPRINTF("qemu: invalid hpet_ram_readl\n");
 387             break;
 388         }
 389     } else {
 390         switch (index) {
 391         case HPET_ID:
 392             return s->capability;
 393         case HPET_PERIOD:
 394             return s->capability >> 32;
 395         case HPET_CFG:
 396             return s->config;
 397         case HPET_CFG + 4:
 398             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
 399             return 0;
 400         case HPET_COUNTER:
 401             if (hpet_enabled(s)) {
 402                 cur_tick = hpet_get_ticks(s);
 403             } else {
 404                 cur_tick = s->hpet_counter;
 405             }
 406             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 407             return cur_tick;
 408         case HPET_COUNTER + 4:
 409             if (hpet_enabled(s)) {
 410                 cur_tick = hpet_get_ticks(s);
 411             } else {
 412                 cur_tick = s->hpet_counter;
 413             }
 414             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 415             return cur_tick >> 32;
 416         case HPET_STATUS:
 417             return s->isr;
 418         default:
 419             DPRINTF("qemu: invalid hpet_ram_readl\n");
 420             break;
 421         }
 422     }
 423     return 0;
 424 }
 425
 426 #ifdef HPET_DEBUG
 427 static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
 428                             uint32_t value)
 429 {
 430     printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
 431            addr, value);
 432 }
 433
 434 static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
 435                             uint32_t value)
 436 {
 437     printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
 438            addr, value);
 439 }
 440 #endif
 441
 442 static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
 443                             uint32_t value)
 444 {
 445     int i;
 446     HPETState *s = opaque;
 447     uint64_t old_val, new_val, val, index;
 448
 449     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 450     index = addr;
 451     old_val = hpet_ram_readl(opaque, addr);
 452     new_val = value;
 453
 454     /*address range of all TN regs*/
 455     if (index >= 0x100 && index <= 0x3ff) {
 456         uint8_t timer_id = (addr - 0x100) / 0x20;
 457         HPETTimer *timer = &s->timer[timer_id];
 458
 459         DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
 460         if (timer_id > s->num_timers) {
 461             DPRINTF("qemu: timer id out of range\n");
 462             return;
 463         }
 464         switch ((addr - 0x100) % 0x20) {
 465         case HPET_TN_CFG:
 466             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 467             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 468                 update_irq(timer, 0);
 469             }
 470             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 471             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 472             if (new_val & HPET_TN_32BIT) {
 473                 timer->cmp = (uint32_t)timer->cmp;
 474                 timer->period = (uint32_t)timer->period;
 475             }
 476             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 477                 hpet_set_timer(timer);
 478             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 479                 hpet_del_timer(timer);
 480             }
 481             break;
 482         case HPET_TN_CFG + 4: // Interrupt capabilities
 483             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 484             break;
 485         case HPET_TN_CMP: // comparator register
 486             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
 487             if (timer->config & HPET_TN_32BIT) {
 488                 new_val = (uint32_t)new_val;
 489             }
 490             if (!timer_is_periodic(timer)
 491                 || (timer->config & HPET_TN_SETVAL)) {
 492                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 493             }
 494             if (timer_is_periodic(timer)) {
 495                 /*
 496                  * FIXME: Clamp period to reasonable min value?
 497                  * Clamp period to reasonable max value
 498                  */
 499                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 500                 timer->period =
 501                     (timer->period & 0xffffffff00000000ULL) | new_val;
 502             }
 503             timer->config &= ~HPET_TN_SETVAL;
 504             if (hpet_enabled(s)) {
 505                 hpet_set_timer(timer);
 506             }
 507             break;
 508         case HPET_TN_CMP + 4: // comparator register high order
 509             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 510             if (!timer_is_periodic(timer)
 511                 || (timer->config & HPET_TN_SETVAL)) {
 512                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 513             } else {
 514                 /*
 515                  * FIXME: Clamp period to reasonable min value?
 516                  * Clamp period to reasonable max value
 517                  */
 518                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 519                 timer->period =
 520                     (timer->period & 0xffffffffULL) | new_val << 32;
 521                 }
 522                 timer->config &= ~HPET_TN_SETVAL;
 523                 if (hpet_enabled(s)) {
 524                     hpet_set_timer(timer);
 525                 }
 526                 break;
 527         case HPET_TN_ROUTE:
 528             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 529             break;
 530         case HPET_TN_ROUTE + 4:
 531             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 532             break;
 533         default:
 534             DPRINTF("qemu: invalid hpet_ram_writel\n");
 535             break;
 536         }
 537         return;
 538     } else {
 539         switch (index) {
 540         case HPET_ID:
 541             return;
 542         case HPET_CFG:
 543             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 544             s->config = (s->config & 0xffffffff00000000ULL) | val;
 545             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 546                 /* Enable main counter and interrupt generation. */
 547                 s->hpet_offset =
 548                     ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
 549                 for (i = 0; i < s->num_timers; i++) {
 550                     if ((&s->timer[i])->cmp != ~0ULL) {
 551                         hpet_set_timer(&s->timer[i]);
 552                     }
 553                 }
 554             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 555                 /* Halt main counter and disable interrupt generation. */
 556                 s->hpet_counter = hpet_get_ticks(s);
 557                 for (i = 0; i < s->num_timers; i++) {
 558                     hpet_del_timer(&s->timer[i]);
 559                 }
 560             }
 561             /* i8254 and RTC are disabled when HPET is in legacy mode */
 562             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 563                 hpet_pit_disable();
 564                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 565             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 566                 hpet_pit_enable();
 567                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 568             }
 569             break;
 570         case HPET_CFG + 4:
 571             DPRINTF("qemu: invalid HPET_CFG+4 write \n");
 572             break;
 573         case HPET_STATUS:
 574             val = new_val & s->isr;
 575             for (i = 0; i < s->num_timers; i++) {
 576                 if (val & (1 << i)) {
 577                     update_irq(&s->timer[i], 0);
 578                 }
 579             }
 580             break;
 581         case HPET_COUNTER:
 582             if (hpet_enabled(s)) {
 583                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 584             }
 585             s->hpet_counter =
 586                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 587             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 588                     value, s->hpet_counter);
 589             break;
 590         case HPET_COUNTER + 4:
 591             if (hpet_enabled(s)) {
 592                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 593             }
 594             s->hpet_counter =
 595                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 596             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 597                     value, s->hpet_counter);
 598             break;
 599         default:
 600             DPRINTF("qemu: invalid hpet_ram_writel\n");
 601             break;
 602         }
 603     }
 604 }
 605
 606 static CPUReadMemoryFunc * const hpet_ram_read[] = {
 607 #ifdef HPET_DEBUG
 608     hpet_ram_readb,
 609     hpet_ram_readw,
 610 #else
 611     NULL,
 612     NULL,
 613 #endif
 614     hpet_ram_readl,
 615 };
 616
 617 static CPUWriteMemoryFunc * const hpet_ram_write[] = {
 618 #ifdef HPET_DEBUG
 619     hpet_ram_writeb,
 620     hpet_ram_writew,
 621 #else
 622     NULL,
 623     NULL,
 624 #endif
 625     hpet_ram_writel,
 626 };
 627
 628 static void hpet_reset(DeviceState *d)
 629 {
 630     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 631     int i;
 632     static int count = 0;
 633
 634     for (i = 0; i < s->num_timers; i++) {
 635         HPETTimer *timer = &s->timer[i];
 636
 637         hpet_del_timer(timer);
 638         timer->cmp = ~0ULL;
 639         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 640         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 641             timer->config |= HPET_TN_FSB_CAP;
 642         }
 643         /* advertise availability of ioapic inti2 */
 644         timer->config |=  0x00000004ULL << 32;
 645         timer->period = 0ULL;
 646         timer->wrap_flag = 0;
 647     }
 648
 649     s->hpet_counter = 0ULL;
 650     s->hpet_offset = 0ULL;
 651     /* 64-bit main counter; LegacyReplacementRoute. */
 652     s->capability = 0x8086a001ULL;
 653     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 654     s->capability |= ((HPET_CLK_PERIOD) << 32);
 655     s->config = 0ULL;
 656     if (count > 0) {
 657         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 658          * because hpet is taking over for pit here. On subsequent invocations,
 659          * hpet_reset is called due to system reset. At this point control must
 660          * be returned to pit until SW reenables hpet.
 661          */
 662         hpet_pit_enable();
 663     }
 664     count = 1;
 665 }
 666
 667 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
 668 {
 669     HPETState *s = FROM_SYSBUS(HPETState, opaque);
 670
 671     s->rtc_irq_level = level;
 672     if (!hpet_in_legacy_mode(s)) {
 673         qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 674     }
 675 }
 676
 677 static int hpet_init(SysBusDevice *dev)
 678 {
 679     HPETState *s = FROM_SYSBUS(HPETState, dev);
 680     int i, iomemtype;
 681     HPETTimer *timer;
 682
 683     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 684         sysbus_init_irq(dev, &s->irqs[i]);
 685     }
 686
 687     if (s->num_timers < HPET_MIN_TIMERS) {
 688         s->num_timers = HPET_MIN_TIMERS;
 689     } else if (s->num_timers > HPET_MAX_TIMERS) {
 690         s->num_timers = HPET_MAX_TIMERS;
 691     }
 692     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 693         timer = &s->timer[i];
 694         timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
 695         timer->tn = i;
 696         timer->state = s;
 697     }
 698
 699     isa_reserve_irq(RTC_ISA_IRQ);
 700     qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
 701
 702     /* HPET Area */
 703     iomemtype = cpu_register_io_memory(hpet_ram_read,
 704                                        hpet_ram_write, s);
 705     sysbus_init_mmio(dev, 0x400, iomemtype);
 706     return 0;
 707 }
 708
 709 static SysBusDeviceInfo hpet_device_info = {
 710     .qdev.name    = "hpet",
 711     .qdev.size    = sizeof(HPETState),
 712     .qdev.no_user = 1,
 713     .qdev.vmsd    = &vmstate_hpet,
 714     .qdev.reset   = hpet_reset,
 715     .init         = hpet_init,
 716     .qdev.props = (Property[]) {
 717         DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 718         DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 719         DEFINE_PROP_END_OF_LIST(),
 720     },
 721 };
 722
 723 static void hpet_register_device(void)
 724 {
 725     sysbus_register_withprop(&hpet_device_info);
 726 }
 727
 728 device_init(hpet_register_device)