2 * Copyright (c) 2007, Neocleus Corporation.
4 * This work is licensed under the terms of the GNU GPL, version 2. See
5 * the COPYING file in the top-level directory.
8 * Assign a PCI device from the host to a guest VM.
10 * This implementation uses the classic device assignment interface of KVM
11 * and is only available on x86 hosts. It is expected to be obsoleted by VFIO
12 * based device assignment.
14 * Adapted for KVM (qemu-kvm) by Qumranet. QEMU version was based on qemu-kvm
15 * revision 4144fe9d48. See its repository for the history.
17 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
18 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
19 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
20 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
21 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
27 #include <sys/types.h>
30 #include "hw/i386/pc.h"
31 #include "qemu/error-report.h"
32 #include "ui/console.h"
33 #include "hw/loader.h"
34 #include "monitor/monitor.h"
35 #include "qemu/range.h"
36 #include "sysemu/sysemu.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/msi.h"
41 #define MSIX_PAGE_SIZE 0x1000
43 /* From linux/ioport.h */
44 #define IORESOURCE_IO 0x00000100 /* Resource type */
45 #define IORESOURCE_MEM 0x00000200
46 #define IORESOURCE_IRQ 0x00000400
47 #define IORESOURCE_DMA 0x00000800
48 #define IORESOURCE_PREFETCH 0x00002000 /* No side effects */
49 #define IORESOURCE_MEM_64 0x00100000
51 //#define DEVICE_ASSIGNMENT_DEBUG
53 #ifdef DEVICE_ASSIGNMENT_DEBUG
54 #define DEBUG(fmt, ...) \
56 fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
59 #define DEBUG(fmt, ...)
62 typedef struct PCIRegion
{
63 int type
; /* Memory or port I/O */
66 uint64_t size
; /* size of the region */
70 typedef struct PCIDevRegions
{
71 uint8_t bus
, dev
, func
; /* Bus inside domain, device and function */
72 int irq
; /* IRQ number */
73 uint16_t region_number
; /* number of active regions */
75 /* Port I/O or MMIO Regions */
76 PCIRegion regions
[PCI_NUM_REGIONS
- 1];
80 typedef struct AssignedDevRegion
{
81 MemoryRegion container
;
82 MemoryRegion real_iomem
;
84 uint8_t *r_virtbase
; /* mmapped access address for memory regions */
85 uint32_t r_baseport
; /* the base guest port for I/O regions */
87 pcibus_t e_size
; /* emulated size of region in bytes */
88 pcibus_t r_size
; /* real size of region in bytes */
92 #define ASSIGNED_DEVICE_PREFER_MSI_BIT 0
93 #define ASSIGNED_DEVICE_SHARE_INTX_BIT 1
95 #define ASSIGNED_DEVICE_PREFER_MSI_MASK (1 << ASSIGNED_DEVICE_PREFER_MSI_BIT)
96 #define ASSIGNED_DEVICE_SHARE_INTX_MASK (1 << ASSIGNED_DEVICE_SHARE_INTX_BIT)
98 typedef struct MSIXTableEntry
{
105 typedef enum AssignedIRQType
{
106 ASSIGNED_IRQ_NONE
= 0,
107 ASSIGNED_IRQ_INTX_HOST_INTX
,
108 ASSIGNED_IRQ_INTX_HOST_MSI
,
113 typedef struct AssignedDevice
{
115 PCIHostDeviceAddress host
;
119 AssignedDevRegion v_addrs
[PCI_NUM_REGIONS
- 1];
120 PCIDevRegions real_device
;
121 PCIINTxRoute intx_route
;
122 AssignedIRQType assigned_irq_type
;
124 #define ASSIGNED_DEVICE_CAP_MSI (1 << 0)
125 #define ASSIGNED_DEVICE_CAP_MSIX (1 << 1)
127 #define ASSIGNED_DEVICE_MSI_ENABLED (1 << 0)
128 #define ASSIGNED_DEVICE_MSIX_ENABLED (1 << 1)
129 #define ASSIGNED_DEVICE_MSIX_MASKED (1 << 2)
132 uint8_t emulate_config_read
[PCI_CONFIG_SPACE_SIZE
];
133 uint8_t emulate_config_write
[PCI_CONFIG_SPACE_SIZE
];
136 MSIXTableEntry
*msix_table
;
137 hwaddr msix_table_addr
;
144 static void assigned_dev_update_irq_routing(PCIDevice
*dev
);
146 static void assigned_dev_load_option_rom(AssignedDevice
*dev
);
148 static void assigned_dev_unregister_msix_mmio(AssignedDevice
*dev
);
150 static uint64_t assigned_dev_ioport_rw(AssignedDevRegion
*dev_region
,
151 hwaddr addr
, int size
,
155 int fd
= dev_region
->region
->resource_fd
;
159 DEBUG("pwrite data=%" PRIx64
", size=%d, e_phys=" TARGET_FMT_plx
160 ", addr="TARGET_FMT_plx
"\n", *data
, size
, addr
, addr
);
161 if (pwrite(fd
, data
, size
, addr
) != size
) {
162 error_report("%s - pwrite failed %s",
163 __func__
, strerror(errno
));
166 if (pread(fd
, &val
, size
, addr
) != size
) {
167 error_report("%s - pread failed %s",
168 __func__
, strerror(errno
));
169 val
= (1UL << (size
* 8)) - 1;
171 DEBUG("pread val=%" PRIx64
", size=%d, e_phys=" TARGET_FMT_plx
172 ", addr=" TARGET_FMT_plx
"\n", val
, size
, addr
, addr
);
175 uint32_t port
= addr
+ dev_region
->u
.r_baseport
;
178 DEBUG("out data=%" PRIx64
", size=%d, e_phys=" TARGET_FMT_plx
179 ", host=%x\n", *data
, size
, addr
, port
);
203 DEBUG("in data=%" PRIx64
", size=%d, e_phys=" TARGET_FMT_plx
204 ", host=%x\n", val
, size
, addr
, port
);
210 static void assigned_dev_ioport_write(void *opaque
, hwaddr addr
,
211 uint64_t data
, unsigned size
)
213 assigned_dev_ioport_rw(opaque
, addr
, size
, &data
);
216 static uint64_t assigned_dev_ioport_read(void *opaque
,
217 hwaddr addr
, unsigned size
)
219 return assigned_dev_ioport_rw(opaque
, addr
, size
, NULL
);
222 static uint32_t slow_bar_readb(void *opaque
, hwaddr addr
)
224 AssignedDevRegion
*d
= opaque
;
225 uint8_t *in
= d
->u
.r_virtbase
+ addr
;
229 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
, r
);
234 static uint32_t slow_bar_readw(void *opaque
, hwaddr addr
)
236 AssignedDevRegion
*d
= opaque
;
237 uint16_t *in
= (uint16_t *)(d
->u
.r_virtbase
+ addr
);
241 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
, r
);
246 static uint32_t slow_bar_readl(void *opaque
, hwaddr addr
)
248 AssignedDevRegion
*d
= opaque
;
249 uint32_t *in
= (uint32_t *)(d
->u
.r_virtbase
+ addr
);
253 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
, r
);
258 static void slow_bar_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
260 AssignedDevRegion
*d
= opaque
;
261 uint8_t *out
= d
->u
.r_virtbase
+ addr
;
263 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%02x\n", addr
, val
);
267 static void slow_bar_writew(void *opaque
, hwaddr addr
, uint32_t val
)
269 AssignedDevRegion
*d
= opaque
;
270 uint16_t *out
= (uint16_t *)(d
->u
.r_virtbase
+ addr
);
272 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%04x\n", addr
, val
);
276 static void slow_bar_writel(void *opaque
, hwaddr addr
, uint32_t val
)
278 AssignedDevRegion
*d
= opaque
;
279 uint32_t *out
= (uint32_t *)(d
->u
.r_virtbase
+ addr
);
281 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
, val
);
285 static const MemoryRegionOps slow_bar_ops
= {
287 .read
= { slow_bar_readb
, slow_bar_readw
, slow_bar_readl
, },
288 .write
= { slow_bar_writeb
, slow_bar_writew
, slow_bar_writel
, },
290 .endianness
= DEVICE_NATIVE_ENDIAN
,
293 static void assigned_dev_iomem_setup(PCIDevice
*pci_dev
, int region_num
,
296 AssignedDevice
*r_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
297 AssignedDevRegion
*region
= &r_dev
->v_addrs
[region_num
];
298 PCIRegion
*real_region
= &r_dev
->real_device
.regions
[region_num
];
301 memory_region_init(®ion
->container
, OBJECT(pci_dev
),
302 "assigned-dev-container", e_size
);
303 memory_region_add_subregion(®ion
->container
, 0, ®ion
->real_iomem
);
305 /* deal with MSI-X MMIO page */
306 if (real_region
->base_addr
<= r_dev
->msix_table_addr
&&
307 real_region
->base_addr
+ real_region
->size
>
308 r_dev
->msix_table_addr
) {
309 uint64_t offset
= r_dev
->msix_table_addr
- real_region
->base_addr
;
311 memory_region_add_subregion_overlap(®ion
->container
,
319 static const MemoryRegionOps assigned_dev_ioport_ops
= {
320 .read
= assigned_dev_ioport_read
,
321 .write
= assigned_dev_ioport_write
,
322 .endianness
= DEVICE_NATIVE_ENDIAN
,
325 static void assigned_dev_ioport_setup(PCIDevice
*pci_dev
, int region_num
,
328 AssignedDevice
*r_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
329 AssignedDevRegion
*region
= &r_dev
->v_addrs
[region_num
];
331 region
->e_size
= size
;
332 memory_region_init(®ion
->container
, OBJECT(pci_dev
),
333 "assigned-dev-container", size
);
334 memory_region_init_io(®ion
->real_iomem
, OBJECT(pci_dev
),
335 &assigned_dev_ioport_ops
, r_dev
->v_addrs
+ region_num
,
336 "assigned-dev-iomem", size
);
337 memory_region_add_subregion(®ion
->container
, 0, ®ion
->real_iomem
);
340 static uint32_t assigned_dev_pci_read(PCIDevice
*d
, int pos
, int len
)
342 AssignedDevice
*pci_dev
= DO_UPCAST(AssignedDevice
, dev
, d
);
345 int fd
= pci_dev
->real_device
.config_fd
;
348 ret
= pread(fd
, &val
, len
, pos
);
350 if ((ret
< 0) && (errno
== EINTR
|| errno
== EAGAIN
)) {
354 hw_error("pci read failed, ret = %zd errno = %d\n", ret
, errno
);
360 static uint8_t assigned_dev_pci_read_byte(PCIDevice
*d
, int pos
)
362 return (uint8_t)assigned_dev_pci_read(d
, pos
, 1);
365 static void assigned_dev_pci_write(PCIDevice
*d
, int pos
, uint32_t val
, int len
)
367 AssignedDevice
*pci_dev
= DO_UPCAST(AssignedDevice
, dev
, d
);
369 int fd
= pci_dev
->real_device
.config_fd
;
372 ret
= pwrite(fd
, &val
, len
, pos
);
374 if ((ret
< 0) && (errno
== EINTR
|| errno
== EAGAIN
)) {
378 hw_error("pci write failed, ret = %zd errno = %d\n", ret
, errno
);
382 static void assigned_dev_emulate_config_read(AssignedDevice
*dev
,
383 uint32_t offset
, uint32_t len
)
385 memset(dev
->emulate_config_read
+ offset
, 0xff, len
);
388 static void assigned_dev_direct_config_read(AssignedDevice
*dev
,
389 uint32_t offset
, uint32_t len
)
391 memset(dev
->emulate_config_read
+ offset
, 0, len
);
394 static void assigned_dev_direct_config_write(AssignedDevice
*dev
,
395 uint32_t offset
, uint32_t len
)
397 memset(dev
->emulate_config_write
+ offset
, 0, len
);
400 static uint8_t pci_find_cap_offset(PCIDevice
*d
, uint8_t cap
, uint8_t start
)
404 int pos
= start
? start
: PCI_CAPABILITY_LIST
;
407 status
= assigned_dev_pci_read_byte(d
, PCI_STATUS
);
408 if ((status
& PCI_STATUS_CAP_LIST
) == 0) {
413 pos
= assigned_dev_pci_read_byte(d
, pos
);
419 id
= assigned_dev_pci_read_byte(d
, pos
+ PCI_CAP_LIST_ID
);
428 pos
+= PCI_CAP_LIST_NEXT
;
433 static int assigned_dev_register_regions(PCIRegion
*io_regions
,
434 unsigned long regions_num
,
435 AssignedDevice
*pci_dev
)
438 PCIRegion
*cur_region
= io_regions
;
440 for (i
= 0; i
< regions_num
; i
++, cur_region
++) {
441 if (!cur_region
->valid
) {
445 /* handle memory io regions */
446 if (cur_region
->type
& IORESOURCE_MEM
) {
447 int t
= PCI_BASE_ADDRESS_SPACE_MEMORY
;
448 if (cur_region
->type
& IORESOURCE_PREFETCH
) {
449 t
|= PCI_BASE_ADDRESS_MEM_PREFETCH
;
451 if (cur_region
->type
& IORESOURCE_MEM_64
) {
452 t
|= PCI_BASE_ADDRESS_MEM_TYPE_64
;
455 /* map physical memory */
456 pci_dev
->v_addrs
[i
].u
.r_virtbase
= mmap(NULL
, cur_region
->size
,
457 PROT_WRITE
| PROT_READ
,
459 cur_region
->resource_fd
,
462 if (pci_dev
->v_addrs
[i
].u
.r_virtbase
== MAP_FAILED
) {
463 pci_dev
->v_addrs
[i
].u
.r_virtbase
= NULL
;
464 error_report("%s: Error: Couldn't mmap 0x%" PRIx64
"!",
465 __func__
, cur_region
->base_addr
);
469 pci_dev
->v_addrs
[i
].r_size
= cur_region
->size
;
470 pci_dev
->v_addrs
[i
].e_size
= 0;
473 pci_dev
->v_addrs
[i
].u
.r_virtbase
+=
474 (cur_region
->base_addr
& 0xFFF);
476 if (cur_region
->size
& 0xFFF) {
477 error_report("PCI region %d at address 0x%" PRIx64
" has "
478 "size 0x%" PRIx64
", which is not a multiple of "
479 "4K. You might experience some performance hit "
481 i
, cur_region
->base_addr
, cur_region
->size
);
482 memory_region_init_io(&pci_dev
->v_addrs
[i
].real_iomem
,
483 OBJECT(pci_dev
), &slow_bar_ops
,
484 &pci_dev
->v_addrs
[i
],
485 "assigned-dev-slow-bar",
488 void *virtbase
= pci_dev
->v_addrs
[i
].u
.r_virtbase
;
490 snprintf(name
, sizeof(name
), "%s.bar%d",
491 object_get_typename(OBJECT(pci_dev
)), i
);
492 memory_region_init_ram_ptr(&pci_dev
->v_addrs
[i
].real_iomem
,
493 OBJECT(pci_dev
), name
,
494 cur_region
->size
, virtbase
);
495 vmstate_register_ram(&pci_dev
->v_addrs
[i
].real_iomem
,
499 assigned_dev_iomem_setup(&pci_dev
->dev
, i
, cur_region
->size
);
500 pci_register_bar((PCIDevice
*) pci_dev
, i
, t
,
501 &pci_dev
->v_addrs
[i
].container
);
504 /* handle port io regions */
508 /* Test kernel support for ioport resource read/write. Old
509 * kernels return EIO. New kernels only allow 1/2/4 byte reads
510 * so should return EINVAL for a 3 byte read */
511 ret
= pread(pci_dev
->v_addrs
[i
].region
->resource_fd
, &val
, 3, 0);
513 error_report("Unexpected return from I/O port read: %d", ret
);
515 } else if (errno
!= EINVAL
) {
516 error_report("Kernel doesn't support ioport resource "
517 "access, hiding this region.");
518 close(pci_dev
->v_addrs
[i
].region
->resource_fd
);
519 cur_region
->valid
= 0;
523 pci_dev
->v_addrs
[i
].u
.r_baseport
= cur_region
->base_addr
;
524 pci_dev
->v_addrs
[i
].r_size
= cur_region
->size
;
525 pci_dev
->v_addrs
[i
].e_size
= 0;
527 assigned_dev_ioport_setup(&pci_dev
->dev
, i
, cur_region
->size
);
528 pci_register_bar((PCIDevice
*) pci_dev
, i
,
529 PCI_BASE_ADDRESS_SPACE_IO
,
530 &pci_dev
->v_addrs
[i
].container
);
538 static int get_real_id(const char *devpath
, const char *idname
, uint16_t *val
)
544 snprintf(name
, sizeof(name
), "%s%s", devpath
, idname
);
545 f
= fopen(name
, "r");
547 error_report("%s: %s: %m", __func__
, name
);
550 if (fscanf(f
, "%li\n", &id
) == 1) {
561 static int get_real_vendor_id(const char *devpath
, uint16_t *val
)
563 return get_real_id(devpath
, "vendor", val
);
566 static int get_real_device_id(const char *devpath
, uint16_t *val
)
568 return get_real_id(devpath
, "device", val
);
571 static int get_real_device(AssignedDevice
*pci_dev
, uint16_t r_seg
,
572 uint8_t r_bus
, uint8_t r_dev
, uint8_t r_func
)
574 char dir
[128], name
[128];
577 uint64_t start
, end
, size
, flags
;
580 PCIDevRegions
*dev
= &pci_dev
->real_device
;
582 dev
->region_number
= 0;
584 snprintf(dir
, sizeof(dir
), "/sys/bus/pci/devices/%04x:%02x:%02x.%x/",
585 r_seg
, r_bus
, r_dev
, r_func
);
587 snprintf(name
, sizeof(name
), "%sconfig", dir
);
589 if (pci_dev
->configfd_name
&& *pci_dev
->configfd_name
) {
590 dev
->config_fd
= monitor_handle_fd_param(cur_mon
, pci_dev
->configfd_name
);
591 if (dev
->config_fd
< 0) {
595 dev
->config_fd
= open(name
, O_RDWR
);
597 if (dev
->config_fd
== -1) {
598 error_report("%s: %s: %m", __func__
, name
);
603 r
= read(dev
->config_fd
, pci_dev
->dev
.config
,
604 pci_config_size(&pci_dev
->dev
));
606 if (errno
== EINTR
|| errno
== EAGAIN
) {
609 error_report("%s: read failed, errno = %d", __func__
, errno
);
612 /* Restore or clear multifunction, this is always controlled by qemu */
613 if (pci_dev
->dev
.cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
614 pci_dev
->dev
.config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
616 pci_dev
->dev
.config
[PCI_HEADER_TYPE
] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
619 /* Clear host resource mapping info. If we choose not to register a
620 * BAR, such as might be the case with the option ROM, we can get
621 * confusing, unwritable, residual addresses from the host here. */
622 memset(&pci_dev
->dev
.config
[PCI_BASE_ADDRESS_0
], 0, 24);
623 memset(&pci_dev
->dev
.config
[PCI_ROM_ADDRESS
], 0, 4);
625 snprintf(name
, sizeof(name
), "%sresource", dir
);
627 f
= fopen(name
, "r");
629 error_report("%s: %s: %m", __func__
, name
);
633 for (r
= 0; r
< PCI_ROM_SLOT
; r
++) {
634 if (fscanf(f
, "%" SCNi64
" %" SCNi64
" %" SCNi64
"\n",
635 &start
, &end
, &flags
) != 3) {
639 rp
= dev
->regions
+ r
;
641 rp
->resource_fd
= -1;
642 size
= end
- start
+ 1;
643 flags
&= IORESOURCE_IO
| IORESOURCE_MEM
| IORESOURCE_PREFETCH
645 if (size
== 0 || (flags
& ~IORESOURCE_PREFETCH
) == 0) {
648 if (flags
& IORESOURCE_MEM
) {
649 flags
&= ~IORESOURCE_IO
;
651 flags
&= ~IORESOURCE_PREFETCH
;
653 snprintf(name
, sizeof(name
), "%sresource%d", dir
, r
);
654 fd
= open(name
, O_RDWR
);
658 rp
->resource_fd
= fd
;
662 rp
->base_addr
= start
;
664 pci_dev
->v_addrs
[r
].region
= rp
;
665 DEBUG("region %d size %" PRIu64
" start 0x%" PRIx64
666 " type %d resource_fd %d\n",
667 r
, rp
->size
, start
, rp
->type
, rp
->resource_fd
);
672 /* read and fill vendor ID */
673 v
= get_real_vendor_id(dir
, &id
);
677 pci_dev
->dev
.config
[0] = id
& 0xff;
678 pci_dev
->dev
.config
[1] = (id
& 0xff00) >> 8;
680 /* read and fill device ID */
681 v
= get_real_device_id(dir
, &id
);
685 pci_dev
->dev
.config
[2] = id
& 0xff;
686 pci_dev
->dev
.config
[3] = (id
& 0xff00) >> 8;
688 pci_word_test_and_clear_mask(pci_dev
->emulate_config_write
+ PCI_COMMAND
,
689 PCI_COMMAND_MASTER
| PCI_COMMAND_INTX_DISABLE
);
691 dev
->region_number
= r
;
695 static void free_msi_virqs(AssignedDevice
*dev
)
699 for (i
= 0; i
< dev
->msi_virq_nr
; i
++) {
700 if (dev
->msi_virq
[i
] >= 0) {
701 kvm_irqchip_release_virq(kvm_state
, dev
->msi_virq
[i
]);
702 dev
->msi_virq
[i
] = -1;
705 g_free(dev
->msi_virq
);
706 dev
->msi_virq
= NULL
;
707 dev
->msi_virq_nr
= 0;
710 static void free_assigned_device(AssignedDevice
*dev
)
714 if (dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSIX
) {
715 assigned_dev_unregister_msix_mmio(dev
);
717 for (i
= 0; i
< dev
->real_device
.region_number
; i
++) {
718 PCIRegion
*pci_region
= &dev
->real_device
.regions
[i
];
719 AssignedDevRegion
*region
= &dev
->v_addrs
[i
];
721 if (!pci_region
->valid
) {
724 if (pci_region
->type
& IORESOURCE_IO
) {
725 if (region
->u
.r_baseport
) {
726 memory_region_del_subregion(®ion
->container
,
727 ®ion
->real_iomem
);
728 memory_region_destroy(®ion
->real_iomem
);
729 memory_region_destroy(®ion
->container
);
731 } else if (pci_region
->type
& IORESOURCE_MEM
) {
732 if (region
->u
.r_virtbase
) {
733 memory_region_del_subregion(®ion
->container
,
734 ®ion
->real_iomem
);
736 /* Remove MSI-X table subregion */
737 if (pci_region
->base_addr
<= dev
->msix_table_addr
&&
738 pci_region
->base_addr
+ pci_region
->size
>
739 dev
->msix_table_addr
) {
740 memory_region_del_subregion(®ion
->container
,
744 memory_region_destroy(®ion
->real_iomem
);
745 memory_region_destroy(®ion
->container
);
746 if (munmap(region
->u
.r_virtbase
,
747 (pci_region
->size
+ 0xFFF) & 0xFFFFF000)) {
748 error_report("Failed to unmap assigned device region: %s",
753 if (pci_region
->resource_fd
>= 0) {
754 close(pci_region
->resource_fd
);
758 if (dev
->real_device
.config_fd
>= 0) {
759 close(dev
->real_device
.config_fd
);
765 static void assign_failed_examine(AssignedDevice
*dev
)
767 char name
[PATH_MAX
], dir
[PATH_MAX
], driver
[PATH_MAX
] = {}, *ns
;
768 uint16_t vendor_id
, device_id
;
771 snprintf(dir
, sizeof(dir
), "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
772 dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
775 snprintf(name
, sizeof(name
), "%sdriver", dir
);
777 r
= readlink(name
, driver
, sizeof(driver
));
778 if ((r
<= 0) || r
>= sizeof(driver
)) {
782 ns
= strrchr(driver
, '/');
789 if (get_real_vendor_id(dir
, &vendor_id
) ||
790 get_real_device_id(dir
, &device_id
)) {
794 error_report("*** The driver '%s' is occupying your device "
795 "%04x:%02x:%02x.%x.",
796 ns
, dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
799 error_report("*** You can try the following commands to free it:");
801 error_report("*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub/"
802 "new_id", vendor_id
, device_id
);
803 error_report("*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/"
805 dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
806 dev
->host
.function
, ns
);
807 error_report("*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/"
809 dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
811 error_report("*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub"
812 "/remove_id", vendor_id
, device_id
);
818 error_report("Couldn't find out why.");
821 static int assign_device(AssignedDevice
*dev
)
823 uint32_t flags
= KVM_DEV_ASSIGN_ENABLE_IOMMU
;
826 /* Only pass non-zero PCI segment to capable module */
827 if (!kvm_check_extension(kvm_state
, KVM_CAP_PCI_SEGMENT
) &&
829 error_report("Can't assign device inside non-zero PCI segment "
830 "as this KVM module doesn't support it.");
834 if (!kvm_check_extension(kvm_state
, KVM_CAP_IOMMU
)) {
835 error_report("No IOMMU found. Unable to assign device \"%s\"",
840 if (dev
->features
& ASSIGNED_DEVICE_SHARE_INTX_MASK
&&
841 kvm_has_intx_set_mask()) {
842 flags
|= KVM_DEV_ASSIGN_PCI_2_3
;
845 r
= kvm_device_pci_assign(kvm_state
, &dev
->host
, flags
, &dev
->dev_id
);
847 error_report("Failed to assign device \"%s\" : %s",
848 dev
->dev
.qdev
.id
, strerror(-r
));
852 assign_failed_examine(dev
);
861 static bool check_irqchip_in_kernel(void)
863 if (kvm_irqchip_in_kernel()) {
866 error_report("pci-assign: error: requires KVM with in-kernel irqchip "
871 static int assign_intx(AssignedDevice
*dev
)
873 AssignedIRQType new_type
;
874 PCIINTxRoute intx_route
;
878 /* Interrupt PIN 0 means don't use INTx */
879 if (assigned_dev_pci_read_byte(&dev
->dev
, PCI_INTERRUPT_PIN
) == 0) {
880 pci_device_set_intx_routing_notifier(&dev
->dev
, NULL
);
884 if (!check_irqchip_in_kernel()) {
888 pci_device_set_intx_routing_notifier(&dev
->dev
,
889 assigned_dev_update_irq_routing
);
891 intx_route
= pci_device_route_intx_to_irq(&dev
->dev
, dev
->intpin
);
892 assert(intx_route
.mode
!= PCI_INTX_INVERTED
);
894 if (!pci_intx_route_changed(&dev
->intx_route
, &intx_route
)) {
898 switch (dev
->assigned_irq_type
) {
899 case ASSIGNED_IRQ_INTX_HOST_INTX
:
900 case ASSIGNED_IRQ_INTX_HOST_MSI
:
901 intx_host_msi
= dev
->assigned_irq_type
== ASSIGNED_IRQ_INTX_HOST_MSI
;
902 r
= kvm_device_intx_deassign(kvm_state
, dev
->dev_id
, intx_host_msi
);
904 case ASSIGNED_IRQ_MSI
:
905 r
= kvm_device_msi_deassign(kvm_state
, dev
->dev_id
);
907 case ASSIGNED_IRQ_MSIX
:
908 r
= kvm_device_msix_deassign(kvm_state
, dev
->dev_id
);
915 perror("assign_intx: deassignment of previous interrupt failed");
917 dev
->assigned_irq_type
= ASSIGNED_IRQ_NONE
;
919 if (intx_route
.mode
== PCI_INTX_DISABLED
) {
920 dev
->intx_route
= intx_route
;
925 if (dev
->features
& ASSIGNED_DEVICE_PREFER_MSI_MASK
&&
926 dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSI
) {
927 intx_host_msi
= true;
928 new_type
= ASSIGNED_IRQ_INTX_HOST_MSI
;
930 intx_host_msi
= false;
931 new_type
= ASSIGNED_IRQ_INTX_HOST_INTX
;
934 r
= kvm_device_intx_assign(kvm_state
, dev
->dev_id
, intx_host_msi
,
937 if (r
== -EIO
&& !(dev
->features
& ASSIGNED_DEVICE_PREFER_MSI_MASK
) &&
938 dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSI
) {
939 /* Retry with host-side MSI. There might be an IRQ conflict and
940 * either the kernel or the device doesn't support sharing. */
941 error_report("Host-side INTx sharing not supported, "
942 "using MSI instead");
943 error_printf("Some devices do not work properly in this mode.\n");
944 dev
->features
|= ASSIGNED_DEVICE_PREFER_MSI_MASK
;
947 error_report("Failed to assign irq for \"%s\": %s",
948 dev
->dev
.qdev
.id
, strerror(-r
));
949 error_report("Perhaps you are assigning a device "
950 "that shares an IRQ with another device?");
954 dev
->intx_route
= intx_route
;
955 dev
->assigned_irq_type
= new_type
;
959 static void deassign_device(AssignedDevice
*dev
)
963 r
= kvm_device_pci_deassign(kvm_state
, dev
->dev_id
);
967 /* The pci config space got updated. Check if irq numbers have changed
970 static void assigned_dev_update_irq_routing(PCIDevice
*dev
)
972 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, dev
);
976 r
= assign_intx(assigned_dev
);
978 qdev_unplug(&dev
->qdev
, &err
);
983 static void assigned_dev_update_msi(PCIDevice
*pci_dev
)
985 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
986 uint8_t ctrl_byte
= pci_get_byte(pci_dev
->config
+ pci_dev
->msi_cap
+
990 /* Some guests gratuitously disable MSI even if they're not using it,
991 * try to catch this by only deassigning irqs if the guest is using
992 * MSI or intends to start. */
993 if (assigned_dev
->assigned_irq_type
== ASSIGNED_IRQ_MSI
||
994 (ctrl_byte
& PCI_MSI_FLAGS_ENABLE
)) {
995 r
= kvm_device_msi_deassign(kvm_state
, assigned_dev
->dev_id
);
996 /* -ENXIO means no assigned irq */
997 if (r
&& r
!= -ENXIO
) {
998 perror("assigned_dev_update_msi: deassign irq");
1001 free_msi_virqs(assigned_dev
);
1003 assigned_dev
->assigned_irq_type
= ASSIGNED_IRQ_NONE
;
1004 pci_device_set_intx_routing_notifier(pci_dev
, NULL
);
1007 if (ctrl_byte
& PCI_MSI_FLAGS_ENABLE
) {
1008 MSIMessage msg
= msi_get_message(pci_dev
, 0);
1011 virq
= kvm_irqchip_add_msi_route(kvm_state
, msg
);
1013 perror("assigned_dev_update_msi: kvm_irqchip_add_msi_route");
1017 assigned_dev
->msi_virq
= g_malloc(sizeof(*assigned_dev
->msi_virq
));
1018 assigned_dev
->msi_virq_nr
= 1;
1019 assigned_dev
->msi_virq
[0] = virq
;
1020 if (kvm_device_msi_assign(kvm_state
, assigned_dev
->dev_id
, virq
) < 0) {
1021 perror("assigned_dev_update_msi: kvm_device_msi_assign");
1024 assigned_dev
->intx_route
.mode
= PCI_INTX_DISABLED
;
1025 assigned_dev
->intx_route
.irq
= -1;
1026 assigned_dev
->assigned_irq_type
= ASSIGNED_IRQ_MSI
;
1028 assign_intx(assigned_dev
);
1032 static void assigned_dev_update_msi_msg(PCIDevice
*pci_dev
)
1034 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1035 uint8_t ctrl_byte
= pci_get_byte(pci_dev
->config
+ pci_dev
->msi_cap
+
1038 if (assigned_dev
->assigned_irq_type
!= ASSIGNED_IRQ_MSI
||
1039 !(ctrl_byte
& PCI_MSI_FLAGS_ENABLE
)) {
1043 kvm_irqchip_update_msi_route(kvm_state
, assigned_dev
->msi_virq
[0],
1044 msi_get_message(pci_dev
, 0));
1047 static bool assigned_dev_msix_masked(MSIXTableEntry
*entry
)
1049 return (entry
->ctrl
& cpu_to_le32(0x1)) != 0;
1053 * When MSI-X is first enabled the vector table typically has all the
1054 * vectors masked, so we can't use that as the obvious test to figure out
1055 * how many vectors to initially enable. Instead we look at the data field
1056 * because this is what worked for pci-assign for a long time. This makes
1057 * sure the physical MSI-X state tracks the guest's view, which is important
1058 * for some VF/PF and PF/fw communication channels.
1060 static bool assigned_dev_msix_skipped(MSIXTableEntry
*entry
)
1062 return !entry
->data
;
1065 static int assigned_dev_update_msix_mmio(PCIDevice
*pci_dev
)
1067 AssignedDevice
*adev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1068 uint16_t entries_nr
= 0;
1070 MSIXTableEntry
*entry
= adev
->msix_table
;
1073 /* Get the usable entry number for allocating */
1074 for (i
= 0; i
< adev
->msix_max
; i
++, entry
++) {
1075 if (assigned_dev_msix_skipped(entry
)) {
1081 DEBUG("MSI-X entries: %d\n", entries_nr
);
1083 /* It's valid to enable MSI-X with all entries masked */
1088 r
= kvm_device_msix_init_vectors(kvm_state
, adev
->dev_id
, entries_nr
);
1090 error_report("fail to set MSI-X entry number for MSIX! %s",
1095 free_msi_virqs(adev
);
1097 adev
->msi_virq_nr
= adev
->msix_max
;
1098 adev
->msi_virq
= g_malloc(adev
->msix_max
* sizeof(*adev
->msi_virq
));
1100 entry
= adev
->msix_table
;
1101 for (i
= 0; i
< adev
->msix_max
; i
++, entry
++) {
1102 adev
->msi_virq
[i
] = -1;
1104 if (assigned_dev_msix_skipped(entry
)) {
1108 msg
.address
= entry
->addr_lo
| ((uint64_t)entry
->addr_hi
<< 32);
1109 msg
.data
= entry
->data
;
1110 r
= kvm_irqchip_add_msi_route(kvm_state
, msg
);
1114 adev
->msi_virq
[i
] = r
;
1116 DEBUG("MSI-X vector %d, gsi %d, addr %08x_%08x, data %08x\n", i
,
1117 r
, entry
->addr_hi
, entry
->addr_lo
, entry
->data
);
1119 r
= kvm_device_msix_set_vector(kvm_state
, adev
->dev_id
, i
,
1122 error_report("fail to set MSI-X entry! %s", strerror(-r
));
1130 static void assigned_dev_update_msix(PCIDevice
*pci_dev
)
1132 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1133 uint16_t ctrl_word
= pci_get_word(pci_dev
->config
+ pci_dev
->msix_cap
+
1137 /* Some guests gratuitously disable MSIX even if they're not using it,
1138 * try to catch this by only deassigning irqs if the guest is using
1139 * MSIX or intends to start. */
1140 if ((assigned_dev
->assigned_irq_type
== ASSIGNED_IRQ_MSIX
) ||
1141 (ctrl_word
& PCI_MSIX_FLAGS_ENABLE
)) {
1142 r
= kvm_device_msix_deassign(kvm_state
, assigned_dev
->dev_id
);
1143 /* -ENXIO means no assigned irq */
1144 if (r
&& r
!= -ENXIO
) {
1145 perror("assigned_dev_update_msix: deassign irq");
1148 free_msi_virqs(assigned_dev
);
1150 assigned_dev
->assigned_irq_type
= ASSIGNED_IRQ_NONE
;
1151 pci_device_set_intx_routing_notifier(pci_dev
, NULL
);
1154 if (ctrl_word
& PCI_MSIX_FLAGS_ENABLE
) {
1155 if (assigned_dev_update_msix_mmio(pci_dev
) < 0) {
1156 perror("assigned_dev_update_msix_mmio");
1160 if (assigned_dev
->msi_virq_nr
> 0) {
1161 if (kvm_device_msix_assign(kvm_state
, assigned_dev
->dev_id
) < 0) {
1162 perror("assigned_dev_enable_msix: assign irq");
1166 assigned_dev
->intx_route
.mode
= PCI_INTX_DISABLED
;
1167 assigned_dev
->intx_route
.irq
= -1;
1168 assigned_dev
->assigned_irq_type
= ASSIGNED_IRQ_MSIX
;
1170 assign_intx(assigned_dev
);
1174 static uint32_t assigned_dev_pci_read_config(PCIDevice
*pci_dev
,
1175 uint32_t address
, int len
)
1177 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1178 uint32_t virt_val
= pci_default_read_config(pci_dev
, address
, len
);
1179 uint32_t real_val
, emulate_mask
, full_emulation_mask
;
1182 memcpy(&emulate_mask
, assigned_dev
->emulate_config_read
+ address
, len
);
1183 emulate_mask
= le32_to_cpu(emulate_mask
);
1185 full_emulation_mask
= 0xffffffff >> (32 - len
* 8);
1187 if (emulate_mask
!= full_emulation_mask
) {
1188 real_val
= assigned_dev_pci_read(pci_dev
, address
, len
);
1189 return (virt_val
& emulate_mask
) | (real_val
& ~emulate_mask
);
1195 static void assigned_dev_pci_write_config(PCIDevice
*pci_dev
, uint32_t address
,
1196 uint32_t val
, int len
)
1198 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1199 uint16_t old_cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1200 uint32_t emulate_mask
, full_emulation_mask
;
1203 pci_default_write_config(pci_dev
, address
, val
, len
);
1205 if (kvm_has_intx_set_mask() &&
1206 range_covers_byte(address
, len
, PCI_COMMAND
+ 1)) {
1207 bool intx_masked
= (pci_get_word(pci_dev
->config
+ PCI_COMMAND
) &
1208 PCI_COMMAND_INTX_DISABLE
);
1210 if (intx_masked
!= !!(old_cmd
& PCI_COMMAND_INTX_DISABLE
)) {
1211 ret
= kvm_device_intx_set_mask(kvm_state
, assigned_dev
->dev_id
,
1214 perror("assigned_dev_pci_write_config: set intx mask");
1218 if (assigned_dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSI
) {
1219 if (range_covers_byte(address
, len
,
1220 pci_dev
->msi_cap
+ PCI_MSI_FLAGS
)) {
1221 assigned_dev_update_msi(pci_dev
);
1222 } else if (ranges_overlap(address
, len
, /* 32bit MSI only */
1223 pci_dev
->msi_cap
+ PCI_MSI_ADDRESS_LO
, 6)) {
1224 assigned_dev_update_msi_msg(pci_dev
);
1227 if (assigned_dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSIX
) {
1228 if (range_covers_byte(address
, len
,
1229 pci_dev
->msix_cap
+ PCI_MSIX_FLAGS
+ 1)) {
1230 assigned_dev_update_msix(pci_dev
);
1235 memcpy(&emulate_mask
, assigned_dev
->emulate_config_write
+ address
, len
);
1236 emulate_mask
= le32_to_cpu(emulate_mask
);
1238 full_emulation_mask
= 0xffffffff >> (32 - len
* 8);
1240 if (emulate_mask
!= full_emulation_mask
) {
1242 val
&= ~emulate_mask
;
1243 val
|= assigned_dev_pci_read(pci_dev
, address
, len
) & emulate_mask
;
1245 assigned_dev_pci_write(pci_dev
, address
, val
, len
);
1249 static void assigned_dev_setup_cap_read(AssignedDevice
*dev
, uint32_t offset
,
1252 assigned_dev_direct_config_read(dev
, offset
, len
);
1253 assigned_dev_emulate_config_read(dev
, offset
+ PCI_CAP_LIST_NEXT
, 1);
1256 static int assigned_device_pci_cap_init(PCIDevice
*pci_dev
)
1258 AssignedDevice
*dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1259 PCIRegion
*pci_region
= dev
->real_device
.regions
;
1262 /* Clear initial capabilities pointer and status copied from hw */
1263 pci_set_byte(pci_dev
->config
+ PCI_CAPABILITY_LIST
, 0);
1264 pci_set_word(pci_dev
->config
+ PCI_STATUS
,
1265 pci_get_word(pci_dev
->config
+ PCI_STATUS
) &
1266 ~PCI_STATUS_CAP_LIST
);
1268 /* Expose MSI capability
1269 * MSI capability is the 1st capability in capability config */
1270 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_MSI
, 0);
1271 if (pos
!= 0 && kvm_check_extension(kvm_state
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
1272 if (!check_irqchip_in_kernel()) {
1275 dev
->cap
.available
|= ASSIGNED_DEVICE_CAP_MSI
;
1276 /* Only 32-bit/no-mask currently supported */
1277 ret
= pci_add_capability(pci_dev
, PCI_CAP_ID_MSI
, pos
, 10);
1281 pci_dev
->msi_cap
= pos
;
1283 pci_set_word(pci_dev
->config
+ pos
+ PCI_MSI_FLAGS
,
1284 pci_get_word(pci_dev
->config
+ pos
+ PCI_MSI_FLAGS
) &
1285 PCI_MSI_FLAGS_QMASK
);
1286 pci_set_long(pci_dev
->config
+ pos
+ PCI_MSI_ADDRESS_LO
, 0);
1287 pci_set_word(pci_dev
->config
+ pos
+ PCI_MSI_DATA_32
, 0);
1289 /* Set writable fields */
1290 pci_set_word(pci_dev
->wmask
+ pos
+ PCI_MSI_FLAGS
,
1291 PCI_MSI_FLAGS_QSIZE
| PCI_MSI_FLAGS_ENABLE
);
1292 pci_set_long(pci_dev
->wmask
+ pos
+ PCI_MSI_ADDRESS_LO
, 0xfffffffc);
1293 pci_set_word(pci_dev
->wmask
+ pos
+ PCI_MSI_DATA_32
, 0xffff);
1295 /* Expose MSI-X capability */
1296 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_MSIX
, 0);
1297 if (pos
!= 0 && kvm_device_msix_supported(kvm_state
)) {
1299 uint32_t msix_table_entry
;
1301 if (!check_irqchip_in_kernel()) {
1304 dev
->cap
.available
|= ASSIGNED_DEVICE_CAP_MSIX
;
1305 ret
= pci_add_capability(pci_dev
, PCI_CAP_ID_MSIX
, pos
, 12);
1309 pci_dev
->msix_cap
= pos
;
1311 pci_set_word(pci_dev
->config
+ pos
+ PCI_MSIX_FLAGS
,
1312 pci_get_word(pci_dev
->config
+ pos
+ PCI_MSIX_FLAGS
) &
1313 PCI_MSIX_FLAGS_QSIZE
);
1315 /* Only enable and function mask bits are writable */
1316 pci_set_word(pci_dev
->wmask
+ pos
+ PCI_MSIX_FLAGS
,
1317 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
1319 msix_table_entry
= pci_get_long(pci_dev
->config
+ pos
+ PCI_MSIX_TABLE
);
1320 bar_nr
= msix_table_entry
& PCI_MSIX_FLAGS_BIRMASK
;
1321 msix_table_entry
&= ~PCI_MSIX_FLAGS_BIRMASK
;
1322 dev
->msix_table_addr
= pci_region
[bar_nr
].base_addr
+ msix_table_entry
;
1323 dev
->msix_max
= pci_get_word(pci_dev
->config
+ pos
+ PCI_MSIX_FLAGS
);
1324 dev
->msix_max
&= PCI_MSIX_FLAGS_QSIZE
;
1328 /* Minimal PM support, nothing writable, device appears to NAK changes */
1329 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_PM
, 0);
1333 ret
= pci_add_capability(pci_dev
, PCI_CAP_ID_PM
, pos
, PCI_PM_SIZEOF
);
1338 assigned_dev_setup_cap_read(dev
, pos
, PCI_PM_SIZEOF
);
1340 pmc
= pci_get_word(pci_dev
->config
+ pos
+ PCI_CAP_FLAGS
);
1341 pmc
&= (PCI_PM_CAP_VER_MASK
| PCI_PM_CAP_DSI
);
1342 pci_set_word(pci_dev
->config
+ pos
+ PCI_CAP_FLAGS
, pmc
);
1344 /* assign_device will bring the device up to D0, so we don't need
1345 * to worry about doing that ourselves here. */
1346 pci_set_word(pci_dev
->config
+ pos
+ PCI_PM_CTRL
,
1347 PCI_PM_CTRL_NO_SOFT_RESET
);
1349 pci_set_byte(pci_dev
->config
+ pos
+ PCI_PM_PPB_EXTENSIONS
, 0);
1350 pci_set_byte(pci_dev
->config
+ pos
+ PCI_PM_DATA_REGISTER
, 0);
1353 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_EXP
, 0);
1355 uint8_t version
, size
= 0;
1356 uint16_t type
, devctl
, lnksta
;
1357 uint32_t devcap
, lnkcap
;
1359 version
= pci_get_byte(pci_dev
->config
+ pos
+ PCI_EXP_FLAGS
);
1360 version
&= PCI_EXP_FLAGS_VERS
;
1363 } else if (version
== 2) {
1365 * Check for non-std size, accept reduced size to 0x34,
1366 * which is what bcm5761 implemented, violating the
1367 * PCIe v3.0 spec that regs should exist and be read as 0,
1368 * not optionally provided and shorten the struct size.
1370 size
= MIN(0x3c, PCI_CONFIG_SPACE_SIZE
- pos
);
1372 error_report("%s: Invalid size PCIe cap-id 0x%x",
1373 __func__
, PCI_CAP_ID_EXP
);
1375 } else if (size
!= 0x3c) {
1376 error_report("WARNING, %s: PCIe cap-id 0x%x has "
1377 "non-standard size 0x%x; std size should be 0x3c",
1378 __func__
, PCI_CAP_ID_EXP
, size
);
1380 } else if (version
== 0) {
1382 vid
= pci_get_word(pci_dev
->config
+ PCI_VENDOR_ID
);
1383 did
= pci_get_word(pci_dev
->config
+ PCI_DEVICE_ID
);
1384 if (vid
== PCI_VENDOR_ID_INTEL
&& did
== 0x10ed) {
1386 * quirk for Intel 82599 VF with invalid PCIe capability
1387 * version, should really be version 2 (same as PF)
1394 error_report("%s: Unsupported PCI express capability version %d",
1399 ret
= pci_add_capability(pci_dev
, PCI_CAP_ID_EXP
, pos
, size
);
1404 assigned_dev_setup_cap_read(dev
, pos
, size
);
1406 type
= pci_get_word(pci_dev
->config
+ pos
+ PCI_EXP_FLAGS
);
1407 type
= (type
& PCI_EXP_FLAGS_TYPE
) >> 4;
1408 if (type
!= PCI_EXP_TYPE_ENDPOINT
&&
1409 type
!= PCI_EXP_TYPE_LEG_END
&& type
!= PCI_EXP_TYPE_RC_END
) {
1410 error_report("Device assignment only supports endpoint assignment,"
1411 " device type %d", type
);
1415 /* capabilities, pass existing read-only copy
1416 * PCI_EXP_FLAGS_IRQ: updated by hardware, should be direct read */
1418 /* device capabilities: hide FLR */
1419 devcap
= pci_get_long(pci_dev
->config
+ pos
+ PCI_EXP_DEVCAP
);
1420 devcap
&= ~PCI_EXP_DEVCAP_FLR
;
1421 pci_set_long(pci_dev
->config
+ pos
+ PCI_EXP_DEVCAP
, devcap
);
1423 /* device control: clear all error reporting enable bits, leaving
1424 * only a few host values. Note, these are
1425 * all writable, but not passed to hw.
1427 devctl
= pci_get_word(pci_dev
->config
+ pos
+ PCI_EXP_DEVCTL
);
1428 devctl
= (devctl
& (PCI_EXP_DEVCTL_READRQ
| PCI_EXP_DEVCTL_PAYLOAD
)) |
1429 PCI_EXP_DEVCTL_RELAX_EN
| PCI_EXP_DEVCTL_NOSNOOP_EN
;
1430 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_DEVCTL
, devctl
);
1431 devctl
= PCI_EXP_DEVCTL_BCR_FLR
| PCI_EXP_DEVCTL_AUX_PME
;
1432 pci_set_word(pci_dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
, ~devctl
);
1434 /* Clear device status */
1435 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_DEVSTA
, 0);
1437 /* Link capabilities, expose links and latencues, clear reporting */
1438 lnkcap
= pci_get_long(pci_dev
->config
+ pos
+ PCI_EXP_LNKCAP
);
1439 lnkcap
&= (PCI_EXP_LNKCAP_SLS
| PCI_EXP_LNKCAP_MLW
|
1440 PCI_EXP_LNKCAP_ASPMS
| PCI_EXP_LNKCAP_L0SEL
|
1441 PCI_EXP_LNKCAP_L1EL
);
1442 pci_set_long(pci_dev
->config
+ pos
+ PCI_EXP_LNKCAP
, lnkcap
);
1444 /* Link control, pass existing read-only copy. Should be writable? */
1446 /* Link status, only expose current speed and width */
1447 lnksta
= pci_get_word(pci_dev
->config
+ pos
+ PCI_EXP_LNKSTA
);
1448 lnksta
&= (PCI_EXP_LNKSTA_CLS
| PCI_EXP_LNKSTA_NLW
);
1449 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_LNKSTA
, lnksta
);
1452 /* Slot capabilities, control, status - not needed for endpoints */
1453 pci_set_long(pci_dev
->config
+ pos
+ PCI_EXP_SLTCAP
, 0);
1454 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_SLTCTL
, 0);
1455 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_SLTSTA
, 0);
1457 /* Root control, capabilities, status - not needed for endpoints */
1458 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_RTCTL
, 0);
1459 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_RTCAP
, 0);
1460 pci_set_long(pci_dev
->config
+ pos
+ PCI_EXP_RTSTA
, 0);
1462 /* Device capabilities/control 2, pass existing read-only copy */
1463 /* Link control 2, pass existing read-only copy */
1467 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_PCIX
, 0);
1472 /* Only expose the minimum, 8 byte capability */
1473 ret
= pci_add_capability(pci_dev
, PCI_CAP_ID_PCIX
, pos
, 8);
1478 assigned_dev_setup_cap_read(dev
, pos
, 8);
1480 /* Command register, clear upper bits, including extended modes */
1481 cmd
= pci_get_word(pci_dev
->config
+ pos
+ PCI_X_CMD
);
1482 cmd
&= (PCI_X_CMD_DPERR_E
| PCI_X_CMD_ERO
| PCI_X_CMD_MAX_READ
|
1483 PCI_X_CMD_MAX_SPLIT
);
1484 pci_set_word(pci_dev
->config
+ pos
+ PCI_X_CMD
, cmd
);
1486 /* Status register, update with emulated PCI bus location, clear
1487 * error bits, leave the rest. */
1488 status
= pci_get_long(pci_dev
->config
+ pos
+ PCI_X_STATUS
);
1489 status
&= ~(PCI_X_STATUS_BUS
| PCI_X_STATUS_DEVFN
);
1490 status
|= (pci_bus_num(pci_dev
->bus
) << 8) | pci_dev
->devfn
;
1491 status
&= ~(PCI_X_STATUS_SPL_DISC
| PCI_X_STATUS_UNX_SPL
|
1492 PCI_X_STATUS_SPL_ERR
);
1493 pci_set_long(pci_dev
->config
+ pos
+ PCI_X_STATUS
, status
);
1496 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_VPD
, 0);
1498 /* Direct R/W passthrough */
1499 ret
= pci_add_capability(pci_dev
, PCI_CAP_ID_VPD
, pos
, 8);
1504 assigned_dev_setup_cap_read(dev
, pos
, 8);
1506 /* direct write for cap content */
1507 assigned_dev_direct_config_write(dev
, pos
+ 2, 6);
1510 /* Devices can have multiple vendor capabilities, get them all */
1511 for (pos
= 0; (pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_VNDR
, pos
));
1512 pos
+= PCI_CAP_LIST_NEXT
) {
1513 uint8_t len
= pci_get_byte(pci_dev
->config
+ pos
+ PCI_CAP_FLAGS
);
1514 /* Direct R/W passthrough */
1515 ret
= pci_add_capability(pci_dev
, PCI_CAP_ID_VNDR
, pos
, len
);
1520 assigned_dev_setup_cap_read(dev
, pos
, len
);
1522 /* direct write for cap content */
1523 assigned_dev_direct_config_write(dev
, pos
+ 2, len
- 2);
1526 /* If real and virtual capability list status bits differ, virtualize the
1528 if ((pci_get_word(pci_dev
->config
+ PCI_STATUS
) & PCI_STATUS_CAP_LIST
) !=
1529 (assigned_dev_pci_read_byte(pci_dev
, PCI_STATUS
) &
1530 PCI_STATUS_CAP_LIST
)) {
1531 dev
->emulate_config_read
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1538 assigned_dev_msix_mmio_read(void *opaque
, hwaddr addr
,
1541 AssignedDevice
*adev
= opaque
;
1544 memcpy(&val
, (void *)((uint8_t *)adev
->msix_table
+ addr
), size
);
1549 static void assigned_dev_msix_mmio_write(void *opaque
, hwaddr addr
,
1550 uint64_t val
, unsigned size
)
1552 AssignedDevice
*adev
= opaque
;
1553 PCIDevice
*pdev
= &adev
->dev
;
1555 MSIXTableEntry orig
;
1558 if (i
>= adev
->msix_max
) {
1559 return; /* Drop write */
1562 ctrl
= pci_get_word(pdev
->config
+ pdev
->msix_cap
+ PCI_MSIX_FLAGS
);
1564 DEBUG("write to MSI-X table offset 0x%lx, val 0x%lx\n", addr
, val
);
1566 if (ctrl
& PCI_MSIX_FLAGS_ENABLE
) {
1567 orig
= adev
->msix_table
[i
];
1570 memcpy((uint8_t *)adev
->msix_table
+ addr
, &val
, size
);
1572 if (ctrl
& PCI_MSIX_FLAGS_ENABLE
) {
1573 MSIXTableEntry
*entry
= &adev
->msix_table
[i
];
1575 if (!assigned_dev_msix_masked(&orig
) &&
1576 assigned_dev_msix_masked(entry
)) {
1578 * Vector masked, disable it
1580 * XXX It's not clear if we can or should actually attempt
1581 * to mask or disable the interrupt. KVM doesn't have
1582 * support for pending bits and kvm_assign_set_msix_entry
1583 * doesn't modify the device hardware mask. Interrupts
1584 * while masked are simply not injected to the guest, so
1585 * are lost. Can we get away with always injecting an
1586 * interrupt on unmask?
1588 } else if (assigned_dev_msix_masked(&orig
) &&
1589 !assigned_dev_msix_masked(entry
)) {
1590 /* Vector unmasked */
1591 if (i
>= adev
->msi_virq_nr
|| adev
->msi_virq
[i
] < 0) {
1592 /* Previously unassigned vector, start from scratch */
1593 assigned_dev_update_msix(pdev
);
1596 /* Update an existing, previously masked vector */
1600 msg
.address
= entry
->addr_lo
|
1601 ((uint64_t)entry
->addr_hi
<< 32);
1602 msg
.data
= entry
->data
;
1604 ret
= kvm_irqchip_update_msi_route(kvm_state
,
1605 adev
->msi_virq
[i
], msg
);
1607 error_report("Error updating irq routing entry (%d)", ret
);
1614 static const MemoryRegionOps assigned_dev_msix_mmio_ops
= {
1615 .read
= assigned_dev_msix_mmio_read
,
1616 .write
= assigned_dev_msix_mmio_write
,
1617 .endianness
= DEVICE_NATIVE_ENDIAN
,
1619 .min_access_size
= 4,
1620 .max_access_size
= 8,
1623 .min_access_size
= 4,
1624 .max_access_size
= 8,
1628 static void assigned_dev_msix_reset(AssignedDevice
*dev
)
1630 MSIXTableEntry
*entry
;
1633 if (!dev
->msix_table
) {
1637 memset(dev
->msix_table
, 0, MSIX_PAGE_SIZE
);
1639 for (i
= 0, entry
= dev
->msix_table
; i
< dev
->msix_max
; i
++, entry
++) {
1640 entry
->ctrl
= cpu_to_le32(0x1); /* Masked */
1644 static int assigned_dev_register_msix_mmio(AssignedDevice
*dev
)
1646 dev
->msix_table
= mmap(NULL
, MSIX_PAGE_SIZE
, PROT_READ
|PROT_WRITE
,
1647 MAP_ANONYMOUS
|MAP_PRIVATE
, 0, 0);
1648 if (dev
->msix_table
== MAP_FAILED
) {
1649 error_report("fail allocate msix_table! %s", strerror(errno
));
1653 assigned_dev_msix_reset(dev
);
1655 memory_region_init_io(&dev
->mmio
, OBJECT(dev
), &assigned_dev_msix_mmio_ops
,
1656 dev
, "assigned-dev-msix", MSIX_PAGE_SIZE
);
1660 static void assigned_dev_unregister_msix_mmio(AssignedDevice
*dev
)
1662 if (!dev
->msix_table
) {
1666 memory_region_destroy(&dev
->mmio
);
1668 if (munmap(dev
->msix_table
, MSIX_PAGE_SIZE
) == -1) {
1669 error_report("error unmapping msix_table! %s", strerror(errno
));
1671 dev
->msix_table
= NULL
;
1674 static const VMStateDescription vmstate_assigned_device
= {
1675 .name
= "pci-assign",
1679 static void reset_assigned_device(DeviceState
*dev
)
1681 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
1682 AssignedDevice
*adev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1683 char reset_file
[64];
1684 const char reset
[] = "1";
1688 * If a guest is reset without being shutdown, MSI/MSI-X can still
1689 * be running. We want to return the device to a known state on
1690 * reset, so disable those here. We especially do not want MSI-X
1691 * enabled since it lives in MMIO space, which is about to get
1694 if (adev
->assigned_irq_type
== ASSIGNED_IRQ_MSIX
) {
1695 uint16_t ctrl
= pci_get_word(pci_dev
->config
+
1696 pci_dev
->msix_cap
+ PCI_MSIX_FLAGS
);
1698 pci_set_word(pci_dev
->config
+ pci_dev
->msix_cap
+ PCI_MSIX_FLAGS
,
1699 ctrl
& ~PCI_MSIX_FLAGS_ENABLE
);
1700 assigned_dev_update_msix(pci_dev
);
1701 } else if (adev
->assigned_irq_type
== ASSIGNED_IRQ_MSI
) {
1702 uint8_t ctrl
= pci_get_byte(pci_dev
->config
+
1703 pci_dev
->msi_cap
+ PCI_MSI_FLAGS
);
1705 pci_set_byte(pci_dev
->config
+ pci_dev
->msi_cap
+ PCI_MSI_FLAGS
,
1706 ctrl
& ~PCI_MSI_FLAGS_ENABLE
);
1707 assigned_dev_update_msi(pci_dev
);
1710 snprintf(reset_file
, sizeof(reset_file
),
1711 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/reset",
1712 adev
->host
.domain
, adev
->host
.bus
, adev
->host
.slot
,
1713 adev
->host
.function
);
1716 * Issue a device reset via pci-sysfs. Note that we use write(2) here
1717 * and ignore the return value because some kernels have a bug that
1718 * returns 0 rather than bytes written on success, sending us into an
1719 * infinite retry loop using other write mechanisms.
1721 fd
= open(reset_file
, O_WRONLY
);
1723 ret
= write(fd
, reset
, strlen(reset
));
1729 * When a 0 is written to the bus master register, the device is logically
1730 * disconnected from the PCI bus. This avoids further DMA transfers.
1732 assigned_dev_pci_write_config(pci_dev
, PCI_COMMAND
, 0, 1);
1735 static int assigned_initfn(struct PCIDevice
*pci_dev
)
1737 AssignedDevice
*dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1741 if (!kvm_enabled()) {
1742 error_report("pci-assign: error: requires KVM support");
1746 if (!dev
->host
.domain
&& !dev
->host
.bus
&& !dev
->host
.slot
&&
1747 !dev
->host
.function
) {
1748 error_report("pci-assign: error: no host device specified");
1753 * Set up basic config space access control. Will be further refined during
1754 * device initialization.
1756 assigned_dev_emulate_config_read(dev
, 0, PCI_CONFIG_SPACE_SIZE
);
1757 assigned_dev_direct_config_read(dev
, PCI_STATUS
, 2);
1758 assigned_dev_direct_config_read(dev
, PCI_REVISION_ID
, 1);
1759 assigned_dev_direct_config_read(dev
, PCI_CLASS_PROG
, 3);
1760 assigned_dev_direct_config_read(dev
, PCI_CACHE_LINE_SIZE
, 1);
1761 assigned_dev_direct_config_read(dev
, PCI_LATENCY_TIMER
, 1);
1762 assigned_dev_direct_config_read(dev
, PCI_BIST
, 1);
1763 assigned_dev_direct_config_read(dev
, PCI_CARDBUS_CIS
, 4);
1764 assigned_dev_direct_config_read(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2);
1765 assigned_dev_direct_config_read(dev
, PCI_SUBSYSTEM_ID
, 2);
1766 assigned_dev_direct_config_read(dev
, PCI_CAPABILITY_LIST
+ 1, 7);
1767 assigned_dev_direct_config_read(dev
, PCI_MIN_GNT
, 1);
1768 assigned_dev_direct_config_read(dev
, PCI_MAX_LAT
, 1);
1769 memcpy(dev
->emulate_config_write
, dev
->emulate_config_read
,
1770 sizeof(dev
->emulate_config_read
));
1772 if (get_real_device(dev
, dev
->host
.domain
, dev
->host
.bus
,
1773 dev
->host
.slot
, dev
->host
.function
)) {
1774 error_report("pci-assign: Error: Couldn't get real device (%s)!",
1779 if (assigned_device_pci_cap_init(pci_dev
) < 0) {
1783 /* intercept MSI-X entry page in the MMIO */
1784 if (dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSIX
) {
1785 if (assigned_dev_register_msix_mmio(dev
)) {
1790 /* handle real device's MMIO/PIO BARs */
1791 if (assigned_dev_register_regions(dev
->real_device
.regions
,
1792 dev
->real_device
.region_number
,
1797 /* handle interrupt routing */
1798 e_intx
= dev
->dev
.config
[PCI_INTERRUPT_PIN
] - 1;
1799 dev
->intpin
= e_intx
;
1800 dev
->intx_route
.mode
= PCI_INTX_DISABLED
;
1801 dev
->intx_route
.irq
= -1;
1803 /* assign device to guest */
1804 r
= assign_device(dev
);
1809 /* assign legacy INTx to the device */
1810 r
= assign_intx(dev
);
1815 assigned_dev_load_option_rom(dev
);
1817 add_boot_device_path(dev
->bootindex
, &pci_dev
->qdev
, NULL
);
1822 deassign_device(dev
);
1824 free_assigned_device(dev
);
1828 static void assigned_exitfn(struct PCIDevice
*pci_dev
)
1830 AssignedDevice
*dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1832 deassign_device(dev
);
1833 free_assigned_device(dev
);
1836 static Property assigned_dev_properties
[] = {
1837 DEFINE_PROP_PCI_HOST_DEVADDR("host", AssignedDevice
, host
),
1838 DEFINE_PROP_BIT("prefer_msi", AssignedDevice
, features
,
1839 ASSIGNED_DEVICE_PREFER_MSI_BIT
, false),
1840 DEFINE_PROP_BIT("share_intx", AssignedDevice
, features
,
1841 ASSIGNED_DEVICE_SHARE_INTX_BIT
, true),
1842 DEFINE_PROP_INT32("bootindex", AssignedDevice
, bootindex
, -1),
1843 DEFINE_PROP_STRING("configfd", AssignedDevice
, configfd_name
),
1844 DEFINE_PROP_END_OF_LIST(),
1847 static void assign_class_init(ObjectClass
*klass
, void *data
)
1849 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1850 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1852 k
->init
= assigned_initfn
;
1853 k
->exit
= assigned_exitfn
;
1854 k
->config_read
= assigned_dev_pci_read_config
;
1855 k
->config_write
= assigned_dev_pci_write_config
;
1856 dc
->props
= assigned_dev_properties
;
1857 dc
->vmsd
= &vmstate_assigned_device
;
1858 dc
->reset
= reset_assigned_device
;
1859 dc
->desc
= "KVM-based PCI passthrough";
1862 static const TypeInfo assign_info
= {
1863 .name
= "kvm-pci-assign",
1864 .parent
= TYPE_PCI_DEVICE
,
1865 .instance_size
= sizeof(AssignedDevice
),
1866 .class_init
= assign_class_init
,
1869 static void assign_register_types(void)
1871 type_register_static(&assign_info
);
1874 type_init(assign_register_types
)
1877 * Scan the assigned devices for the devices that have an option ROM, and then
1878 * load the corresponding ROM data to RAM. If an error occurs while loading an
1879 * option ROM, we just ignore that option ROM and continue with the next one.
1881 static void assigned_dev_load_option_rom(AssignedDevice
*dev
)
1883 char name
[32], rom_file
[64];
1889 /* If loading ROM from file, pci handles it */
1890 if (dev
->dev
.romfile
|| !dev
->dev
.rom_bar
) {
1894 snprintf(rom_file
, sizeof(rom_file
),
1895 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/rom",
1896 dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
1897 dev
->host
.function
);
1899 if (stat(rom_file
, &st
)) {
1903 if (access(rom_file
, F_OK
)) {
1904 error_report("pci-assign: Insufficient privileges for %s", rom_file
);
1908 /* Write "1" to the ROM file to enable it */
1909 fp
= fopen(rom_file
, "r+");
1914 if (fwrite(&val
, 1, 1, fp
) != 1) {
1917 fseek(fp
, 0, SEEK_SET
);
1919 snprintf(name
, sizeof(name
), "%s.rom",
1920 object_get_typename(OBJECT(dev
)));
1921 memory_region_init_ram(&dev
->dev
.rom
, OBJECT(dev
), name
, st
.st_size
);
1922 vmstate_register_ram(&dev
->dev
.rom
, &dev
->dev
.qdev
);
1923 ptr
= memory_region_get_ram_ptr(&dev
->dev
.rom
);
1924 memset(ptr
, 0xff, st
.st_size
);
1926 if (!fread(ptr
, 1, st
.st_size
, fp
)) {
1927 error_report("pci-assign: Cannot read from host %s", rom_file
);
1928 error_printf("Device option ROM contents are probably invalid "
1929 "(check dmesg).\nSkip option ROM probe with rombar=0, "
1930 "or load from file with romfile=\n");
1931 memory_region_destroy(&dev
->dev
.rom
);
1935 pci_register_bar(&dev
->dev
, PCI_ROM_SLOT
, 0, &dev
->dev
.rom
);
1936 dev
->dev
.has_rom
= true;
1938 /* Write "0" to disable ROM */
1939 fseek(fp
, 0, SEEK_SET
);
1941 if (!fwrite(&val
, 1, 1, fp
)) {
1942 DEBUG("%s\n", "Failed to disable pci-sysfs rom file");