hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/i386/pc.h"
  26 #include "hw/char/serial.h"
  27 #include "hw/i386/apic.h"
  28 #include "hw/block/fdc.h"
  29 #include "hw/ide.h"
  30 #include "hw/pci/pci.h"
  31 #include "monitor/monitor.h"
  32 #include "hw/nvram/fw_cfg.h"
  33 #include "hw/timer/hpet.h"
  34 #include "hw/i386/smbios.h"
  35 #include "hw/loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "hw/timer/mc146818rtc.h"
  39 #include "hw/timer/i8254.h"
  40 #include "hw/audio/pcspk.h"
  41 #include "hw/pci/msi.h"
  42 #include "hw/sysbus.h"
  43 #include "sysemu/sysemu.h"
  44 #include "sysemu/kvm.h"
  45 #include "kvm_i386.h"
  46 #include "hw/xen/xen.h"
  47 #include "sysemu/blockdev.h"
  48 #include "hw/block/block.h"
  49 #include "ui/qemu-spice.h"
  50 #include "exec/memory.h"
  51 #include "exec/address-spaces.h"
  52 #include "sysemu/arch_init.h"
  53 #include "qemu/bitmap.h"
  54 #include "qemu/config-file.h"
  55 #include "hw/acpi/acpi.h"
  56 #include "hw/cpu/icc_bus.h"
  57 #include "hw/boards.h"
  58
  59 /* debug PC/ISA interrupts */
  60 //#define DEBUG_IRQ
  61
  62 #ifdef DEBUG_IRQ
  63 #define DPRINTF(fmt, ...)                                       \
  64     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  65 #else
  66 #define DPRINTF(fmt, ...)
  67 #endif
  68
  69 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  70 #define ACPI_DATA_SIZE       0x10000
  71 #define BIOS_CFG_IOPORT 0x510
  72 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  73 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  74 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  75 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  76 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  77
  78 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000
  79
  80 #define E820_NR_ENTRIES         16
  81
  82 struct e820_entry {
  83     uint64_t address;
  84     uint64_t length;
  85     uint32_t type;
  86 } QEMU_PACKED __attribute((__aligned__(4)));
  87
  88 struct e820_table {
  89     uint32_t count;
  90     struct e820_entry entry[E820_NR_ENTRIES];
  91 } QEMU_PACKED __attribute((__aligned__(4)));
  92
  93 static struct e820_table e820_table;
  94 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  95
  96 void gsi_handler(void *opaque, int n, int level)
  97 {
  98     GSIState *s = opaque;
  99
 100     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
 101     if (n < ISA_NUM_IRQS) {
 102         qemu_set_irq(s->i8259_irq[n], level);
 103     }
 104     qemu_set_irq(s->ioapic_irq[n], level);
 105 }
 106
 107 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 108                            unsigned size)
 109 {
 110 }
 111
 112 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 113 {
 114     return 0xffffffffffffffffULL;
 115 }
 116
 117 /* MSDOS compatibility mode FPU exception support */
 118 static qemu_irq ferr_irq;
 119
 120 void pc_register_ferr_irq(qemu_irq irq)
 121 {
 122     ferr_irq = irq;
 123 }
 124
 125 /* XXX: add IGNNE support */
 126 void cpu_set_ferr(CPUX86State *s)
 127 {
 128     qemu_irq_raise(ferr_irq);
 129 }
 130
 131 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 132                            unsigned size)
 133 {
 134     qemu_irq_lower(ferr_irq);
 135 }
 136
 137 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 138 {
 139     return 0xffffffffffffffffULL;
 140 }
 141
 142 /* TSC handling */
 143 uint64_t cpu_get_tsc(CPUX86State *env)
 144 {
 145     return cpu_get_ticks();
 146 }
 147
 148 /* SMM support */
 149
 150 static cpu_set_smm_t smm_set;
 151 static void *smm_arg;
 152
 153 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 154 {
 155     assert(smm_set == NULL);
 156     assert(smm_arg == NULL);
 157     smm_set = callback;
 158     smm_arg = arg;
 159 }
 160
 161 void cpu_smm_update(CPUX86State *env)
 162 {
 163     if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) {
 164         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 165     }
 166 }
 167
 168
 169 /* IRQ handling */
 170 int cpu_get_pic_interrupt(CPUX86State *env)
 171 {
 172     int intno;
 173
 174     intno = apic_get_interrupt(env->apic_state);
 175     if (intno >= 0) {
 176         return intno;
 177     }
 178     /* read the irq from the PIC */
 179     if (!apic_accept_pic_intr(env->apic_state)) {
 180         return -1;
 181     }
 182
 183     intno = pic_read_irq(isa_pic);
 184     return intno;
 185 }
 186
 187 static void pic_irq_request(void *opaque, int irq, int level)
 188 {
 189     CPUState *cs = first_cpu;
 190     X86CPU *cpu = X86_CPU(cs);
 191     CPUX86State *env = &cpu->env;
 192
 193     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 194     if (env->apic_state) {
 195         while (cs) {
 196             cpu = X86_CPU(cs);
 197             env = &cpu->env;
 198             if (apic_accept_pic_intr(env->apic_state)) {
 199                 apic_deliver_pic_intr(env->apic_state, level);
 200             }
 201             cs = cs->next_cpu;
 202         }
 203     } else {
 204         if (level) {
 205             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 206         } else {
 207             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 208         }
 209     }
 210 }
 211
 212 /* PC cmos mappings */
 213
 214 #define REG_EQUIPMENT_BYTE          0x14
 215
 216 static int cmos_get_fd_drive_type(FDriveType fd0)
 217 {
 218     int val;
 219
 220     switch (fd0) {
 221     case FDRIVE_DRV_144:
 222         /* 1.44 Mb 3"5 drive */
 223         val = 4;
 224         break;
 225     case FDRIVE_DRV_288:
 226         /* 2.88 Mb 3"5 drive */
 227         val = 5;
 228         break;
 229     case FDRIVE_DRV_120:
 230         /* 1.2 Mb 5"5 drive */
 231         val = 2;
 232         break;
 233     case FDRIVE_DRV_NONE:
 234     default:
 235         val = 0;
 236         break;
 237     }
 238     return val;
 239 }
 240
 241 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 242                          int16_t cylinders, int8_t heads, int8_t sectors)
 243 {
 244     rtc_set_memory(s, type_ofs, 47);
 245     rtc_set_memory(s, info_ofs, cylinders);
 246     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 247     rtc_set_memory(s, info_ofs + 2, heads);
 248     rtc_set_memory(s, info_ofs + 3, 0xff);
 249     rtc_set_memory(s, info_ofs + 4, 0xff);
 250     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 251     rtc_set_memory(s, info_ofs + 6, cylinders);
 252     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 253     rtc_set_memory(s, info_ofs + 8, sectors);
 254 }
 255
 256 /* convert boot_device letter to something recognizable by the bios */
 257 static int boot_device2nibble(char boot_device)
 258 {
 259     switch(boot_device) {
 260     case 'a':
 261     case 'b':
 262         return 0x01; /* floppy boot */
 263     case 'c':
 264         return 0x02; /* hard drive boot */
 265     case 'd':
 266         return 0x03; /* CD-ROM boot */
 267     case 'n':
 268         return 0x04; /* Network boot */
 269     }
 270     return 0;
 271 }
 272
 273 static int set_boot_dev(ISADevice *s, const char *boot_device)
 274 {
 275 #define PC_MAX_BOOT_DEVICES 3
 276     int nbds, bds[3] = { 0, };
 277     int i;
 278
 279     nbds = strlen(boot_device);
 280     if (nbds > PC_MAX_BOOT_DEVICES) {
 281         error_report("Too many boot devices for PC");
 282         return(1);
 283     }
 284     for (i = 0; i < nbds; i++) {
 285         bds[i] = boot_device2nibble(boot_device[i]);
 286         if (bds[i] == 0) {
 287             error_report("Invalid boot device for PC: '%c'",
 288                          boot_device[i]);
 289             return(1);
 290         }
 291     }
 292     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 293     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 294     return(0);
 295 }
 296
 297 static int pc_boot_set(void *opaque, const char *boot_device)
 298 {
 299     return set_boot_dev(opaque, boot_device);
 300 }
 301
 302 typedef struct pc_cmos_init_late_arg {
 303     ISADevice *rtc_state;
 304     BusState *idebus[2];
 305 } pc_cmos_init_late_arg;
 306
 307 static void pc_cmos_init_late(void *opaque)
 308 {
 309     pc_cmos_init_late_arg *arg = opaque;
 310     ISADevice *s = arg->rtc_state;
 311     int16_t cylinders;
 312     int8_t heads, sectors;
 313     int val;
 314     int i, trans;
 315
 316     val = 0;
 317     if (ide_get_geometry(arg->idebus[0], 0,
 318                          &cylinders, &heads, &sectors) >= 0) {
 319         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 320         val |= 0xf0;
 321     }
 322     if (ide_get_geometry(arg->idebus[0], 1,
 323                          &cylinders, &heads, &sectors) >= 0) {
 324         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 325         val |= 0x0f;
 326     }
 327     rtc_set_memory(s, 0x12, val);
 328
 329     val = 0;
 330     for (i = 0; i < 4; i++) {
 331         /* NOTE: ide_get_geometry() returns the physical
 332            geometry.  It is always such that: 1 <= sects <= 63, 1
 333            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 334            geometry can be different if a translation is done. */
 335         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 336                              &cylinders, &heads, &sectors) >= 0) {
 337             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 338             assert((trans & ~3) == 0);
 339             val |= trans << (i * 2);
 340         }
 341     }
 342     rtc_set_memory(s, 0x39, val);
 343
 344     qemu_unregister_reset(pc_cmos_init_late, opaque);
 345 }
 346
 347 typedef struct RTCCPUHotplugArg {
 348     Notifier cpu_added_notifier;
 349     ISADevice *rtc_state;
 350 } RTCCPUHotplugArg;
 351
 352 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
 353 {
 354     RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
 355                                          cpu_added_notifier);
 356     ISADevice *s = arg->rtc_state;
 357
 358     /* increment the number of CPUs */
 359     rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
 360 }
 361
 362 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 363                   const char *boot_device,
 364                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 365                   ISADevice *s)
 366 {
 367     int val, nb, i;
 368     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 369     static pc_cmos_init_late_arg arg;
 370     static RTCCPUHotplugArg cpu_hotplug_cb;
 371
 372     /* various important CMOS locations needed by PC/Bochs bios */
 373
 374     /* memory size */
 375     /* base memory (first MiB) */
 376     val = MIN(ram_size / 1024, 640);
 377     rtc_set_memory(s, 0x15, val);
 378     rtc_set_memory(s, 0x16, val >> 8);
 379     /* extended memory (next 64MiB) */
 380     if (ram_size > 1024 * 1024) {
 381         val = (ram_size - 1024 * 1024) / 1024;
 382     } else {
 383         val = 0;
 384     }
 385     if (val > 65535)
 386         val = 65535;
 387     rtc_set_memory(s, 0x17, val);
 388     rtc_set_memory(s, 0x18, val >> 8);
 389     rtc_set_memory(s, 0x30, val);
 390     rtc_set_memory(s, 0x31, val >> 8);
 391     /* memory between 16MiB and 4GiB */
 392     if (ram_size > 16 * 1024 * 1024) {
 393         val = (ram_size - 16 * 1024 * 1024) / 65536;
 394     } else {
 395         val = 0;
 396     }
 397     if (val > 65535)
 398         val = 65535;
 399     rtc_set_memory(s, 0x34, val);
 400     rtc_set_memory(s, 0x35, val >> 8);
 401     /* memory above 4GiB */
 402     val = above_4g_mem_size / 65536;
 403     rtc_set_memory(s, 0x5b, val);
 404     rtc_set_memory(s, 0x5c, val >> 8);
 405     rtc_set_memory(s, 0x5d, val >> 16);
 406
 407     /* set the number of CPU */
 408     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 409     /* init CPU hotplug notifier */
 410     cpu_hotplug_cb.rtc_state = s;
 411     cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
 412     qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
 413
 414     if (set_boot_dev(s, boot_device)) {
 415         exit(1);
 416     }
 417
 418     /* floppy type */
 419     if (floppy) {
 420         for (i = 0; i < 2; i++) {
 421             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 422         }
 423     }
 424     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 425         cmos_get_fd_drive_type(fd_type[1]);
 426     rtc_set_memory(s, 0x10, val);
 427
 428     val = 0;
 429     nb = 0;
 430     if (fd_type[0] < FDRIVE_DRV_NONE) {
 431         nb++;
 432     }
 433     if (fd_type[1] < FDRIVE_DRV_NONE) {
 434         nb++;
 435     }
 436     switch (nb) {
 437     case 0:
 438         break;
 439     case 1:
 440         val |= 0x01; /* 1 drive, ready for boot */
 441         break;
 442     case 2:
 443         val |= 0x41; /* 2 drives, ready for boot */
 444         break;
 445     }
 446     val |= 0x02; /* FPU is there */
 447     val |= 0x04; /* PS/2 mouse installed */
 448     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 449
 450     /* hard drives */
 451     arg.rtc_state = s;
 452     arg.idebus[0] = idebus0;
 453     arg.idebus[1] = idebus1;
 454     qemu_register_reset(pc_cmos_init_late, &arg);
 455 }
 456
 457 #define TYPE_PORT92 "port92"
 458 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 459
 460 /* port 92 stuff: could be split off */
 461 typedef struct Port92State {
 462     ISADevice parent_obj;
 463
 464     MemoryRegion io;
 465     uint8_t outport;
 466     qemu_irq *a20_out;
 467 } Port92State;
 468
 469 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 470                          unsigned size)
 471 {
 472     Port92State *s = opaque;
 473
 474     DPRINTF("port92: write 0x%02x\n", val);
 475     s->outport = val;
 476     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 477     if (val & 1) {
 478         qemu_system_reset_request();
 479     }
 480 }
 481
 482 static uint64_t port92_read(void *opaque, hwaddr addr,
 483                             unsigned size)
 484 {
 485     Port92State *s = opaque;
 486     uint32_t ret;
 487
 488     ret = s->outport;
 489     DPRINTF("port92: read 0x%02x\n", ret);
 490     return ret;
 491 }
 492
 493 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 494 {
 495     Port92State *s = PORT92(dev);
 496
 497     s->a20_out = a20_out;
 498 }
 499
 500 static const VMStateDescription vmstate_port92_isa = {
 501     .name = "port92",
 502     .version_id = 1,
 503     .minimum_version_id = 1,
 504     .minimum_version_id_old = 1,
 505     .fields      = (VMStateField []) {
 506         VMSTATE_UINT8(outport, Port92State),
 507         VMSTATE_END_OF_LIST()
 508     }
 509 };
 510
 511 static void port92_reset(DeviceState *d)
 512 {
 513     Port92State *s = PORT92(d);
 514
 515     s->outport &= ~1;
 516 }
 517
 518 static const MemoryRegionOps port92_ops = {
 519     .read = port92_read,
 520     .write = port92_write,
 521     .impl = {
 522         .min_access_size = 1,
 523         .max_access_size = 1,
 524     },
 525     .endianness = DEVICE_LITTLE_ENDIAN,
 526 };
 527
 528 static void port92_initfn(Object *obj)
 529 {
 530     Port92State *s = PORT92(obj);
 531
 532     memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
 533
 534     s->outport = 0;
 535 }
 536
 537 static void port92_realizefn(DeviceState *dev, Error **errp)
 538 {
 539     ISADevice *isadev = ISA_DEVICE(dev);
 540     Port92State *s = PORT92(dev);
 541
 542     isa_register_ioport(isadev, &s->io, 0x92);
 543 }
 544
 545 static void port92_class_initfn(ObjectClass *klass, void *data)
 546 {
 547     DeviceClass *dc = DEVICE_CLASS(klass);
 548
 549     dc->no_user = 1;
 550     dc->realize = port92_realizefn;
 551     dc->reset = port92_reset;
 552     dc->vmsd = &vmstate_port92_isa;
 553 }
 554
 555 static const TypeInfo port92_info = {
 556     .name          = TYPE_PORT92,
 557     .parent        = TYPE_ISA_DEVICE,
 558     .instance_size = sizeof(Port92State),
 559     .instance_init = port92_initfn,
 560     .class_init    = port92_class_initfn,
 561 };
 562
 563 static void port92_register_types(void)
 564 {
 565     type_register_static(&port92_info);
 566 }
 567
 568 type_init(port92_register_types)
 569
 570 static void handle_a20_line_change(void *opaque, int irq, int level)
 571 {
 572     X86CPU *cpu = opaque;
 573
 574     /* XXX: send to all CPUs ? */
 575     /* XXX: add logic to handle multiple A20 line sources */
 576     x86_cpu_set_a20(cpu, level);
 577 }
 578
 579 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 580 {
 581     int index = le32_to_cpu(e820_table.count);
 582     struct e820_entry *entry;
 583
 584     if (index >= E820_NR_ENTRIES)
 585         return -EBUSY;
 586     entry = &e820_table.entry[index++];
 587
 588     entry->address = cpu_to_le64(address);
 589     entry->length = cpu_to_le64(length);
 590     entry->type = cpu_to_le32(type);
 591
 592     e820_table.count = cpu_to_le32(index);
 593     return index;
 594 }
 595
 596 /* Calculates the limit to CPU APIC ID values
 597  *
 598  * This function returns the limit for the APIC ID value, so that all
 599  * CPU APIC IDs are < pc_apic_id_limit().
 600  *
 601  * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
 602  */
 603 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
 604 {
 605     return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
 606 }
 607
 608 static FWCfgState *bochs_bios_init(void)
 609 {
 610     FWCfgState *fw_cfg;
 611     uint8_t *smbios_table;
 612     size_t smbios_len;
 613     uint64_t *numa_fw_cfg;
 614     int i, j;
 615     unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
 616
 617     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 618     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 619      *
 620      * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
 621      * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
 622      * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
 623      * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
 624      * may see".
 625      *
 626      * So, this means we must not use max_cpus, here, but the maximum possible
 627      * APIC ID value, plus one.
 628      *
 629      * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
 630      *     the APIC ID, not the "CPU index"
 631      */
 632     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
 633     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 634     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 635     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 636                      acpi_tables, acpi_tables_len);
 637     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 638
 639     smbios_table = smbios_get_table(&smbios_len);
 640     if (smbios_table)
 641         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 642                          smbios_table, smbios_len);
 643     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 644                      &e820_table, sizeof(e820_table));
 645
 646     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 647     /* allocate memory for the NUMA channel: one (64bit) word for the number
 648      * of nodes, one word for each VCPU->node and one word for each node to
 649      * hold the amount of memory.
 650      */
 651     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 652     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 653     for (i = 0; i < max_cpus; i++) {
 654         unsigned int apic_id = x86_cpu_apic_id_from_index(i);
 655         assert(apic_id < apic_id_limit);
 656         for (j = 0; j < nb_numa_nodes; j++) {
 657             if (test_bit(i, node_cpumask[j])) {
 658                 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
 659                 break;
 660             }
 661         }
 662     }
 663     for (i = 0; i < nb_numa_nodes; i++) {
 664         numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
 665     }
 666     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 667                      (1 + apic_id_limit + nb_numa_nodes) *
 668                      sizeof(*numa_fw_cfg));
 669
 670     return fw_cfg;
 671 }
 672
 673 static long get_file_size(FILE *f)
 674 {
 675     long where, size;
 676
 677     /* XXX: on Unix systems, using fstat() probably makes more sense */
 678
 679     where = ftell(f);
 680     fseek(f, 0, SEEK_END);
 681     size = ftell(f);
 682     fseek(f, where, SEEK_SET);
 683
 684     return size;
 685 }
 686
 687 static void load_linux(FWCfgState *fw_cfg,
 688                        const char *kernel_filename,
 689                        const char *initrd_filename,
 690                        const char *kernel_cmdline,
 691                        hwaddr max_ram_size)
 692 {
 693     uint16_t protocol;
 694     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 695     uint32_t initrd_max;
 696     uint8_t header[8192], *setup, *kernel, *initrd_data;
 697     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 698     FILE *f;
 699     char *vmode;
 700
 701     /* Align to 16 bytes as a paranoia measure */
 702     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 703
 704     /* load the kernel header */
 705     f = fopen(kernel_filename, "rb");
 706     if (!f || !(kernel_size = get_file_size(f)) ||
 707         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 708         MIN(ARRAY_SIZE(header), kernel_size)) {
 709         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 710                 kernel_filename, strerror(errno));
 711         exit(1);
 712     }
 713
 714     /* kernel protocol version */
 715 #if 0
 716     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 717 #endif
 718     if (ldl_p(header+0x202) == 0x53726448) {
 719         protocol = lduw_p(header+0x206);
 720     } else {
 721         /* This looks like a multiboot kernel. If it is, let's stop
 722            treating it like a Linux kernel. */
 723         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 724                            kernel_cmdline, kernel_size, header)) {
 725             return;
 726         }
 727         protocol = 0;
 728     }
 729
 730     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 731         /* Low kernel */
 732         real_addr    = 0x90000;
 733         cmdline_addr = 0x9a000 - cmdline_size;
 734         prot_addr    = 0x10000;
 735     } else if (protocol < 0x202) {
 736         /* High but ancient kernel */
 737         real_addr    = 0x90000;
 738         cmdline_addr = 0x9a000 - cmdline_size;
 739         prot_addr    = 0x100000;
 740     } else {
 741         /* High and recent kernel */
 742         real_addr    = 0x10000;
 743         cmdline_addr = 0x20000;
 744         prot_addr    = 0x100000;
 745     }
 746
 747 #if 0
 748     fprintf(stderr,
 749             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 750             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 751             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 752             real_addr,
 753             cmdline_addr,
 754             prot_addr);
 755 #endif
 756
 757     /* highest address for loading the initrd */
 758     if (protocol >= 0x203) {
 759         initrd_max = ldl_p(header+0x22c);
 760     } else {
 761         initrd_max = 0x37ffffff;
 762     }
 763
 764     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 765         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 766
 767     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 768     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 769     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 770
 771     if (protocol >= 0x202) {
 772         stl_p(header+0x228, cmdline_addr);
 773     } else {
 774         stw_p(header+0x20, 0xA33F);
 775         stw_p(header+0x22, cmdline_addr-real_addr);
 776     }
 777
 778     /* handle vga= parameter */
 779     vmode = strstr(kernel_cmdline, "vga=");
 780     if (vmode) {
 781         unsigned int video_mode;
 782         /* skip "vga=" */
 783         vmode += 4;
 784         if (!strncmp(vmode, "normal", 6)) {
 785             video_mode = 0xffff;
 786         } else if (!strncmp(vmode, "ext", 3)) {
 787             video_mode = 0xfffe;
 788         } else if (!strncmp(vmode, "ask", 3)) {
 789             video_mode = 0xfffd;
 790         } else {
 791             video_mode = strtol(vmode, NULL, 0);
 792         }
 793         stw_p(header+0x1fa, video_mode);
 794     }
 795
 796     /* loader type */
 797     /* High nybble = B reserved for QEMU; low nybble is revision number.
 798        If this code is substantially changed, you may want to consider
 799        incrementing the revision. */
 800     if (protocol >= 0x200) {
 801         header[0x210] = 0xB0;
 802     }
 803     /* heap */
 804     if (protocol >= 0x201) {
 805         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 806         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 807     }
 808
 809     /* load initrd */
 810     if (initrd_filename) {
 811         if (protocol < 0x200) {
 812             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 813             exit(1);
 814         }
 815
 816         initrd_size = get_image_size(initrd_filename);
 817         if (initrd_size < 0) {
 818             fprintf(stderr, "qemu: error reading initrd %s\n",
 819                     initrd_filename);
 820             exit(1);
 821         }
 822
 823         initrd_addr = (initrd_max-initrd_size) & ~4095;
 824
 825         initrd_data = g_malloc(initrd_size);
 826         load_image(initrd_filename, initrd_data);
 827
 828         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 829         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 830         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 831
 832         stl_p(header+0x218, initrd_addr);
 833         stl_p(header+0x21c, initrd_size);
 834     }
 835
 836     /* load kernel and setup */
 837     setup_size = header[0x1f1];
 838     if (setup_size == 0) {
 839         setup_size = 4;
 840     }
 841     setup_size = (setup_size+1)*512;
 842     kernel_size -= setup_size;
 843
 844     setup  = g_malloc(setup_size);
 845     kernel = g_malloc(kernel_size);
 846     fseek(f, 0, SEEK_SET);
 847     if (fread(setup, 1, setup_size, f) != setup_size) {
 848         fprintf(stderr, "fread() failed\n");
 849         exit(1);
 850     }
 851     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 852         fprintf(stderr, "fread() failed\n");
 853         exit(1);
 854     }
 855     fclose(f);
 856     memcpy(setup, header, MIN(sizeof(header), setup_size));
 857
 858     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 859     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 860     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 861
 862     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 863     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 864     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 865
 866     option_rom[nb_option_roms].name = "linuxboot.bin";
 867     option_rom[nb_option_roms].bootindex = 0;
 868     nb_option_roms++;
 869 }
 870
 871 #define NE2000_NB_MAX 6
 872
 873 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 874                                               0x280, 0x380 };
 875 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 876
 877 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 878 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 879
 880 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 881 {
 882     static int nb_ne2k = 0;
 883
 884     if (nb_ne2k == NE2000_NB_MAX)
 885         return;
 886     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 887                     ne2000_irq[nb_ne2k], nd);
 888     nb_ne2k++;
 889 }
 890
 891 DeviceState *cpu_get_current_apic(void)
 892 {
 893     if (current_cpu) {
 894         X86CPU *cpu = X86_CPU(current_cpu);
 895         return cpu->env.apic_state;
 896     } else {
 897         return NULL;
 898     }
 899 }
 900
 901 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 902 {
 903     X86CPU *cpu = opaque;
 904
 905     if (level) {
 906         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
 907     }
 908 }
 909
 910 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
 911                           DeviceState *icc_bridge, Error **errp)
 912 {
 913     X86CPU *cpu;
 914     Error *local_err = NULL;
 915
 916     cpu = cpu_x86_create(cpu_model, icc_bridge, errp);
 917     if (!cpu) {
 918         return cpu;
 919     }
 920
 921     object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
 922     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 923
 924     if (local_err) {
 925         if (cpu != NULL) {
 926             object_unref(OBJECT(cpu));
 927             cpu = NULL;
 928         }
 929         error_propagate(errp, local_err);
 930     }
 931     return cpu;
 932 }
 933
 934 static const char *current_cpu_model;
 935
 936 void pc_hot_add_cpu(const int64_t id, Error **errp)
 937 {
 938     DeviceState *icc_bridge;
 939     int64_t apic_id = x86_cpu_apic_id_from_index(id);
 940
 941     if (id < 0) {
 942         error_setg(errp, "Invalid CPU id: %" PRIi64, id);
 943         return;
 944     }
 945
 946     if (cpu_exists(apic_id)) {
 947         error_setg(errp, "Unable to add CPU: %" PRIi64
 948                    ", it already exists", id);
 949         return;
 950     }
 951
 952     if (id >= max_cpus) {
 953         error_setg(errp, "Unable to add CPU: %" PRIi64
 954                    ", max allowed: %d", id, max_cpus - 1);
 955         return;
 956     }
 957
 958     icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
 959                                                  TYPE_ICC_BRIDGE, NULL));
 960     pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
 961 }
 962
 963 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
 964 {
 965     int i;
 966     X86CPU *cpu = NULL;
 967     Error *error = NULL;
 968
 969     /* init CPUs */
 970     if (cpu_model == NULL) {
 971 #ifdef TARGET_X86_64
 972         cpu_model = "qemu64";
 973 #else
 974         cpu_model = "qemu32";
 975 #endif
 976     }
 977     current_cpu_model = cpu_model;
 978
 979     for (i = 0; i < smp_cpus; i++) {
 980         cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
 981                          icc_bridge, &error);
 982         if (error) {
 983             fprintf(stderr, "%s\n", error_get_pretty(error));
 984             error_free(error);
 985             exit(1);
 986         }
 987     }
 988
 989     /* map APIC MMIO area if CPU has APIC */
 990     if (cpu && cpu->env.apic_state) {
 991         /* XXX: what if the base changes? */
 992         sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
 993                                 APIC_DEFAULT_ADDRESS, 0x1000);
 994     }
 995 }
 996
 997 /* pci-info ROM file. Little endian format */
 998 typedef struct PcRomPciInfo {
 999     uint64_t w32_min;
1000     uint64_t w32_max;
1001     uint64_t w64_min;
1002     uint64_t w64_max;
1003 } PcRomPciInfo;
1004
1005 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
1006 {
1007     PcRomPciInfo *info;
1008     if (!guest_info->has_pci_info || !guest_info->fw_cfg) {
1009         return;
1010     }
1011
1012     info = g_malloc(sizeof *info);
1013     info->w32_min = cpu_to_le64(guest_info->pci_info.w32.begin);
1014     info->w32_max = cpu_to_le64(guest_info->pci_info.w32.end);
1015     info->w64_min = cpu_to_le64(guest_info->pci_info.w64.begin);
1016     info->w64_max = cpu_to_le64(guest_info->pci_info.w64.end);
1017     /* Pass PCI hole info to guest via a side channel.
1018      * Required so guest PCI enumeration does the right thing. */
1019     fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
1020 }
1021
1022 typedef struct PcGuestInfoState {
1023     PcGuestInfo info;
1024     Notifier machine_done;
1025 } PcGuestInfoState;
1026
1027 static
1028 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1029 {
1030     PcGuestInfoState *guest_info_state = container_of(notifier,
1031                                                       PcGuestInfoState,
1032                                                       machine_done);
1033     pc_fw_cfg_guest_info(&guest_info_state->info);
1034 }
1035
1036 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1037                                 ram_addr_t above_4g_mem_size)
1038 {
1039     PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1040     PcGuestInfo *guest_info = &guest_info_state->info;
1041
1042     guest_info->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
1043     if (sizeof(hwaddr) == 4) {
1044         guest_info->pci_info.w64.begin = 0;
1045         guest_info->pci_info.w64.end = 0;
1046     } else {
1047         /*
1048          * BIOS does not set MTRR entries for the 64 bit window, so no need to
1049          * align address to power of two.  Align address at 1G, this makes sure
1050          * it can be exactly covered with a PAT entry even when using huge
1051          * pages.
1052          */
1053         guest_info->pci_info.w64.begin =
1054             ROUND_UP((0x1ULL << 32) + above_4g_mem_size, 0x1ULL << 30);
1055         guest_info->pci_info.w64.end = guest_info->pci_info.w64.begin +
1056             (0x1ULL << 62);
1057         assert(guest_info->pci_info.w64.begin <= guest_info->pci_info.w64.end);
1058     }
1059
1060     guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1061     qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1062     return guest_info;
1063 }
1064
1065 void pc_acpi_init(const char *default_dsdt)
1066 {
1067     char *filename;
1068
1069     if (acpi_tables != NULL) {
1070         /* manually set via -acpitable, leave it alone */
1071         return;
1072     }
1073
1074     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1075     if (filename == NULL) {
1076         fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1077     } else {
1078         char *arg;
1079         QemuOpts *opts;
1080         Error *err = NULL;
1081
1082         arg = g_strdup_printf("file=%s", filename);
1083
1084         /* creates a deep copy of "arg" */
1085         opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1086         g_assert(opts != NULL);
1087
1088         acpi_table_add(opts, &err);
1089         if (err) {
1090             fprintf(stderr, "WARNING: failed to load %s: %s\n", filename,
1091                     error_get_pretty(err));
1092             error_free(err);
1093         }
1094         g_free(arg);
1095         g_free(filename);
1096     }
1097 }
1098
1099 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
1100                            const char *kernel_filename,
1101                            const char *kernel_cmdline,
1102                            const char *initrd_filename,
1103                            ram_addr_t below_4g_mem_size,
1104                            ram_addr_t above_4g_mem_size,
1105                            MemoryRegion *rom_memory,
1106                            MemoryRegion **ram_memory,
1107                            PcGuestInfo *guest_info)
1108 {
1109     int linux_boot, i;
1110     MemoryRegion *ram, *option_rom_mr;
1111     MemoryRegion *ram_below_4g, *ram_above_4g;
1112     FWCfgState *fw_cfg;
1113
1114     linux_boot = (kernel_filename != NULL);
1115
1116     /* Allocate RAM.  We allocate it as a single memory region and use
1117      * aliases to address portions of it, mostly for backwards compatibility
1118      * with older qemus that used qemu_ram_alloc().
1119      */
1120     ram = g_malloc(sizeof(*ram));
1121     memory_region_init_ram(ram, NULL, "pc.ram",
1122                            below_4g_mem_size + above_4g_mem_size);
1123     vmstate_register_ram_global(ram);
1124     *ram_memory = ram;
1125     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1126     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1127                              0, below_4g_mem_size);
1128     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1129     if (above_4g_mem_size > 0) {
1130         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1131         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1132                                  below_4g_mem_size, above_4g_mem_size);
1133         memory_region_add_subregion(system_memory, 0x100000000ULL,
1134                                     ram_above_4g);
1135     }
1136
1137
1138     /* Initialize PC system firmware */
1139     pc_system_firmware_init(rom_memory);
1140
1141     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1142     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1143     vmstate_register_ram_global(option_rom_mr);
1144     memory_region_add_subregion_overlap(rom_memory,
1145                                         PC_ROM_MIN_VGA,
1146                                         option_rom_mr,
1147                                         1);
1148
1149     fw_cfg = bochs_bios_init();
1150     rom_set_fw(fw_cfg);
1151
1152     if (linux_boot) {
1153         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1154     }
1155
1156     for (i = 0; i < nb_option_roms; i++) {
1157         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1158     }
1159     guest_info->fw_cfg = fw_cfg;
1160     return fw_cfg;
1161 }
1162
1163 qemu_irq *pc_allocate_cpu_irq(void)
1164 {
1165     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1166 }
1167
1168 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1169 {
1170     DeviceState *dev = NULL;
1171
1172     if (pci_bus) {
1173         PCIDevice *pcidev = pci_vga_init(pci_bus);
1174         dev = pcidev ? &pcidev->qdev : NULL;
1175     } else if (isa_bus) {
1176         ISADevice *isadev = isa_vga_init(isa_bus);
1177         dev = isadev ? DEVICE(isadev) : NULL;
1178     }
1179     return dev;
1180 }
1181
1182 static void cpu_request_exit(void *opaque, int irq, int level)
1183 {
1184     CPUState *cpu = current_cpu;
1185
1186     if (cpu && level) {
1187         cpu_exit(cpu);
1188     }
1189 }
1190
1191 static const MemoryRegionOps ioport80_io_ops = {
1192     .write = ioport80_write,
1193     .read = ioport80_read,
1194     .endianness = DEVICE_NATIVE_ENDIAN,
1195     .impl = {
1196         .min_access_size = 1,
1197         .max_access_size = 1,
1198     },
1199 };
1200
1201 static const MemoryRegionOps ioportF0_io_ops = {
1202     .write = ioportF0_write,
1203     .read = ioportF0_read,
1204     .endianness = DEVICE_NATIVE_ENDIAN,
1205     .impl = {
1206         .min_access_size = 1,
1207         .max_access_size = 1,
1208     },
1209 };
1210
1211 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1212                           ISADevice **rtc_state,
1213                           ISADevice **floppy,
1214                           bool no_vmport)
1215 {
1216     int i;
1217     DriveInfo *fd[MAX_FD];
1218     DeviceState *hpet = NULL;
1219     int pit_isa_irq = 0;
1220     qemu_irq pit_alt_irq = NULL;
1221     qemu_irq rtc_irq = NULL;
1222     qemu_irq *a20_line;
1223     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1224     qemu_irq *cpu_exit_irq;
1225     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1226     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1227
1228     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1229     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1230
1231     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1232     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1233
1234     /*
1235      * Check if an HPET shall be created.
1236      *
1237      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1238      * when the HPET wants to take over. Thus we have to disable the latter.
1239      */
1240     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1241         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1242
1243         if (hpet) {
1244             for (i = 0; i < GSI_NUM_PINS; i++) {
1245                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1246             }
1247             pit_isa_irq = -1;
1248             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1249             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1250         }
1251     }
1252     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1253
1254     qemu_register_boot_set(pc_boot_set, *rtc_state);
1255
1256     if (!xen_enabled()) {
1257         if (kvm_irqchip_in_kernel()) {
1258             pit = kvm_pit_init(isa_bus, 0x40);
1259         } else {
1260             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1261         }
1262         if (hpet) {
1263             /* connect PIT to output control line of the HPET */
1264             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1265         }
1266         pcspk_init(isa_bus, pit);
1267     }
1268
1269     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1270         if (serial_hds[i]) {
1271             serial_isa_init(isa_bus, i, serial_hds[i]);
1272         }
1273     }
1274
1275     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1276         if (parallel_hds[i]) {
1277             parallel_init(isa_bus, i, parallel_hds[i]);
1278         }
1279     }
1280
1281     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1282     i8042 = isa_create_simple(isa_bus, "i8042");
1283     i8042_setup_a20_line(i8042, &a20_line[0]);
1284     if (!no_vmport) {
1285         vmport_init(isa_bus);
1286         vmmouse = isa_try_create(isa_bus, "vmmouse");
1287     } else {
1288         vmmouse = NULL;
1289     }
1290     if (vmmouse) {
1291         DeviceState *dev = DEVICE(vmmouse);
1292         qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1293         qdev_init_nofail(dev);
1294     }
1295     port92 = isa_create_simple(isa_bus, "port92");
1296     port92_init(port92, &a20_line[1]);
1297
1298     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1299     DMA_init(0, cpu_exit_irq);
1300
1301     for(i = 0; i < MAX_FD; i++) {
1302         fd[i] = drive_get(IF_FLOPPY, 0, i);
1303     }
1304     *floppy = fdctrl_init_isa(isa_bus, fd);
1305 }
1306
1307 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1308 {
1309     int i;
1310
1311     for (i = 0; i < nb_nics; i++) {
1312         NICInfo *nd = &nd_table[i];
1313
1314         if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1315             pc_init_ne2k_isa(isa_bus, nd);
1316         } else {
1317             pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1318         }
1319     }
1320 }
1321
1322 void pc_pci_device_init(PCIBus *pci_bus)
1323 {
1324     int max_bus;
1325     int bus;
1326
1327     max_bus = drive_get_max_bus(IF_SCSI);
1328     for (bus = 0; bus <= max_bus; bus++) {
1329         pci_create_simple(pci_bus, -1, "lsi53c895a");
1330     }
1331 }
1332
1333 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1334 {
1335     DeviceState *dev;
1336     SysBusDevice *d;
1337     unsigned int i;
1338
1339     if (kvm_irqchip_in_kernel()) {
1340         dev = qdev_create(NULL, "kvm-ioapic");
1341     } else {
1342         dev = qdev_create(NULL, "ioapic");
1343     }
1344     if (parent_name) {
1345         object_property_add_child(object_resolve_path(parent_name, NULL),
1346                                   "ioapic", OBJECT(dev), NULL);
1347     }
1348     qdev_init_nofail(dev);
1349     d = SYS_BUS_DEVICE(dev);
1350     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1351
1352     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1353         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1354     }
1355 }