hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/pc.h"
  26 #include "hw/serial.h"
  27 #include "hw/apic.h"
  28 #include "hw/fdc.h"
  29 #include "hw/ide.h"
  30 #include "hw/pci/pci.h"
  31 #include "monitor/monitor.h"
  32 #include "hw/fw_cfg.h"
  33 #include "hw/hpet_emul.h"
  34 #include "hw/smbios.h"
  35 #include "hw/loader.h"
  36 #include "elf.h"
  37 #include "hw/multiboot.h"
  38 #include "hw/mc146818rtc.h"
  39 #include "hw/i8254.h"
  40 #include "hw/pcspk.h"
  41 #include "hw/pci/msi.h"
  42 #include "hw/sysbus.h"
  43 #include "sysemu/sysemu.h"
  44 #include "sysemu/kvm.h"
  45 #include "kvm_i386.h"
  46 #include "hw/xen.h"
  47 #include "sysemu/blockdev.h"
  48 #include "hw/block-common.h"
  49 #include "ui/qemu-spice.h"
  50 #include "exec/memory.h"
  51 #include "exec/address-spaces.h"
  52 #include "sysemu/arch_init.h"
  53 #include "qemu/bitmap.h"
  54
  55 /* debug PC/ISA interrupts */
  56 //#define DEBUG_IRQ
  57
  58 #ifdef DEBUG_IRQ
  59 #define DPRINTF(fmt, ...)                                       \
  60     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  61 #else
  62 #define DPRINTF(fmt, ...)
  63 #endif
  64
  65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  66 #define ACPI_DATA_SIZE       0x10000
  67 #define BIOS_CFG_IOPORT 0x510
  68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  73
  74 #define E820_NR_ENTRIES         16
  75
  76 struct e820_entry {
  77     uint64_t address;
  78     uint64_t length;
  79     uint32_t type;
  80 } QEMU_PACKED __attribute((__aligned__(4)));
  81
  82 struct e820_table {
  83     uint32_t count;
  84     struct e820_entry entry[E820_NR_ENTRIES];
  85 } QEMU_PACKED __attribute((__aligned__(4)));
  86
  87 static struct e820_table e820_table;
  88 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  89
  90 void gsi_handler(void *opaque, int n, int level)
  91 {
  92     GSIState *s = opaque;
  93
  94     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  95     if (n < ISA_NUM_IRQS) {
  96         qemu_set_irq(s->i8259_irq[n], level);
  97     }
  98     qemu_set_irq(s->ioapic_irq[n], level);
  99 }
 100
 101 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 102                            unsigned size)
 103 {
 104 }
 105
 106 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 107 {
 108     return 0xffffffffffffffffULL;
 109 }
 110
 111 /* MSDOS compatibility mode FPU exception support */
 112 static qemu_irq ferr_irq;
 113
 114 void pc_register_ferr_irq(qemu_irq irq)
 115 {
 116     ferr_irq = irq;
 117 }
 118
 119 /* XXX: add IGNNE support */
 120 void cpu_set_ferr(CPUX86State *s)
 121 {
 122     qemu_irq_raise(ferr_irq);
 123 }
 124
 125 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 126                            unsigned size)
 127 {
 128     qemu_irq_lower(ferr_irq);
 129 }
 130
 131 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 132 {
 133     return 0xffffffffffffffffULL;
 134 }
 135
 136 /* TSC handling */
 137 uint64_t cpu_get_tsc(CPUX86State *env)
 138 {
 139     return cpu_get_ticks();
 140 }
 141
 142 /* SMM support */
 143
 144 static cpu_set_smm_t smm_set;
 145 static void *smm_arg;
 146
 147 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 148 {
 149     assert(smm_set == NULL);
 150     assert(smm_arg == NULL);
 151     smm_set = callback;
 152     smm_arg = arg;
 153 }
 154
 155 void cpu_smm_update(CPUX86State *env)
 156 {
 157     if (smm_set && smm_arg && env == first_cpu)
 158         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 159 }
 160
 161
 162 /* IRQ handling */
 163 int cpu_get_pic_interrupt(CPUX86State *env)
 164 {
 165     int intno;
 166
 167     intno = apic_get_interrupt(env->apic_state);
 168     if (intno >= 0) {
 169         return intno;
 170     }
 171     /* read the irq from the PIC */
 172     if (!apic_accept_pic_intr(env->apic_state)) {
 173         return -1;
 174     }
 175
 176     intno = pic_read_irq(isa_pic);
 177     return intno;
 178 }
 179
 180 static void pic_irq_request(void *opaque, int irq, int level)
 181 {
 182     CPUX86State *env = first_cpu;
 183
 184     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 185     if (env->apic_state) {
 186         while (env) {
 187             if (apic_accept_pic_intr(env->apic_state)) {
 188                 apic_deliver_pic_intr(env->apic_state, level);
 189             }
 190             env = env->next_cpu;
 191         }
 192     } else {
 193         CPUState *cs = CPU(x86_env_get_cpu(env));
 194         if (level) {
 195             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 196         } else {
 197             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 198         }
 199     }
 200 }
 201
 202 /* PC cmos mappings */
 203
 204 #define REG_EQUIPMENT_BYTE          0x14
 205
 206 static int cmos_get_fd_drive_type(FDriveType fd0)
 207 {
 208     int val;
 209
 210     switch (fd0) {
 211     case FDRIVE_DRV_144:
 212         /* 1.44 Mb 3"5 drive */
 213         val = 4;
 214         break;
 215     case FDRIVE_DRV_288:
 216         /* 2.88 Mb 3"5 drive */
 217         val = 5;
 218         break;
 219     case FDRIVE_DRV_120:
 220         /* 1.2 Mb 5"5 drive */
 221         val = 2;
 222         break;
 223     case FDRIVE_DRV_NONE:
 224     default:
 225         val = 0;
 226         break;
 227     }
 228     return val;
 229 }
 230
 231 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 232                          int16_t cylinders, int8_t heads, int8_t sectors)
 233 {
 234     rtc_set_memory(s, type_ofs, 47);
 235     rtc_set_memory(s, info_ofs, cylinders);
 236     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 237     rtc_set_memory(s, info_ofs + 2, heads);
 238     rtc_set_memory(s, info_ofs + 3, 0xff);
 239     rtc_set_memory(s, info_ofs + 4, 0xff);
 240     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 241     rtc_set_memory(s, info_ofs + 6, cylinders);
 242     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 243     rtc_set_memory(s, info_ofs + 8, sectors);
 244 }
 245
 246 /* convert boot_device letter to something recognizable by the bios */
 247 static int boot_device2nibble(char boot_device)
 248 {
 249     switch(boot_device) {
 250     case 'a':
 251     case 'b':
 252         return 0x01; /* floppy boot */
 253     case 'c':
 254         return 0x02; /* hard drive boot */
 255     case 'd':
 256         return 0x03; /* CD-ROM boot */
 257     case 'n':
 258         return 0x04; /* Network boot */
 259     }
 260     return 0;
 261 }
 262
 263 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 264 {
 265 #define PC_MAX_BOOT_DEVICES 3
 266     int nbds, bds[3] = { 0, };
 267     int i;
 268
 269     nbds = strlen(boot_device);
 270     if (nbds > PC_MAX_BOOT_DEVICES) {
 271         error_report("Too many boot devices for PC");
 272         return(1);
 273     }
 274     for (i = 0; i < nbds; i++) {
 275         bds[i] = boot_device2nibble(boot_device[i]);
 276         if (bds[i] == 0) {
 277             error_report("Invalid boot device for PC: '%c'",
 278                          boot_device[i]);
 279             return(1);
 280         }
 281     }
 282     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 283     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 284     return(0);
 285 }
 286
 287 static int pc_boot_set(void *opaque, const char *boot_device)
 288 {
 289     return set_boot_dev(opaque, boot_device, 0);
 290 }
 291
 292 typedef struct pc_cmos_init_late_arg {
 293     ISADevice *rtc_state;
 294     BusState *idebus[2];
 295 } pc_cmos_init_late_arg;
 296
 297 static void pc_cmos_init_late(void *opaque)
 298 {
 299     pc_cmos_init_late_arg *arg = opaque;
 300     ISADevice *s = arg->rtc_state;
 301     int16_t cylinders;
 302     int8_t heads, sectors;
 303     int val;
 304     int i, trans;
 305
 306     val = 0;
 307     if (ide_get_geometry(arg->idebus[0], 0,
 308                          &cylinders, &heads, &sectors) >= 0) {
 309         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 310         val |= 0xf0;
 311     }
 312     if (ide_get_geometry(arg->idebus[0], 1,
 313                          &cylinders, &heads, &sectors) >= 0) {
 314         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 315         val |= 0x0f;
 316     }
 317     rtc_set_memory(s, 0x12, val);
 318
 319     val = 0;
 320     for (i = 0; i < 4; i++) {
 321         /* NOTE: ide_get_geometry() returns the physical
 322            geometry.  It is always such that: 1 <= sects <= 63, 1
 323            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 324            geometry can be different if a translation is done. */
 325         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 326                              &cylinders, &heads, &sectors) >= 0) {
 327             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 328             assert((trans & ~3) == 0);
 329             val |= trans << (i * 2);
 330         }
 331     }
 332     rtc_set_memory(s, 0x39, val);
 333
 334     qemu_unregister_reset(pc_cmos_init_late, opaque);
 335 }
 336
 337 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 338                   const char *boot_device,
 339                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 340                   ISADevice *s)
 341 {
 342     int val, nb, i;
 343     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 344     static pc_cmos_init_late_arg arg;
 345
 346     /* various important CMOS locations needed by PC/Bochs bios */
 347
 348     /* memory size */
 349     /* base memory (first MiB) */
 350     val = MIN(ram_size / 1024, 640);
 351     rtc_set_memory(s, 0x15, val);
 352     rtc_set_memory(s, 0x16, val >> 8);
 353     /* extended memory (next 64MiB) */
 354     if (ram_size > 1024 * 1024) {
 355         val = (ram_size - 1024 * 1024) / 1024;
 356     } else {
 357         val = 0;
 358     }
 359     if (val > 65535)
 360         val = 65535;
 361     rtc_set_memory(s, 0x17, val);
 362     rtc_set_memory(s, 0x18, val >> 8);
 363     rtc_set_memory(s, 0x30, val);
 364     rtc_set_memory(s, 0x31, val >> 8);
 365     /* memory between 16MiB and 4GiB */
 366     if (ram_size > 16 * 1024 * 1024) {
 367         val = (ram_size - 16 * 1024 * 1024) / 65536;
 368     } else {
 369         val = 0;
 370     }
 371     if (val > 65535)
 372         val = 65535;
 373     rtc_set_memory(s, 0x34, val);
 374     rtc_set_memory(s, 0x35, val >> 8);
 375     /* memory above 4GiB */
 376     val = above_4g_mem_size / 65536;
 377     rtc_set_memory(s, 0x5b, val);
 378     rtc_set_memory(s, 0x5c, val >> 8);
 379     rtc_set_memory(s, 0x5d, val >> 16);
 380
 381     /* set the number of CPU */
 382     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 383
 384     /* set boot devices, and disable floppy signature check if requested */
 385     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 386         exit(1);
 387     }
 388
 389     /* floppy type */
 390     if (floppy) {
 391         for (i = 0; i < 2; i++) {
 392             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 393         }
 394     }
 395     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 396         cmos_get_fd_drive_type(fd_type[1]);
 397     rtc_set_memory(s, 0x10, val);
 398
 399     val = 0;
 400     nb = 0;
 401     if (fd_type[0] < FDRIVE_DRV_NONE) {
 402         nb++;
 403     }
 404     if (fd_type[1] < FDRIVE_DRV_NONE) {
 405         nb++;
 406     }
 407     switch (nb) {
 408     case 0:
 409         break;
 410     case 1:
 411         val |= 0x01; /* 1 drive, ready for boot */
 412         break;
 413     case 2:
 414         val |= 0x41; /* 2 drives, ready for boot */
 415         break;
 416     }
 417     val |= 0x02; /* FPU is there */
 418     val |= 0x04; /* PS/2 mouse installed */
 419     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 420
 421     /* hard drives */
 422     arg.rtc_state = s;
 423     arg.idebus[0] = idebus0;
 424     arg.idebus[1] = idebus1;
 425     qemu_register_reset(pc_cmos_init_late, &arg);
 426 }
 427
 428 /* port 92 stuff: could be split off */
 429 typedef struct Port92State {
 430     ISADevice dev;
 431     MemoryRegion io;
 432     uint8_t outport;
 433     qemu_irq *a20_out;
 434 } Port92State;
 435
 436 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 437                          unsigned size)
 438 {
 439     Port92State *s = opaque;
 440
 441     DPRINTF("port92: write 0x%02x\n", val);
 442     s->outport = val;
 443     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 444     if (val & 1) {
 445         qemu_system_reset_request();
 446     }
 447 }
 448
 449 static uint64_t port92_read(void *opaque, hwaddr addr,
 450                             unsigned size)
 451 {
 452     Port92State *s = opaque;
 453     uint32_t ret;
 454
 455     ret = s->outport;
 456     DPRINTF("port92: read 0x%02x\n", ret);
 457     return ret;
 458 }
 459
 460 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 461 {
 462     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 463
 464     s->a20_out = a20_out;
 465 }
 466
 467 static const VMStateDescription vmstate_port92_isa = {
 468     .name = "port92",
 469     .version_id = 1,
 470     .minimum_version_id = 1,
 471     .minimum_version_id_old = 1,
 472     .fields      = (VMStateField []) {
 473         VMSTATE_UINT8(outport, Port92State),
 474         VMSTATE_END_OF_LIST()
 475     }
 476 };
 477
 478 static void port92_reset(DeviceState *d)
 479 {
 480     Port92State *s = container_of(d, Port92State, dev.qdev);
 481
 482     s->outport &= ~1;
 483 }
 484
 485 static const MemoryRegionOps port92_ops = {
 486     .read = port92_read,
 487     .write = port92_write,
 488     .impl = {
 489         .min_access_size = 1,
 490         .max_access_size = 1,
 491     },
 492     .endianness = DEVICE_LITTLE_ENDIAN,
 493 };
 494
 495 static int port92_initfn(ISADevice *dev)
 496 {
 497     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 498
 499     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 500     isa_register_ioport(dev, &s->io, 0x92);
 501
 502     s->outport = 0;
 503     return 0;
 504 }
 505
 506 static void port92_class_initfn(ObjectClass *klass, void *data)
 507 {
 508     DeviceClass *dc = DEVICE_CLASS(klass);
 509     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 510     ic->init = port92_initfn;
 511     dc->no_user = 1;
 512     dc->reset = port92_reset;
 513     dc->vmsd = &vmstate_port92_isa;
 514 }
 515
 516 static const TypeInfo port92_info = {
 517     .name          = "port92",
 518     .parent        = TYPE_ISA_DEVICE,
 519     .instance_size = sizeof(Port92State),
 520     .class_init    = port92_class_initfn,
 521 };
 522
 523 static void port92_register_types(void)
 524 {
 525     type_register_static(&port92_info);
 526 }
 527
 528 type_init(port92_register_types)
 529
 530 static void handle_a20_line_change(void *opaque, int irq, int level)
 531 {
 532     X86CPU *cpu = opaque;
 533
 534     /* XXX: send to all CPUs ? */
 535     /* XXX: add logic to handle multiple A20 line sources */
 536     x86_cpu_set_a20(cpu, level);
 537 }
 538
 539 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 540 {
 541     int index = le32_to_cpu(e820_table.count);
 542     struct e820_entry *entry;
 543
 544     if (index >= E820_NR_ENTRIES)
 545         return -EBUSY;
 546     entry = &e820_table.entry[index++];
 547
 548     entry->address = cpu_to_le64(address);
 549     entry->length = cpu_to_le64(length);
 550     entry->type = cpu_to_le32(type);
 551
 552     e820_table.count = cpu_to_le32(index);
 553     return index;
 554 }
 555
 556 /* Calculates the limit to CPU APIC ID values
 557  *
 558  * This function returns the limit for the APIC ID value, so that all
 559  * CPU APIC IDs are < pc_apic_id_limit().
 560  *
 561  * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
 562  */
 563 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
 564 {
 565     return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
 566 }
 567
 568 static void *bochs_bios_init(void)
 569 {
 570     void *fw_cfg;
 571     uint8_t *smbios_table;
 572     size_t smbios_len;
 573     uint64_t *numa_fw_cfg;
 574     int i, j;
 575     unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
 576
 577     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 578     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 579      *
 580      * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
 581      * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
 582      * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
 583      * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
 584      * may see".
 585      *
 586      * So, this means we must not use max_cpus, here, but the maximum possible
 587      * APIC ID value, plus one.
 588      *
 589      * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
 590      *     the APIC ID, not the "CPU index"
 591      */
 592     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
 593     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 594     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 595     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 596                      acpi_tables, acpi_tables_len);
 597     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 598
 599     smbios_table = smbios_get_table(&smbios_len);
 600     if (smbios_table)
 601         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 602                          smbios_table, smbios_len);
 603     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 604                      &e820_table, sizeof(e820_table));
 605
 606     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 607     /* allocate memory for the NUMA channel: one (64bit) word for the number
 608      * of nodes, one word for each VCPU->node and one word for each node to
 609      * hold the amount of memory.
 610      */
 611     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 612     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 613     for (i = 0; i < max_cpus; i++) {
 614         unsigned int apic_id = x86_cpu_apic_id_from_index(i);
 615         assert(apic_id < apic_id_limit);
 616         for (j = 0; j < nb_numa_nodes; j++) {
 617             if (test_bit(i, node_cpumask[j])) {
 618                 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
 619                 break;
 620             }
 621         }
 622     }
 623     for (i = 0; i < nb_numa_nodes; i++) {
 624         numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
 625     }
 626     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 627                      (1 + apic_id_limit + nb_numa_nodes) *
 628                      sizeof(*numa_fw_cfg));
 629
 630     return fw_cfg;
 631 }
 632
 633 static long get_file_size(FILE *f)
 634 {
 635     long where, size;
 636
 637     /* XXX: on Unix systems, using fstat() probably makes more sense */
 638
 639     where = ftell(f);
 640     fseek(f, 0, SEEK_END);
 641     size = ftell(f);
 642     fseek(f, where, SEEK_SET);
 643
 644     return size;
 645 }
 646
 647 static void load_linux(void *fw_cfg,
 648                        const char *kernel_filename,
 649                        const char *initrd_filename,
 650                        const char *kernel_cmdline,
 651                        hwaddr max_ram_size)
 652 {
 653     uint16_t protocol;
 654     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 655     uint32_t initrd_max;
 656     uint8_t header[8192], *setup, *kernel, *initrd_data;
 657     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 658     FILE *f;
 659     char *vmode;
 660
 661     /* Align to 16 bytes as a paranoia measure */
 662     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 663
 664     /* load the kernel header */
 665     f = fopen(kernel_filename, "rb");
 666     if (!f || !(kernel_size = get_file_size(f)) ||
 667         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 668         MIN(ARRAY_SIZE(header), kernel_size)) {
 669         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 670                 kernel_filename, strerror(errno));
 671         exit(1);
 672     }
 673
 674     /* kernel protocol version */
 675 #if 0
 676     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 677 #endif
 678     if (ldl_p(header+0x202) == 0x53726448)
 679         protocol = lduw_p(header+0x206);
 680     else {
 681         /* This looks like a multiboot kernel. If it is, let's stop
 682            treating it like a Linux kernel. */
 683         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 684                            kernel_cmdline, kernel_size, header))
 685             return;
 686         protocol = 0;
 687     }
 688
 689     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 690         /* Low kernel */
 691         real_addr    = 0x90000;
 692         cmdline_addr = 0x9a000 - cmdline_size;
 693         prot_addr    = 0x10000;
 694     } else if (protocol < 0x202) {
 695         /* High but ancient kernel */
 696         real_addr    = 0x90000;
 697         cmdline_addr = 0x9a000 - cmdline_size;
 698         prot_addr    = 0x100000;
 699     } else {
 700         /* High and recent kernel */
 701         real_addr    = 0x10000;
 702         cmdline_addr = 0x20000;
 703         prot_addr    = 0x100000;
 704     }
 705
 706 #if 0
 707     fprintf(stderr,
 708             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 709             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 710             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 711             real_addr,
 712             cmdline_addr,
 713             prot_addr);
 714 #endif
 715
 716     /* highest address for loading the initrd */
 717     if (protocol >= 0x203)
 718         initrd_max = ldl_p(header+0x22c);
 719     else
 720         initrd_max = 0x37ffffff;
 721
 722     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 723         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 724
 725     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 726     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 727     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 728
 729     if (protocol >= 0x202) {
 730         stl_p(header+0x228, cmdline_addr);
 731     } else {
 732         stw_p(header+0x20, 0xA33F);
 733         stw_p(header+0x22, cmdline_addr-real_addr);
 734     }
 735
 736     /* handle vga= parameter */
 737     vmode = strstr(kernel_cmdline, "vga=");
 738     if (vmode) {
 739         unsigned int video_mode;
 740         /* skip "vga=" */
 741         vmode += 4;
 742         if (!strncmp(vmode, "normal", 6)) {
 743             video_mode = 0xffff;
 744         } else if (!strncmp(vmode, "ext", 3)) {
 745             video_mode = 0xfffe;
 746         } else if (!strncmp(vmode, "ask", 3)) {
 747             video_mode = 0xfffd;
 748         } else {
 749             video_mode = strtol(vmode, NULL, 0);
 750         }
 751         stw_p(header+0x1fa, video_mode);
 752     }
 753
 754     /* loader type */
 755     /* High nybble = B reserved for QEMU; low nybble is revision number.
 756        If this code is substantially changed, you may want to consider
 757        incrementing the revision. */
 758     if (protocol >= 0x200)
 759         header[0x210] = 0xB0;
 760
 761     /* heap */
 762     if (protocol >= 0x201) {
 763         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 764         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 765     }
 766
 767     /* load initrd */
 768     if (initrd_filename) {
 769         if (protocol < 0x200) {
 770             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 771             exit(1);
 772         }
 773
 774         initrd_size = get_image_size(initrd_filename);
 775         if (initrd_size < 0) {
 776             fprintf(stderr, "qemu: error reading initrd %s\n",
 777                     initrd_filename);
 778             exit(1);
 779         }
 780
 781         initrd_addr = (initrd_max-initrd_size) & ~4095;
 782
 783         initrd_data = g_malloc(initrd_size);
 784         load_image(initrd_filename, initrd_data);
 785
 786         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 787         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 788         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 789
 790         stl_p(header+0x218, initrd_addr);
 791         stl_p(header+0x21c, initrd_size);
 792     }
 793
 794     /* load kernel and setup */
 795     setup_size = header[0x1f1];
 796     if (setup_size == 0)
 797         setup_size = 4;
 798     setup_size = (setup_size+1)*512;
 799     kernel_size -= setup_size;
 800
 801     setup  = g_malloc(setup_size);
 802     kernel = g_malloc(kernel_size);
 803     fseek(f, 0, SEEK_SET);
 804     if (fread(setup, 1, setup_size, f) != setup_size) {
 805         fprintf(stderr, "fread() failed\n");
 806         exit(1);
 807     }
 808     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 809         fprintf(stderr, "fread() failed\n");
 810         exit(1);
 811     }
 812     fclose(f);
 813     memcpy(setup, header, MIN(sizeof(header), setup_size));
 814
 815     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 816     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 817     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 818
 819     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 820     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 821     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 822
 823     option_rom[nb_option_roms].name = "linuxboot.bin";
 824     option_rom[nb_option_roms].bootindex = 0;
 825     nb_option_roms++;
 826 }
 827
 828 #define NE2000_NB_MAX 6
 829
 830 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 831                                               0x280, 0x380 };
 832 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 833
 834 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 835 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 836
 837 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 838 {
 839     static int nb_ne2k = 0;
 840
 841     if (nb_ne2k == NE2000_NB_MAX)
 842         return;
 843     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 844                     ne2000_irq[nb_ne2k], nd);
 845     nb_ne2k++;
 846 }
 847
 848 DeviceState *cpu_get_current_apic(void)
 849 {
 850     if (cpu_single_env) {
 851         return cpu_single_env->apic_state;
 852     } else {
 853         return NULL;
 854     }
 855 }
 856
 857 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 858 {
 859     CPUX86State *s = opaque;
 860
 861     if (level) {
 862         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 863     }
 864 }
 865
 866 void pc_cpus_init(const char *cpu_model)
 867 {
 868     int i;
 869
 870     /* init CPUs */
 871     if (cpu_model == NULL) {
 872 #ifdef TARGET_X86_64
 873         cpu_model = "qemu64";
 874 #else
 875         cpu_model = "qemu32";
 876 #endif
 877     }
 878
 879     for (i = 0; i < smp_cpus; i++) {
 880         if (!cpu_x86_init(cpu_model)) {
 881             exit(1);
 882         }
 883     }
 884 }
 885
 886 void pc_acpi_init(const char *default_dsdt)
 887 {
 888     char *filename = NULL, *arg = NULL;
 889
 890     if (acpi_tables != NULL) {
 891         /* manually set via -acpitable, leave it alone */
 892         return;
 893     }
 894
 895     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
 896     if (filename == NULL) {
 897         fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
 898         return;
 899     }
 900
 901     arg = g_strdup_printf("file=%s", filename);
 902     if (acpi_table_add(arg) != 0) {
 903         fprintf(stderr, "WARNING: failed to load %s\n", filename);
 904     }
 905     g_free(arg);
 906     g_free(filename);
 907 }
 908
 909 void *pc_memory_init(MemoryRegion *system_memory,
 910                     const char *kernel_filename,
 911                     const char *kernel_cmdline,
 912                     const char *initrd_filename,
 913                     ram_addr_t below_4g_mem_size,
 914                     ram_addr_t above_4g_mem_size,
 915                     MemoryRegion *rom_memory,
 916                     MemoryRegion **ram_memory)
 917 {
 918     int linux_boot, i;
 919     MemoryRegion *ram, *option_rom_mr;
 920     MemoryRegion *ram_below_4g, *ram_above_4g;
 921     void *fw_cfg;
 922
 923     linux_boot = (kernel_filename != NULL);
 924
 925     /* Allocate RAM.  We allocate it as a single memory region and use
 926      * aliases to address portions of it, mostly for backwards compatibility
 927      * with older qemus that used qemu_ram_alloc().
 928      */
 929     ram = g_malloc(sizeof(*ram));
 930     memory_region_init_ram(ram, "pc.ram",
 931                            below_4g_mem_size + above_4g_mem_size);
 932     vmstate_register_ram_global(ram);
 933     *ram_memory = ram;
 934     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 935     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 936                              0, below_4g_mem_size);
 937     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 938     if (above_4g_mem_size > 0) {
 939         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
 940         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
 941                                  below_4g_mem_size, above_4g_mem_size);
 942         memory_region_add_subregion(system_memory, 0x100000000ULL,
 943                                     ram_above_4g);
 944     }
 945
 946
 947     /* Initialize PC system firmware */
 948     pc_system_firmware_init(rom_memory);
 949
 950     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
 951     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
 952     vmstate_register_ram_global(option_rom_mr);
 953     memory_region_add_subregion_overlap(rom_memory,
 954                                         PC_ROM_MIN_VGA,
 955                                         option_rom_mr,
 956                                         1);
 957
 958     fw_cfg = bochs_bios_init();
 959     rom_set_fw(fw_cfg);
 960
 961     if (linux_boot) {
 962         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 963     }
 964
 965     for (i = 0; i < nb_option_roms; i++) {
 966         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
 967     }
 968     return fw_cfg;
 969 }
 970
 971 qemu_irq *pc_allocate_cpu_irq(void)
 972 {
 973     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 974 }
 975
 976 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
 977 {
 978     DeviceState *dev = NULL;
 979
 980     if (pci_bus) {
 981         PCIDevice *pcidev = pci_vga_init(pci_bus);
 982         dev = pcidev ? &pcidev->qdev : NULL;
 983     } else if (isa_bus) {
 984         ISADevice *isadev = isa_vga_init(isa_bus);
 985         dev = isadev ? &isadev->qdev : NULL;
 986     }
 987     return dev;
 988 }
 989
 990 static void cpu_request_exit(void *opaque, int irq, int level)
 991 {
 992     CPUX86State *env = cpu_single_env;
 993
 994     if (env && level) {
 995         cpu_exit(env);
 996     }
 997 }
 998
 999 static const MemoryRegionOps ioport80_io_ops = {
1000     .write = ioport80_write,
1001     .read = ioport80_read,
1002     .endianness = DEVICE_NATIVE_ENDIAN,
1003     .impl = {
1004         .min_access_size = 1,
1005         .max_access_size = 1,
1006     },
1007 };
1008
1009 static const MemoryRegionOps ioportF0_io_ops = {
1010     .write = ioportF0_write,
1011     .read = ioportF0_read,
1012     .endianness = DEVICE_NATIVE_ENDIAN,
1013     .impl = {
1014         .min_access_size = 1,
1015         .max_access_size = 1,
1016     },
1017 };
1018
1019 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1020                           ISADevice **rtc_state,
1021                           ISADevice **floppy,
1022                           bool no_vmport)
1023 {
1024     int i;
1025     DriveInfo *fd[MAX_FD];
1026     DeviceState *hpet = NULL;
1027     int pit_isa_irq = 0;
1028     qemu_irq pit_alt_irq = NULL;
1029     qemu_irq rtc_irq = NULL;
1030     qemu_irq *a20_line;
1031     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1032     qemu_irq *cpu_exit_irq;
1033     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1034     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1035
1036     memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1);
1037     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1038
1039     memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1);
1040     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1041
1042     /*
1043      * Check if an HPET shall be created.
1044      *
1045      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1046      * when the HPET wants to take over. Thus we have to disable the latter.
1047      */
1048     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1049         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1050
1051         if (hpet) {
1052             for (i = 0; i < GSI_NUM_PINS; i++) {
1053                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1054             }
1055             pit_isa_irq = -1;
1056             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1057             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1058         }
1059     }
1060     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1061
1062     qemu_register_boot_set(pc_boot_set, *rtc_state);
1063
1064     if (!xen_enabled()) {
1065         if (kvm_irqchip_in_kernel()) {
1066             pit = kvm_pit_init(isa_bus, 0x40);
1067         } else {
1068             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1069         }
1070         if (hpet) {
1071             /* connect PIT to output control line of the HPET */
1072             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1073         }
1074         pcspk_init(isa_bus, pit);
1075     }
1076
1077     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1078         if (serial_hds[i]) {
1079             serial_isa_init(isa_bus, i, serial_hds[i]);
1080         }
1081     }
1082
1083     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1084         if (parallel_hds[i]) {
1085             parallel_init(isa_bus, i, parallel_hds[i]);
1086         }
1087     }
1088
1089     a20_line = qemu_allocate_irqs(handle_a20_line_change,
1090                                   x86_env_get_cpu(first_cpu), 2);
1091     i8042 = isa_create_simple(isa_bus, "i8042");
1092     i8042_setup_a20_line(i8042, &a20_line[0]);
1093     if (!no_vmport) {
1094         vmport_init(isa_bus);
1095         vmmouse = isa_try_create(isa_bus, "vmmouse");
1096     } else {
1097         vmmouse = NULL;
1098     }
1099     if (vmmouse) {
1100         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1101         qdev_init_nofail(&vmmouse->qdev);
1102     }
1103     port92 = isa_create_simple(isa_bus, "port92");
1104     port92_init(port92, &a20_line[1]);
1105
1106     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1107     DMA_init(0, cpu_exit_irq);
1108
1109     for(i = 0; i < MAX_FD; i++) {
1110         fd[i] = drive_get(IF_FLOPPY, 0, i);
1111     }
1112     *floppy = fdctrl_init_isa(isa_bus, fd);
1113 }
1114
1115 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1116 {
1117     int i;
1118
1119     for (i = 0; i < nb_nics; i++) {
1120         NICInfo *nd = &nd_table[i];
1121
1122         if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1123             pc_init_ne2k_isa(isa_bus, nd);
1124         } else {
1125             pci_nic_init_nofail(nd, "e1000", NULL);
1126         }
1127     }
1128 }
1129
1130 void pc_pci_device_init(PCIBus *pci_bus)
1131 {
1132     int max_bus;
1133     int bus;
1134
1135     max_bus = drive_get_max_bus(IF_SCSI);
1136     for (bus = 0; bus <= max_bus; bus++) {
1137         pci_create_simple(pci_bus, -1, "lsi53c895a");
1138     }
1139 }
1140
1141 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1142 {
1143     DeviceState *dev;
1144     SysBusDevice *d;
1145     unsigned int i;
1146
1147     if (kvm_irqchip_in_kernel()) {
1148         dev = qdev_create(NULL, "kvm-ioapic");
1149     } else {
1150         dev = qdev_create(NULL, "ioapic");
1151     }
1152     if (parent_name) {
1153         object_property_add_child(object_resolve_path(parent_name, NULL),
1154                                   "ioapic", OBJECT(dev), NULL);
1155     }
1156     qdev_init_nofail(dev);
1157     d = SYS_BUS_DEVICE(dev);
1158     sysbus_mmio_map(d, 0, 0xfec00000);
1159
1160     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1161         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1162     }
1163 }