hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/pc.h"
  26 #include "hw/serial.h"
  27 #include "hw/apic.h"
  28 #include "hw/fdc.h"
  29 #include "hw/ide.h"
  30 #include "hw/pci/pci.h"
  31 #include "monitor/monitor.h"
  32 #include "hw/fw_cfg.h"
  33 #include "hw/hpet_emul.h"
  34 #include "hw/smbios.h"
  35 #include "hw/loader.h"
  36 #include "elf.h"
  37 #include "hw/multiboot.h"
  38 #include "hw/mc146818rtc.h"
  39 #include "hw/i8254.h"
  40 #include "hw/pcspk.h"
  41 #include "hw/pci/msi.h"
  42 #include "hw/sysbus.h"
  43 #include "sysemu/sysemu.h"
  44 #include "sysemu/kvm.h"
  45 #include "kvm_i386.h"
  46 #include "hw/xen.h"
  47 #include "sysemu/blockdev.h"
  48 #include "hw/block-common.h"
  49 #include "ui/qemu-spice.h"
  50 #include "exec/memory.h"
  51 #include "exec/address-spaces.h"
  52 #include "sysemu/arch_init.h"
  53 #include "qemu/bitmap.h"
  54 #include "qemu/config-file.h"
  55
  56 /* debug PC/ISA interrupts */
  57 //#define DEBUG_IRQ
  58
  59 #ifdef DEBUG_IRQ
  60 #define DPRINTF(fmt, ...)                                       \
  61     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  62 #else
  63 #define DPRINTF(fmt, ...)
  64 #endif
  65
  66 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  67 #define ACPI_DATA_SIZE       0x10000
  68 #define BIOS_CFG_IOPORT 0x510
  69 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  70 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  71 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  72 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  73 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  74
  75 #define E820_NR_ENTRIES         16
  76
  77 struct e820_entry {
  78     uint64_t address;
  79     uint64_t length;
  80     uint32_t type;
  81 } QEMU_PACKED __attribute((__aligned__(4)));
  82
  83 struct e820_table {
  84     uint32_t count;
  85     struct e820_entry entry[E820_NR_ENTRIES];
  86 } QEMU_PACKED __attribute((__aligned__(4)));
  87
  88 static struct e820_table e820_table;
  89 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  90
  91 void gsi_handler(void *opaque, int n, int level)
  92 {
  93     GSIState *s = opaque;
  94
  95     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  96     if (n < ISA_NUM_IRQS) {
  97         qemu_set_irq(s->i8259_irq[n], level);
  98     }
  99     qemu_set_irq(s->ioapic_irq[n], level);
 100 }
 101
 102 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 103                            unsigned size)
 104 {
 105 }
 106
 107 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 108 {
 109     return 0xffffffffffffffffULL;
 110 }
 111
 112 /* MSDOS compatibility mode FPU exception support */
 113 static qemu_irq ferr_irq;
 114
 115 void pc_register_ferr_irq(qemu_irq irq)
 116 {
 117     ferr_irq = irq;
 118 }
 119
 120 /* XXX: add IGNNE support */
 121 void cpu_set_ferr(CPUX86State *s)
 122 {
 123     qemu_irq_raise(ferr_irq);
 124 }
 125
 126 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 127                            unsigned size)
 128 {
 129     qemu_irq_lower(ferr_irq);
 130 }
 131
 132 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 133 {
 134     return 0xffffffffffffffffULL;
 135 }
 136
 137 /* TSC handling */
 138 uint64_t cpu_get_tsc(CPUX86State *env)
 139 {
 140     return cpu_get_ticks();
 141 }
 142
 143 /* SMM support */
 144
 145 static cpu_set_smm_t smm_set;
 146 static void *smm_arg;
 147
 148 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 149 {
 150     assert(smm_set == NULL);
 151     assert(smm_arg == NULL);
 152     smm_set = callback;
 153     smm_arg = arg;
 154 }
 155
 156 void cpu_smm_update(CPUX86State *env)
 157 {
 158     if (smm_set && smm_arg && env == first_cpu)
 159         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 160 }
 161
 162
 163 /* IRQ handling */
 164 int cpu_get_pic_interrupt(CPUX86State *env)
 165 {
 166     int intno;
 167
 168     intno = apic_get_interrupt(env->apic_state);
 169     if (intno >= 0) {
 170         return intno;
 171     }
 172     /* read the irq from the PIC */
 173     if (!apic_accept_pic_intr(env->apic_state)) {
 174         return -1;
 175     }
 176
 177     intno = pic_read_irq(isa_pic);
 178     return intno;
 179 }
 180
 181 static void pic_irq_request(void *opaque, int irq, int level)
 182 {
 183     CPUX86State *env = first_cpu;
 184
 185     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 186     if (env->apic_state) {
 187         while (env) {
 188             if (apic_accept_pic_intr(env->apic_state)) {
 189                 apic_deliver_pic_intr(env->apic_state, level);
 190             }
 191             env = env->next_cpu;
 192         }
 193     } else {
 194         CPUState *cs = CPU(x86_env_get_cpu(env));
 195         if (level) {
 196             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 197         } else {
 198             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 199         }
 200     }
 201 }
 202
 203 /* PC cmos mappings */
 204
 205 #define REG_EQUIPMENT_BYTE          0x14
 206
 207 static int cmos_get_fd_drive_type(FDriveType fd0)
 208 {
 209     int val;
 210
 211     switch (fd0) {
 212     case FDRIVE_DRV_144:
 213         /* 1.44 Mb 3"5 drive */
 214         val = 4;
 215         break;
 216     case FDRIVE_DRV_288:
 217         /* 2.88 Mb 3"5 drive */
 218         val = 5;
 219         break;
 220     case FDRIVE_DRV_120:
 221         /* 1.2 Mb 5"5 drive */
 222         val = 2;
 223         break;
 224     case FDRIVE_DRV_NONE:
 225     default:
 226         val = 0;
 227         break;
 228     }
 229     return val;
 230 }
 231
 232 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 233                          int16_t cylinders, int8_t heads, int8_t sectors)
 234 {
 235     rtc_set_memory(s, type_ofs, 47);
 236     rtc_set_memory(s, info_ofs, cylinders);
 237     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 238     rtc_set_memory(s, info_ofs + 2, heads);
 239     rtc_set_memory(s, info_ofs + 3, 0xff);
 240     rtc_set_memory(s, info_ofs + 4, 0xff);
 241     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 242     rtc_set_memory(s, info_ofs + 6, cylinders);
 243     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 244     rtc_set_memory(s, info_ofs + 8, sectors);
 245 }
 246
 247 /* convert boot_device letter to something recognizable by the bios */
 248 static int boot_device2nibble(char boot_device)
 249 {
 250     switch(boot_device) {
 251     case 'a':
 252     case 'b':
 253         return 0x01; /* floppy boot */
 254     case 'c':
 255         return 0x02; /* hard drive boot */
 256     case 'd':
 257         return 0x03; /* CD-ROM boot */
 258     case 'n':
 259         return 0x04; /* Network boot */
 260     }
 261     return 0;
 262 }
 263
 264 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 265 {
 266 #define PC_MAX_BOOT_DEVICES 3
 267     int nbds, bds[3] = { 0, };
 268     int i;
 269
 270     nbds = strlen(boot_device);
 271     if (nbds > PC_MAX_BOOT_DEVICES) {
 272         error_report("Too many boot devices for PC");
 273         return(1);
 274     }
 275     for (i = 0; i < nbds; i++) {
 276         bds[i] = boot_device2nibble(boot_device[i]);
 277         if (bds[i] == 0) {
 278             error_report("Invalid boot device for PC: '%c'",
 279                          boot_device[i]);
 280             return(1);
 281         }
 282     }
 283     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 284     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 285     return(0);
 286 }
 287
 288 static int pc_boot_set(void *opaque, const char *boot_device)
 289 {
 290     return set_boot_dev(opaque, boot_device, 0);
 291 }
 292
 293 typedef struct pc_cmos_init_late_arg {
 294     ISADevice *rtc_state;
 295     BusState *idebus[2];
 296 } pc_cmos_init_late_arg;
 297
 298 static void pc_cmos_init_late(void *opaque)
 299 {
 300     pc_cmos_init_late_arg *arg = opaque;
 301     ISADevice *s = arg->rtc_state;
 302     int16_t cylinders;
 303     int8_t heads, sectors;
 304     int val;
 305     int i, trans;
 306
 307     val = 0;
 308     if (ide_get_geometry(arg->idebus[0], 0,
 309                          &cylinders, &heads, &sectors) >= 0) {
 310         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 311         val |= 0xf0;
 312     }
 313     if (ide_get_geometry(arg->idebus[0], 1,
 314                          &cylinders, &heads, &sectors) >= 0) {
 315         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 316         val |= 0x0f;
 317     }
 318     rtc_set_memory(s, 0x12, val);
 319
 320     val = 0;
 321     for (i = 0; i < 4; i++) {
 322         /* NOTE: ide_get_geometry() returns the physical
 323            geometry.  It is always such that: 1 <= sects <= 63, 1
 324            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 325            geometry can be different if a translation is done. */
 326         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 327                              &cylinders, &heads, &sectors) >= 0) {
 328             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 329             assert((trans & ~3) == 0);
 330             val |= trans << (i * 2);
 331         }
 332     }
 333     rtc_set_memory(s, 0x39, val);
 334
 335     qemu_unregister_reset(pc_cmos_init_late, opaque);
 336 }
 337
 338 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 339                   const char *boot_device,
 340                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 341                   ISADevice *s)
 342 {
 343     int val, nb, i;
 344     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 345     static pc_cmos_init_late_arg arg;
 346
 347     /* various important CMOS locations needed by PC/Bochs bios */
 348
 349     /* memory size */
 350     /* base memory (first MiB) */
 351     val = MIN(ram_size / 1024, 640);
 352     rtc_set_memory(s, 0x15, val);
 353     rtc_set_memory(s, 0x16, val >> 8);
 354     /* extended memory (next 64MiB) */
 355     if (ram_size > 1024 * 1024) {
 356         val = (ram_size - 1024 * 1024) / 1024;
 357     } else {
 358         val = 0;
 359     }
 360     if (val > 65535)
 361         val = 65535;
 362     rtc_set_memory(s, 0x17, val);
 363     rtc_set_memory(s, 0x18, val >> 8);
 364     rtc_set_memory(s, 0x30, val);
 365     rtc_set_memory(s, 0x31, val >> 8);
 366     /* memory between 16MiB and 4GiB */
 367     if (ram_size > 16 * 1024 * 1024) {
 368         val = (ram_size - 16 * 1024 * 1024) / 65536;
 369     } else {
 370         val = 0;
 371     }
 372     if (val > 65535)
 373         val = 65535;
 374     rtc_set_memory(s, 0x34, val);
 375     rtc_set_memory(s, 0x35, val >> 8);
 376     /* memory above 4GiB */
 377     val = above_4g_mem_size / 65536;
 378     rtc_set_memory(s, 0x5b, val);
 379     rtc_set_memory(s, 0x5c, val >> 8);
 380     rtc_set_memory(s, 0x5d, val >> 16);
 381
 382     /* set the number of CPU */
 383     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 384
 385     /* set boot devices, and disable floppy signature check if requested */
 386     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 387         exit(1);
 388     }
 389
 390     /* floppy type */
 391     if (floppy) {
 392         for (i = 0; i < 2; i++) {
 393             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 394         }
 395     }
 396     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 397         cmos_get_fd_drive_type(fd_type[1]);
 398     rtc_set_memory(s, 0x10, val);
 399
 400     val = 0;
 401     nb = 0;
 402     if (fd_type[0] < FDRIVE_DRV_NONE) {
 403         nb++;
 404     }
 405     if (fd_type[1] < FDRIVE_DRV_NONE) {
 406         nb++;
 407     }
 408     switch (nb) {
 409     case 0:
 410         break;
 411     case 1:
 412         val |= 0x01; /* 1 drive, ready for boot */
 413         break;
 414     case 2:
 415         val |= 0x41; /* 2 drives, ready for boot */
 416         break;
 417     }
 418     val |= 0x02; /* FPU is there */
 419     val |= 0x04; /* PS/2 mouse installed */
 420     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 421
 422     /* hard drives */
 423     arg.rtc_state = s;
 424     arg.idebus[0] = idebus0;
 425     arg.idebus[1] = idebus1;
 426     qemu_register_reset(pc_cmos_init_late, &arg);
 427 }
 428
 429 /* port 92 stuff: could be split off */
 430 typedef struct Port92State {
 431     ISADevice dev;
 432     MemoryRegion io;
 433     uint8_t outport;
 434     qemu_irq *a20_out;
 435 } Port92State;
 436
 437 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 438                          unsigned size)
 439 {
 440     Port92State *s = opaque;
 441
 442     DPRINTF("port92: write 0x%02x\n", val);
 443     s->outport = val;
 444     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 445     if (val & 1) {
 446         qemu_system_reset_request();
 447     }
 448 }
 449
 450 static uint64_t port92_read(void *opaque, hwaddr addr,
 451                             unsigned size)
 452 {
 453     Port92State *s = opaque;
 454     uint32_t ret;
 455
 456     ret = s->outport;
 457     DPRINTF("port92: read 0x%02x\n", ret);
 458     return ret;
 459 }
 460
 461 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 462 {
 463     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 464
 465     s->a20_out = a20_out;
 466 }
 467
 468 static const VMStateDescription vmstate_port92_isa = {
 469     .name = "port92",
 470     .version_id = 1,
 471     .minimum_version_id = 1,
 472     .minimum_version_id_old = 1,
 473     .fields      = (VMStateField []) {
 474         VMSTATE_UINT8(outport, Port92State),
 475         VMSTATE_END_OF_LIST()
 476     }
 477 };
 478
 479 static void port92_reset(DeviceState *d)
 480 {
 481     Port92State *s = container_of(d, Port92State, dev.qdev);
 482
 483     s->outport &= ~1;
 484 }
 485
 486 static const MemoryRegionOps port92_ops = {
 487     .read = port92_read,
 488     .write = port92_write,
 489     .impl = {
 490         .min_access_size = 1,
 491         .max_access_size = 1,
 492     },
 493     .endianness = DEVICE_LITTLE_ENDIAN,
 494 };
 495
 496 static int port92_initfn(ISADevice *dev)
 497 {
 498     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 499
 500     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 501     isa_register_ioport(dev, &s->io, 0x92);
 502
 503     s->outport = 0;
 504     return 0;
 505 }
 506
 507 static void port92_class_initfn(ObjectClass *klass, void *data)
 508 {
 509     DeviceClass *dc = DEVICE_CLASS(klass);
 510     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 511     ic->init = port92_initfn;
 512     dc->no_user = 1;
 513     dc->reset = port92_reset;
 514     dc->vmsd = &vmstate_port92_isa;
 515 }
 516
 517 static const TypeInfo port92_info = {
 518     .name          = "port92",
 519     .parent        = TYPE_ISA_DEVICE,
 520     .instance_size = sizeof(Port92State),
 521     .class_init    = port92_class_initfn,
 522 };
 523
 524 static void port92_register_types(void)
 525 {
 526     type_register_static(&port92_info);
 527 }
 528
 529 type_init(port92_register_types)
 530
 531 static void handle_a20_line_change(void *opaque, int irq, int level)
 532 {
 533     X86CPU *cpu = opaque;
 534
 535     /* XXX: send to all CPUs ? */
 536     /* XXX: add logic to handle multiple A20 line sources */
 537     x86_cpu_set_a20(cpu, level);
 538 }
 539
 540 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 541 {
 542     int index = le32_to_cpu(e820_table.count);
 543     struct e820_entry *entry;
 544
 545     if (index >= E820_NR_ENTRIES)
 546         return -EBUSY;
 547     entry = &e820_table.entry[index++];
 548
 549     entry->address = cpu_to_le64(address);
 550     entry->length = cpu_to_le64(length);
 551     entry->type = cpu_to_le32(type);
 552
 553     e820_table.count = cpu_to_le32(index);
 554     return index;
 555 }
 556
 557 /* Calculates the limit to CPU APIC ID values
 558  *
 559  * This function returns the limit for the APIC ID value, so that all
 560  * CPU APIC IDs are < pc_apic_id_limit().
 561  *
 562  * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
 563  */
 564 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
 565 {
 566     return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
 567 }
 568
 569 static void *bochs_bios_init(void)
 570 {
 571     void *fw_cfg;
 572     uint8_t *smbios_table;
 573     size_t smbios_len;
 574     uint64_t *numa_fw_cfg;
 575     int i, j;
 576     unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
 577
 578     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 579     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 580      *
 581      * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
 582      * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
 583      * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
 584      * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
 585      * may see".
 586      *
 587      * So, this means we must not use max_cpus, here, but the maximum possible
 588      * APIC ID value, plus one.
 589      *
 590      * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
 591      *     the APIC ID, not the "CPU index"
 592      */
 593     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
 594     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 595     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 596     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 597                      acpi_tables, acpi_tables_len);
 598     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 599
 600     smbios_table = smbios_get_table(&smbios_len);
 601     if (smbios_table)
 602         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 603                          smbios_table, smbios_len);
 604     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 605                      &e820_table, sizeof(e820_table));
 606
 607     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 608     /* allocate memory for the NUMA channel: one (64bit) word for the number
 609      * of nodes, one word for each VCPU->node and one word for each node to
 610      * hold the amount of memory.
 611      */
 612     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 613     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 614     for (i = 0; i < max_cpus; i++) {
 615         unsigned int apic_id = x86_cpu_apic_id_from_index(i);
 616         assert(apic_id < apic_id_limit);
 617         for (j = 0; j < nb_numa_nodes; j++) {
 618             if (test_bit(i, node_cpumask[j])) {
 619                 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
 620                 break;
 621             }
 622         }
 623     }
 624     for (i = 0; i < nb_numa_nodes; i++) {
 625         numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
 626     }
 627     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 628                      (1 + apic_id_limit + nb_numa_nodes) *
 629                      sizeof(*numa_fw_cfg));
 630
 631     return fw_cfg;
 632 }
 633
 634 static long get_file_size(FILE *f)
 635 {
 636     long where, size;
 637
 638     /* XXX: on Unix systems, using fstat() probably makes more sense */
 639
 640     where = ftell(f);
 641     fseek(f, 0, SEEK_END);
 642     size = ftell(f);
 643     fseek(f, where, SEEK_SET);
 644
 645     return size;
 646 }
 647
 648 static void load_linux(void *fw_cfg,
 649                        const char *kernel_filename,
 650                        const char *initrd_filename,
 651                        const char *kernel_cmdline,
 652                        hwaddr max_ram_size)
 653 {
 654     uint16_t protocol;
 655     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 656     uint32_t initrd_max;
 657     uint8_t header[8192], *setup, *kernel, *initrd_data;
 658     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 659     FILE *f;
 660     char *vmode;
 661
 662     /* Align to 16 bytes as a paranoia measure */
 663     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 664
 665     /* load the kernel header */
 666     f = fopen(kernel_filename, "rb");
 667     if (!f || !(kernel_size = get_file_size(f)) ||
 668         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 669         MIN(ARRAY_SIZE(header), kernel_size)) {
 670         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 671                 kernel_filename, strerror(errno));
 672         exit(1);
 673     }
 674
 675     /* kernel protocol version */
 676 #if 0
 677     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 678 #endif
 679     if (ldl_p(header+0x202) == 0x53726448) {
 680         protocol = lduw_p(header+0x206);
 681     } else {
 682         /* This looks like a multiboot kernel. If it is, let's stop
 683            treating it like a Linux kernel. */
 684         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 685                            kernel_cmdline, kernel_size, header)) {
 686             return;
 687         }
 688         protocol = 0;
 689     }
 690
 691     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 692         /* Low kernel */
 693         real_addr    = 0x90000;
 694         cmdline_addr = 0x9a000 - cmdline_size;
 695         prot_addr    = 0x10000;
 696     } else if (protocol < 0x202) {
 697         /* High but ancient kernel */
 698         real_addr    = 0x90000;
 699         cmdline_addr = 0x9a000 - cmdline_size;
 700         prot_addr    = 0x100000;
 701     } else {
 702         /* High and recent kernel */
 703         real_addr    = 0x10000;
 704         cmdline_addr = 0x20000;
 705         prot_addr    = 0x100000;
 706     }
 707
 708 #if 0
 709     fprintf(stderr,
 710             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 711             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 712             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 713             real_addr,
 714             cmdline_addr,
 715             prot_addr);
 716 #endif
 717
 718     /* highest address for loading the initrd */
 719     if (protocol >= 0x203) {
 720         initrd_max = ldl_p(header+0x22c);
 721     } else {
 722         initrd_max = 0x37ffffff;
 723     }
 724
 725     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 726         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 727
 728     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 729     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 730     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 731
 732     if (protocol >= 0x202) {
 733         stl_p(header+0x228, cmdline_addr);
 734     } else {
 735         stw_p(header+0x20, 0xA33F);
 736         stw_p(header+0x22, cmdline_addr-real_addr);
 737     }
 738
 739     /* handle vga= parameter */
 740     vmode = strstr(kernel_cmdline, "vga=");
 741     if (vmode) {
 742         unsigned int video_mode;
 743         /* skip "vga=" */
 744         vmode += 4;
 745         if (!strncmp(vmode, "normal", 6)) {
 746             video_mode = 0xffff;
 747         } else if (!strncmp(vmode, "ext", 3)) {
 748             video_mode = 0xfffe;
 749         } else if (!strncmp(vmode, "ask", 3)) {
 750             video_mode = 0xfffd;
 751         } else {
 752             video_mode = strtol(vmode, NULL, 0);
 753         }
 754         stw_p(header+0x1fa, video_mode);
 755     }
 756
 757     /* loader type */
 758     /* High nybble = B reserved for QEMU; low nybble is revision number.
 759        If this code is substantially changed, you may want to consider
 760        incrementing the revision. */
 761     if (protocol >= 0x200) {
 762         header[0x210] = 0xB0;
 763     }
 764     /* heap */
 765     if (protocol >= 0x201) {
 766         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 767         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 768     }
 769
 770     /* load initrd */
 771     if (initrd_filename) {
 772         if (protocol < 0x200) {
 773             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 774             exit(1);
 775         }
 776
 777         initrd_size = get_image_size(initrd_filename);
 778         if (initrd_size < 0) {
 779             fprintf(stderr, "qemu: error reading initrd %s\n",
 780                     initrd_filename);
 781             exit(1);
 782         }
 783
 784         initrd_addr = (initrd_max-initrd_size) & ~4095;
 785
 786         initrd_data = g_malloc(initrd_size);
 787         load_image(initrd_filename, initrd_data);
 788
 789         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 790         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 791         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 792
 793         stl_p(header+0x218, initrd_addr);
 794         stl_p(header+0x21c, initrd_size);
 795     }
 796
 797     /* load kernel and setup */
 798     setup_size = header[0x1f1];
 799     if (setup_size == 0) {
 800         setup_size = 4;
 801     }
 802     setup_size = (setup_size+1)*512;
 803     kernel_size -= setup_size;
 804
 805     setup  = g_malloc(setup_size);
 806     kernel = g_malloc(kernel_size);
 807     fseek(f, 0, SEEK_SET);
 808     if (fread(setup, 1, setup_size, f) != setup_size) {
 809         fprintf(stderr, "fread() failed\n");
 810         exit(1);
 811     }
 812     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 813         fprintf(stderr, "fread() failed\n");
 814         exit(1);
 815     }
 816     fclose(f);
 817     memcpy(setup, header, MIN(sizeof(header), setup_size));
 818
 819     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 820     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 821     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 822
 823     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 824     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 825     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 826
 827     option_rom[nb_option_roms].name = "linuxboot.bin";
 828     option_rom[nb_option_roms].bootindex = 0;
 829     nb_option_roms++;
 830 }
 831
 832 #define NE2000_NB_MAX 6
 833
 834 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 835                                               0x280, 0x380 };
 836 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 837
 838 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 839 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 840
 841 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 842 {
 843     static int nb_ne2k = 0;
 844
 845     if (nb_ne2k == NE2000_NB_MAX)
 846         return;
 847     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 848                     ne2000_irq[nb_ne2k], nd);
 849     nb_ne2k++;
 850 }
 851
 852 DeviceState *cpu_get_current_apic(void)
 853 {
 854     if (cpu_single_env) {
 855         return cpu_single_env->apic_state;
 856     } else {
 857         return NULL;
 858     }
 859 }
 860
 861 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 862 {
 863     X86CPU *cpu = opaque;
 864
 865     if (level) {
 866         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
 867     }
 868 }
 869
 870 void pc_cpus_init(const char *cpu_model)
 871 {
 872     int i;
 873
 874     /* init CPUs */
 875     if (cpu_model == NULL) {
 876 #ifdef TARGET_X86_64
 877         cpu_model = "qemu64";
 878 #else
 879         cpu_model = "qemu32";
 880 #endif
 881     }
 882
 883     for (i = 0; i < smp_cpus; i++) {
 884         if (!cpu_x86_init(cpu_model)) {
 885             exit(1);
 886         }
 887     }
 888 }
 889
 890 void pc_acpi_init(const char *default_dsdt)
 891 {
 892     char *filename = NULL, *arg = NULL;
 893     QemuOpts *opts;
 894     Error *err = NULL;
 895
 896     if (acpi_tables != NULL) {
 897         /* manually set via -acpitable, leave it alone */
 898         return;
 899     }
 900
 901     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
 902     if (filename == NULL) {
 903         fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
 904         return;
 905     }
 906
 907     arg = g_strdup_printf("file=%s", filename);
 908
 909     /* creates a deep copy of "arg" */
 910     opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
 911     g_assert(opts != NULL);
 912
 913     acpi_table_add(opts, &err);
 914     if (err) {
 915         fprintf(stderr, "WARNING: failed to load %s: %s\n", filename,
 916                 error_get_pretty(err));
 917         error_free(err);
 918     }
 919     g_free(arg);
 920     g_free(filename);
 921 }
 922
 923 void *pc_memory_init(MemoryRegion *system_memory,
 924                     const char *kernel_filename,
 925                     const char *kernel_cmdline,
 926                     const char *initrd_filename,
 927                     ram_addr_t below_4g_mem_size,
 928                     ram_addr_t above_4g_mem_size,
 929                     MemoryRegion *rom_memory,
 930                     MemoryRegion **ram_memory)
 931 {
 932     int linux_boot, i;
 933     MemoryRegion *ram, *option_rom_mr;
 934     MemoryRegion *ram_below_4g, *ram_above_4g;
 935     void *fw_cfg;
 936
 937     linux_boot = (kernel_filename != NULL);
 938
 939     /* Allocate RAM.  We allocate it as a single memory region and use
 940      * aliases to address portions of it, mostly for backwards compatibility
 941      * with older qemus that used qemu_ram_alloc().
 942      */
 943     ram = g_malloc(sizeof(*ram));
 944     memory_region_init_ram(ram, "pc.ram",
 945                            below_4g_mem_size + above_4g_mem_size);
 946     vmstate_register_ram_global(ram);
 947     *ram_memory = ram;
 948     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 949     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 950                              0, below_4g_mem_size);
 951     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 952     if (above_4g_mem_size > 0) {
 953         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
 954         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
 955                                  below_4g_mem_size, above_4g_mem_size);
 956         memory_region_add_subregion(system_memory, 0x100000000ULL,
 957                                     ram_above_4g);
 958     }
 959
 960
 961     /* Initialize PC system firmware */
 962     pc_system_firmware_init(rom_memory);
 963
 964     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
 965     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
 966     vmstate_register_ram_global(option_rom_mr);
 967     memory_region_add_subregion_overlap(rom_memory,
 968                                         PC_ROM_MIN_VGA,
 969                                         option_rom_mr,
 970                                         1);
 971
 972     fw_cfg = bochs_bios_init();
 973     rom_set_fw(fw_cfg);
 974
 975     if (linux_boot) {
 976         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 977     }
 978
 979     for (i = 0; i < nb_option_roms; i++) {
 980         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
 981     }
 982     return fw_cfg;
 983 }
 984
 985 qemu_irq *pc_allocate_cpu_irq(void)
 986 {
 987     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 988 }
 989
 990 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
 991 {
 992     DeviceState *dev = NULL;
 993
 994     if (pci_bus) {
 995         PCIDevice *pcidev = pci_vga_init(pci_bus);
 996         dev = pcidev ? &pcidev->qdev : NULL;
 997     } else if (isa_bus) {
 998         ISADevice *isadev = isa_vga_init(isa_bus);
 999         dev = isadev ? &isadev->qdev : NULL;
1000     }
1001     return dev;
1002 }
1003
1004 static void cpu_request_exit(void *opaque, int irq, int level)
1005 {
1006     CPUX86State *env = cpu_single_env;
1007
1008     if (env && level) {
1009         cpu_exit(env);
1010     }
1011 }
1012
1013 static const MemoryRegionOps ioport80_io_ops = {
1014     .write = ioport80_write,
1015     .read = ioport80_read,
1016     .endianness = DEVICE_NATIVE_ENDIAN,
1017     .impl = {
1018         .min_access_size = 1,
1019         .max_access_size = 1,
1020     },
1021 };
1022
1023 static const MemoryRegionOps ioportF0_io_ops = {
1024     .write = ioportF0_write,
1025     .read = ioportF0_read,
1026     .endianness = DEVICE_NATIVE_ENDIAN,
1027     .impl = {
1028         .min_access_size = 1,
1029         .max_access_size = 1,
1030     },
1031 };
1032
1033 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1034                           ISADevice **rtc_state,
1035                           ISADevice **floppy,
1036                           bool no_vmport)
1037 {
1038     int i;
1039     DriveInfo *fd[MAX_FD];
1040     DeviceState *hpet = NULL;
1041     int pit_isa_irq = 0;
1042     qemu_irq pit_alt_irq = NULL;
1043     qemu_irq rtc_irq = NULL;
1044     qemu_irq *a20_line;
1045     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1046     qemu_irq *cpu_exit_irq;
1047     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1048     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1049
1050     memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1);
1051     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1052
1053     memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1);
1054     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1055
1056     /*
1057      * Check if an HPET shall be created.
1058      *
1059      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1060      * when the HPET wants to take over. Thus we have to disable the latter.
1061      */
1062     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1063         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1064
1065         if (hpet) {
1066             for (i = 0; i < GSI_NUM_PINS; i++) {
1067                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1068             }
1069             pit_isa_irq = -1;
1070             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1071             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1072         }
1073     }
1074     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1075
1076     qemu_register_boot_set(pc_boot_set, *rtc_state);
1077
1078     if (!xen_enabled()) {
1079         if (kvm_irqchip_in_kernel()) {
1080             pit = kvm_pit_init(isa_bus, 0x40);
1081         } else {
1082             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1083         }
1084         if (hpet) {
1085             /* connect PIT to output control line of the HPET */
1086             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1087         }
1088         pcspk_init(isa_bus, pit);
1089     }
1090
1091     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1092         if (serial_hds[i]) {
1093             serial_isa_init(isa_bus, i, serial_hds[i]);
1094         }
1095     }
1096
1097     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1098         if (parallel_hds[i]) {
1099             parallel_init(isa_bus, i, parallel_hds[i]);
1100         }
1101     }
1102
1103     a20_line = qemu_allocate_irqs(handle_a20_line_change,
1104                                   x86_env_get_cpu(first_cpu), 2);
1105     i8042 = isa_create_simple(isa_bus, "i8042");
1106     i8042_setup_a20_line(i8042, &a20_line[0]);
1107     if (!no_vmport) {
1108         vmport_init(isa_bus);
1109         vmmouse = isa_try_create(isa_bus, "vmmouse");
1110     } else {
1111         vmmouse = NULL;
1112     }
1113     if (vmmouse) {
1114         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1115         qdev_init_nofail(&vmmouse->qdev);
1116     }
1117     port92 = isa_create_simple(isa_bus, "port92");
1118     port92_init(port92, &a20_line[1]);
1119
1120     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1121     DMA_init(0, cpu_exit_irq);
1122
1123     for(i = 0; i < MAX_FD; i++) {
1124         fd[i] = drive_get(IF_FLOPPY, 0, i);
1125     }
1126     *floppy = fdctrl_init_isa(isa_bus, fd);
1127 }
1128
1129 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1130 {
1131     int i;
1132
1133     for (i = 0; i < nb_nics; i++) {
1134         NICInfo *nd = &nd_table[i];
1135
1136         if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1137             pc_init_ne2k_isa(isa_bus, nd);
1138         } else {
1139             pci_nic_init_nofail(nd, "e1000", NULL);
1140         }
1141     }
1142 }
1143
1144 void pc_pci_device_init(PCIBus *pci_bus)
1145 {
1146     int max_bus;
1147     int bus;
1148
1149     max_bus = drive_get_max_bus(IF_SCSI);
1150     for (bus = 0; bus <= max_bus; bus++) {
1151         pci_create_simple(pci_bus, -1, "lsi53c895a");
1152     }
1153 }
1154
1155 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1156 {
1157     DeviceState *dev;
1158     SysBusDevice *d;
1159     unsigned int i;
1160
1161     if (kvm_irqchip_in_kernel()) {
1162         dev = qdev_create(NULL, "kvm-ioapic");
1163     } else {
1164         dev = qdev_create(NULL, "ioapic");
1165     }
1166     if (parent_name) {
1167         object_property_add_child(object_resolve_path(parent_name, NULL),
1168                                   "ioapic", OBJECT(dev), NULL);
1169     }
1170     qdev_init_nofail(dev);
1171     d = SYS_BUS_DEVICE(dev);
1172     sysbus_mmio_map(d, 0, 0xfec00000);
1173
1174     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1175         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1176     }
1177 }