hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/i386/pc.h"
  26 #include "hw/char/serial.h"
  27 #include "hw/i386/apic.h"
  28 #include "hw/block/fdc.h"
  29 #include "hw/ide.h"
  30 #include "hw/pci/pci.h"
  31 #include "monitor/monitor.h"
  32 #include "hw/nvram/fw_cfg.h"
  33 #include "hw/timer/hpet.h"
  34 #include "hw/i386/smbios.h"
  35 #include "hw/loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "hw/timer/mc146818rtc.h"
  39 #include "hw/timer/i8254.h"
  40 #include "hw/audio/pcspk.h"
  41 #include "hw/pci/msi.h"
  42 #include "hw/sysbus.h"
  43 #include "sysemu/sysemu.h"
  44 #include "sysemu/kvm.h"
  45 #include "kvm_i386.h"
  46 #include "hw/xen/xen.h"
  47 #include "sysemu/blockdev.h"
  48 #include "hw/block/block.h"
  49 #include "ui/qemu-spice.h"
  50 #include "exec/memory.h"
  51 #include "exec/address-spaces.h"
  52 #include "sysemu/arch_init.h"
  53 #include "qemu/bitmap.h"
  54 #include "qemu/config-file.h"
  55 #include "hw/acpi/acpi.h"
  56 #include "hw/cpu/icc_bus.h"
  57 #include "hw/boards.h"
  58
  59 /* debug PC/ISA interrupts */
  60 //#define DEBUG_IRQ
  61
  62 #ifdef DEBUG_IRQ
  63 #define DPRINTF(fmt, ...)                                       \
  64     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  65 #else
  66 #define DPRINTF(fmt, ...)
  67 #endif
  68
  69 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  70 #define ACPI_DATA_SIZE       0x10000
  71 #define BIOS_CFG_IOPORT 0x510
  72 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  73 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  74 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  75 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  76 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  77
  78 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000
  79
  80 #define E820_NR_ENTRIES         16
  81
  82 struct e820_entry {
  83     uint64_t address;
  84     uint64_t length;
  85     uint32_t type;
  86 } QEMU_PACKED __attribute((__aligned__(4)));
  87
  88 struct e820_table {
  89     uint32_t count;
  90     struct e820_entry entry[E820_NR_ENTRIES];
  91 } QEMU_PACKED __attribute((__aligned__(4)));
  92
  93 static struct e820_table e820_table;
  94 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  95
  96 void gsi_handler(void *opaque, int n, int level)
  97 {
  98     GSIState *s = opaque;
  99
 100     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
 101     if (n < ISA_NUM_IRQS) {
 102         qemu_set_irq(s->i8259_irq[n], level);
 103     }
 104     qemu_set_irq(s->ioapic_irq[n], level);
 105 }
 106
 107 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 108                            unsigned size)
 109 {
 110 }
 111
 112 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 113 {
 114     return 0xffffffffffffffffULL;
 115 }
 116
 117 /* MSDOS compatibility mode FPU exception support */
 118 static qemu_irq ferr_irq;
 119
 120 void pc_register_ferr_irq(qemu_irq irq)
 121 {
 122     ferr_irq = irq;
 123 }
 124
 125 /* XXX: add IGNNE support */
 126 void cpu_set_ferr(CPUX86State *s)
 127 {
 128     qemu_irq_raise(ferr_irq);
 129 }
 130
 131 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 132                            unsigned size)
 133 {
 134     qemu_irq_lower(ferr_irq);
 135 }
 136
 137 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 138 {
 139     return 0xffffffffffffffffULL;
 140 }
 141
 142 /* TSC handling */
 143 uint64_t cpu_get_tsc(CPUX86State *env)
 144 {
 145     return cpu_get_ticks();
 146 }
 147
 148 /* SMM support */
 149
 150 static cpu_set_smm_t smm_set;
 151 static void *smm_arg;
 152
 153 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 154 {
 155     assert(smm_set == NULL);
 156     assert(smm_arg == NULL);
 157     smm_set = callback;
 158     smm_arg = arg;
 159 }
 160
 161 void cpu_smm_update(CPUX86State *env)
 162 {
 163     if (smm_set && smm_arg && env == first_cpu)
 164         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 165 }
 166
 167
 168 /* IRQ handling */
 169 int cpu_get_pic_interrupt(CPUX86State *env)
 170 {
 171     int intno;
 172
 173     intno = apic_get_interrupt(env->apic_state);
 174     if (intno >= 0) {
 175         return intno;
 176     }
 177     /* read the irq from the PIC */
 178     if (!apic_accept_pic_intr(env->apic_state)) {
 179         return -1;
 180     }
 181
 182     intno = pic_read_irq(isa_pic);
 183     return intno;
 184 }
 185
 186 static void pic_irq_request(void *opaque, int irq, int level)
 187 {
 188     CPUX86State *env = first_cpu;
 189
 190     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 191     if (env->apic_state) {
 192         while (env) {
 193             if (apic_accept_pic_intr(env->apic_state)) {
 194                 apic_deliver_pic_intr(env->apic_state, level);
 195             }
 196             env = env->next_cpu;
 197         }
 198     } else {
 199         CPUState *cs = CPU(x86_env_get_cpu(env));
 200         if (level) {
 201             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 202         } else {
 203             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 204         }
 205     }
 206 }
 207
 208 /* PC cmos mappings */
 209
 210 #define REG_EQUIPMENT_BYTE          0x14
 211
 212 static int cmos_get_fd_drive_type(FDriveType fd0)
 213 {
 214     int val;
 215
 216     switch (fd0) {
 217     case FDRIVE_DRV_144:
 218         /* 1.44 Mb 3"5 drive */
 219         val = 4;
 220         break;
 221     case FDRIVE_DRV_288:
 222         /* 2.88 Mb 3"5 drive */
 223         val = 5;
 224         break;
 225     case FDRIVE_DRV_120:
 226         /* 1.2 Mb 5"5 drive */
 227         val = 2;
 228         break;
 229     case FDRIVE_DRV_NONE:
 230     default:
 231         val = 0;
 232         break;
 233     }
 234     return val;
 235 }
 236
 237 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 238                          int16_t cylinders, int8_t heads, int8_t sectors)
 239 {
 240     rtc_set_memory(s, type_ofs, 47);
 241     rtc_set_memory(s, info_ofs, cylinders);
 242     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 243     rtc_set_memory(s, info_ofs + 2, heads);
 244     rtc_set_memory(s, info_ofs + 3, 0xff);
 245     rtc_set_memory(s, info_ofs + 4, 0xff);
 246     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 247     rtc_set_memory(s, info_ofs + 6, cylinders);
 248     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 249     rtc_set_memory(s, info_ofs + 8, sectors);
 250 }
 251
 252 /* convert boot_device letter to something recognizable by the bios */
 253 static int boot_device2nibble(char boot_device)
 254 {
 255     switch(boot_device) {
 256     case 'a':
 257     case 'b':
 258         return 0x01; /* floppy boot */
 259     case 'c':
 260         return 0x02; /* hard drive boot */
 261     case 'd':
 262         return 0x03; /* CD-ROM boot */
 263     case 'n':
 264         return 0x04; /* Network boot */
 265     }
 266     return 0;
 267 }
 268
 269 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 270 {
 271 #define PC_MAX_BOOT_DEVICES 3
 272     int nbds, bds[3] = { 0, };
 273     int i;
 274
 275     nbds = strlen(boot_device);
 276     if (nbds > PC_MAX_BOOT_DEVICES) {
 277         error_report("Too many boot devices for PC");
 278         return(1);
 279     }
 280     for (i = 0; i < nbds; i++) {
 281         bds[i] = boot_device2nibble(boot_device[i]);
 282         if (bds[i] == 0) {
 283             error_report("Invalid boot device for PC: '%c'",
 284                          boot_device[i]);
 285             return(1);
 286         }
 287     }
 288     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 289     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 290     return(0);
 291 }
 292
 293 static int pc_boot_set(void *opaque, const char *boot_device)
 294 {
 295     return set_boot_dev(opaque, boot_device, 0);
 296 }
 297
 298 typedef struct pc_cmos_init_late_arg {
 299     ISADevice *rtc_state;
 300     BusState *idebus[2];
 301 } pc_cmos_init_late_arg;
 302
 303 static void pc_cmos_init_late(void *opaque)
 304 {
 305     pc_cmos_init_late_arg *arg = opaque;
 306     ISADevice *s = arg->rtc_state;
 307     int16_t cylinders;
 308     int8_t heads, sectors;
 309     int val;
 310     int i, trans;
 311
 312     val = 0;
 313     if (ide_get_geometry(arg->idebus[0], 0,
 314                          &cylinders, &heads, &sectors) >= 0) {
 315         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 316         val |= 0xf0;
 317     }
 318     if (ide_get_geometry(arg->idebus[0], 1,
 319                          &cylinders, &heads, &sectors) >= 0) {
 320         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 321         val |= 0x0f;
 322     }
 323     rtc_set_memory(s, 0x12, val);
 324
 325     val = 0;
 326     for (i = 0; i < 4; i++) {
 327         /* NOTE: ide_get_geometry() returns the physical
 328            geometry.  It is always such that: 1 <= sects <= 63, 1
 329            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 330            geometry can be different if a translation is done. */
 331         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 332                              &cylinders, &heads, &sectors) >= 0) {
 333             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 334             assert((trans & ~3) == 0);
 335             val |= trans << (i * 2);
 336         }
 337     }
 338     rtc_set_memory(s, 0x39, val);
 339
 340     qemu_unregister_reset(pc_cmos_init_late, opaque);
 341 }
 342
 343 typedef struct RTCCPUHotplugArg {
 344     Notifier cpu_added_notifier;
 345     ISADevice *rtc_state;
 346 } RTCCPUHotplugArg;
 347
 348 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
 349 {
 350     RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
 351                                          cpu_added_notifier);
 352     ISADevice *s = arg->rtc_state;
 353
 354     /* increment the number of CPUs */
 355     rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
 356 }
 357
 358 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 359                   const char *boot_device,
 360                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 361                   ISADevice *s)
 362 {
 363     int val, nb, i;
 364     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 365     static pc_cmos_init_late_arg arg;
 366     static RTCCPUHotplugArg cpu_hotplug_cb;
 367
 368     /* various important CMOS locations needed by PC/Bochs bios */
 369
 370     /* memory size */
 371     /* base memory (first MiB) */
 372     val = MIN(ram_size / 1024, 640);
 373     rtc_set_memory(s, 0x15, val);
 374     rtc_set_memory(s, 0x16, val >> 8);
 375     /* extended memory (next 64MiB) */
 376     if (ram_size > 1024 * 1024) {
 377         val = (ram_size - 1024 * 1024) / 1024;
 378     } else {
 379         val = 0;
 380     }
 381     if (val > 65535)
 382         val = 65535;
 383     rtc_set_memory(s, 0x17, val);
 384     rtc_set_memory(s, 0x18, val >> 8);
 385     rtc_set_memory(s, 0x30, val);
 386     rtc_set_memory(s, 0x31, val >> 8);
 387     /* memory between 16MiB and 4GiB */
 388     if (ram_size > 16 * 1024 * 1024) {
 389         val = (ram_size - 16 * 1024 * 1024) / 65536;
 390     } else {
 391         val = 0;
 392     }
 393     if (val > 65535)
 394         val = 65535;
 395     rtc_set_memory(s, 0x34, val);
 396     rtc_set_memory(s, 0x35, val >> 8);
 397     /* memory above 4GiB */
 398     val = above_4g_mem_size / 65536;
 399     rtc_set_memory(s, 0x5b, val);
 400     rtc_set_memory(s, 0x5c, val >> 8);
 401     rtc_set_memory(s, 0x5d, val >> 16);
 402
 403     /* set the number of CPU */
 404     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 405     /* init CPU hotplug notifier */
 406     cpu_hotplug_cb.rtc_state = s;
 407     cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
 408     qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
 409
 410     /* set boot devices, and disable floppy signature check if requested */
 411     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 412         exit(1);
 413     }
 414
 415     /* floppy type */
 416     if (floppy) {
 417         for (i = 0; i < 2; i++) {
 418             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 419         }
 420     }
 421     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 422         cmos_get_fd_drive_type(fd_type[1]);
 423     rtc_set_memory(s, 0x10, val);
 424
 425     val = 0;
 426     nb = 0;
 427     if (fd_type[0] < FDRIVE_DRV_NONE) {
 428         nb++;
 429     }
 430     if (fd_type[1] < FDRIVE_DRV_NONE) {
 431         nb++;
 432     }
 433     switch (nb) {
 434     case 0:
 435         break;
 436     case 1:
 437         val |= 0x01; /* 1 drive, ready for boot */
 438         break;
 439     case 2:
 440         val |= 0x41; /* 2 drives, ready for boot */
 441         break;
 442     }
 443     val |= 0x02; /* FPU is there */
 444     val |= 0x04; /* PS/2 mouse installed */
 445     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 446
 447     /* hard drives */
 448     arg.rtc_state = s;
 449     arg.idebus[0] = idebus0;
 450     arg.idebus[1] = idebus1;
 451     qemu_register_reset(pc_cmos_init_late, &arg);
 452 }
 453
 454 #define TYPE_PORT92 "port92"
 455 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 456
 457 /* port 92 stuff: could be split off */
 458 typedef struct Port92State {
 459     ISADevice parent_obj;
 460
 461     MemoryRegion io;
 462     uint8_t outport;
 463     qemu_irq *a20_out;
 464 } Port92State;
 465
 466 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 467                          unsigned size)
 468 {
 469     Port92State *s = opaque;
 470
 471     DPRINTF("port92: write 0x%02x\n", val);
 472     s->outport = val;
 473     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 474     if (val & 1) {
 475         qemu_system_reset_request();
 476     }
 477 }
 478
 479 static uint64_t port92_read(void *opaque, hwaddr addr,
 480                             unsigned size)
 481 {
 482     Port92State *s = opaque;
 483     uint32_t ret;
 484
 485     ret = s->outport;
 486     DPRINTF("port92: read 0x%02x\n", ret);
 487     return ret;
 488 }
 489
 490 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 491 {
 492     Port92State *s = PORT92(dev);
 493
 494     s->a20_out = a20_out;
 495 }
 496
 497 static const VMStateDescription vmstate_port92_isa = {
 498     .name = "port92",
 499     .version_id = 1,
 500     .minimum_version_id = 1,
 501     .minimum_version_id_old = 1,
 502     .fields      = (VMStateField []) {
 503         VMSTATE_UINT8(outport, Port92State),
 504         VMSTATE_END_OF_LIST()
 505     }
 506 };
 507
 508 static void port92_reset(DeviceState *d)
 509 {
 510     Port92State *s = PORT92(d);
 511
 512     s->outport &= ~1;
 513 }
 514
 515 static const MemoryRegionOps port92_ops = {
 516     .read = port92_read,
 517     .write = port92_write,
 518     .impl = {
 519         .min_access_size = 1,
 520         .max_access_size = 1,
 521     },
 522     .endianness = DEVICE_LITTLE_ENDIAN,
 523 };
 524
 525 static int port92_initfn(ISADevice *dev)
 526 {
 527     Port92State *s = PORT92(dev);
 528
 529     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 530     isa_register_ioport(dev, &s->io, 0x92);
 531
 532     s->outport = 0;
 533     return 0;
 534 }
 535
 536 static void port92_class_initfn(ObjectClass *klass, void *data)
 537 {
 538     DeviceClass *dc = DEVICE_CLASS(klass);
 539     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 540     ic->init = port92_initfn;
 541     dc->no_user = 1;
 542     dc->reset = port92_reset;
 543     dc->vmsd = &vmstate_port92_isa;
 544 }
 545
 546 static const TypeInfo port92_info = {
 547     .name          = TYPE_PORT92,
 548     .parent        = TYPE_ISA_DEVICE,
 549     .instance_size = sizeof(Port92State),
 550     .class_init    = port92_class_initfn,
 551 };
 552
 553 static void port92_register_types(void)
 554 {
 555     type_register_static(&port92_info);
 556 }
 557
 558 type_init(port92_register_types)
 559
 560 static void handle_a20_line_change(void *opaque, int irq, int level)
 561 {
 562     X86CPU *cpu = opaque;
 563
 564     /* XXX: send to all CPUs ? */
 565     /* XXX: add logic to handle multiple A20 line sources */
 566     x86_cpu_set_a20(cpu, level);
 567 }
 568
 569 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 570 {
 571     int index = le32_to_cpu(e820_table.count);
 572     struct e820_entry *entry;
 573
 574     if (index >= E820_NR_ENTRIES)
 575         return -EBUSY;
 576     entry = &e820_table.entry[index++];
 577
 578     entry->address = cpu_to_le64(address);
 579     entry->length = cpu_to_le64(length);
 580     entry->type = cpu_to_le32(type);
 581
 582     e820_table.count = cpu_to_le32(index);
 583     return index;
 584 }
 585
 586 /* Calculates the limit to CPU APIC ID values
 587  *
 588  * This function returns the limit for the APIC ID value, so that all
 589  * CPU APIC IDs are < pc_apic_id_limit().
 590  *
 591  * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
 592  */
 593 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
 594 {
 595     return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
 596 }
 597
 598 static FWCfgState *bochs_bios_init(void)
 599 {
 600     FWCfgState *fw_cfg;
 601     uint8_t *smbios_table;
 602     size_t smbios_len;
 603     uint64_t *numa_fw_cfg;
 604     int i, j;
 605     unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
 606
 607     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 608     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 609      *
 610      * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
 611      * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
 612      * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
 613      * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
 614      * may see".
 615      *
 616      * So, this means we must not use max_cpus, here, but the maximum possible
 617      * APIC ID value, plus one.
 618      *
 619      * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
 620      *     the APIC ID, not the "CPU index"
 621      */
 622     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
 623     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 624     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 625     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 626                      acpi_tables, acpi_tables_len);
 627     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 628
 629     smbios_table = smbios_get_table(&smbios_len);
 630     if (smbios_table)
 631         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 632                          smbios_table, smbios_len);
 633     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 634                      &e820_table, sizeof(e820_table));
 635
 636     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 637     /* allocate memory for the NUMA channel: one (64bit) word for the number
 638      * of nodes, one word for each VCPU->node and one word for each node to
 639      * hold the amount of memory.
 640      */
 641     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 642     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 643     for (i = 0; i < max_cpus; i++) {
 644         unsigned int apic_id = x86_cpu_apic_id_from_index(i);
 645         assert(apic_id < apic_id_limit);
 646         for (j = 0; j < nb_numa_nodes; j++) {
 647             if (test_bit(i, node_cpumask[j])) {
 648                 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
 649                 break;
 650             }
 651         }
 652     }
 653     for (i = 0; i < nb_numa_nodes; i++) {
 654         numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
 655     }
 656     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 657                      (1 + apic_id_limit + nb_numa_nodes) *
 658                      sizeof(*numa_fw_cfg));
 659
 660     return fw_cfg;
 661 }
 662
 663 static long get_file_size(FILE *f)
 664 {
 665     long where, size;
 666
 667     /* XXX: on Unix systems, using fstat() probably makes more sense */
 668
 669     where = ftell(f);
 670     fseek(f, 0, SEEK_END);
 671     size = ftell(f);
 672     fseek(f, where, SEEK_SET);
 673
 674     return size;
 675 }
 676
 677 static void load_linux(FWCfgState *fw_cfg,
 678                        const char *kernel_filename,
 679                        const char *initrd_filename,
 680                        const char *kernel_cmdline,
 681                        hwaddr max_ram_size)
 682 {
 683     uint16_t protocol;
 684     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 685     uint32_t initrd_max;
 686     uint8_t header[8192], *setup, *kernel, *initrd_data;
 687     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 688     FILE *f;
 689     char *vmode;
 690
 691     /* Align to 16 bytes as a paranoia measure */
 692     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 693
 694     /* load the kernel header */
 695     f = fopen(kernel_filename, "rb");
 696     if (!f || !(kernel_size = get_file_size(f)) ||
 697         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 698         MIN(ARRAY_SIZE(header), kernel_size)) {
 699         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 700                 kernel_filename, strerror(errno));
 701         exit(1);
 702     }
 703
 704     /* kernel protocol version */
 705 #if 0
 706     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 707 #endif
 708     if (ldl_p(header+0x202) == 0x53726448) {
 709         protocol = lduw_p(header+0x206);
 710     } else {
 711         /* This looks like a multiboot kernel. If it is, let's stop
 712            treating it like a Linux kernel. */
 713         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 714                            kernel_cmdline, kernel_size, header)) {
 715             return;
 716         }
 717         protocol = 0;
 718     }
 719
 720     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 721         /* Low kernel */
 722         real_addr    = 0x90000;
 723         cmdline_addr = 0x9a000 - cmdline_size;
 724         prot_addr    = 0x10000;
 725     } else if (protocol < 0x202) {
 726         /* High but ancient kernel */
 727         real_addr    = 0x90000;
 728         cmdline_addr = 0x9a000 - cmdline_size;
 729         prot_addr    = 0x100000;
 730     } else {
 731         /* High and recent kernel */
 732         real_addr    = 0x10000;
 733         cmdline_addr = 0x20000;
 734         prot_addr    = 0x100000;
 735     }
 736
 737 #if 0
 738     fprintf(stderr,
 739             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 740             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 741             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 742             real_addr,
 743             cmdline_addr,
 744             prot_addr);
 745 #endif
 746
 747     /* highest address for loading the initrd */
 748     if (protocol >= 0x203) {
 749         initrd_max = ldl_p(header+0x22c);
 750     } else {
 751         initrd_max = 0x37ffffff;
 752     }
 753
 754     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 755         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 756
 757     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 758     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 759     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 760
 761     if (protocol >= 0x202) {
 762         stl_p(header+0x228, cmdline_addr);
 763     } else {
 764         stw_p(header+0x20, 0xA33F);
 765         stw_p(header+0x22, cmdline_addr-real_addr);
 766     }
 767
 768     /* handle vga= parameter */
 769     vmode = strstr(kernel_cmdline, "vga=");
 770     if (vmode) {
 771         unsigned int video_mode;
 772         /* skip "vga=" */
 773         vmode += 4;
 774         if (!strncmp(vmode, "normal", 6)) {
 775             video_mode = 0xffff;
 776         } else if (!strncmp(vmode, "ext", 3)) {
 777             video_mode = 0xfffe;
 778         } else if (!strncmp(vmode, "ask", 3)) {
 779             video_mode = 0xfffd;
 780         } else {
 781             video_mode = strtol(vmode, NULL, 0);
 782         }
 783         stw_p(header+0x1fa, video_mode);
 784     }
 785
 786     /* loader type */
 787     /* High nybble = B reserved for QEMU; low nybble is revision number.
 788        If this code is substantially changed, you may want to consider
 789        incrementing the revision. */
 790     if (protocol >= 0x200) {
 791         header[0x210] = 0xB0;
 792     }
 793     /* heap */
 794     if (protocol >= 0x201) {
 795         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 796         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 797     }
 798
 799     /* load initrd */
 800     if (initrd_filename) {
 801         if (protocol < 0x200) {
 802             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 803             exit(1);
 804         }
 805
 806         initrd_size = get_image_size(initrd_filename);
 807         if (initrd_size < 0) {
 808             fprintf(stderr, "qemu: error reading initrd %s\n",
 809                     initrd_filename);
 810             exit(1);
 811         }
 812
 813         initrd_addr = (initrd_max-initrd_size) & ~4095;
 814
 815         initrd_data = g_malloc(initrd_size);
 816         load_image(initrd_filename, initrd_data);
 817
 818         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 819         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 820         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 821
 822         stl_p(header+0x218, initrd_addr);
 823         stl_p(header+0x21c, initrd_size);
 824     }
 825
 826     /* load kernel and setup */
 827     setup_size = header[0x1f1];
 828     if (setup_size == 0) {
 829         setup_size = 4;
 830     }
 831     setup_size = (setup_size+1)*512;
 832     kernel_size -= setup_size;
 833
 834     setup  = g_malloc(setup_size);
 835     kernel = g_malloc(kernel_size);
 836     fseek(f, 0, SEEK_SET);
 837     if (fread(setup, 1, setup_size, f) != setup_size) {
 838         fprintf(stderr, "fread() failed\n");
 839         exit(1);
 840     }
 841     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 842         fprintf(stderr, "fread() failed\n");
 843         exit(1);
 844     }
 845     fclose(f);
 846     memcpy(setup, header, MIN(sizeof(header), setup_size));
 847
 848     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 849     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 850     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 851
 852     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 853     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 854     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 855
 856     option_rom[nb_option_roms].name = "linuxboot.bin";
 857     option_rom[nb_option_roms].bootindex = 0;
 858     nb_option_roms++;
 859 }
 860
 861 #define NE2000_NB_MAX 6
 862
 863 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 864                                               0x280, 0x380 };
 865 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 866
 867 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 868 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 869
 870 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 871 {
 872     static int nb_ne2k = 0;
 873
 874     if (nb_ne2k == NE2000_NB_MAX)
 875         return;
 876     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 877                     ne2000_irq[nb_ne2k], nd);
 878     nb_ne2k++;
 879 }
 880
 881 DeviceState *cpu_get_current_apic(void)
 882 {
 883     if (cpu_single_env) {
 884         return cpu_single_env->apic_state;
 885     } else {
 886         return NULL;
 887     }
 888 }
 889
 890 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 891 {
 892     X86CPU *cpu = opaque;
 893
 894     if (level) {
 895         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
 896     }
 897 }
 898
 899 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
 900                           DeviceState *icc_bridge, Error **errp)
 901 {
 902     X86CPU *cpu;
 903     Error *local_err = NULL;
 904
 905     cpu = cpu_x86_create(cpu_model, icc_bridge, errp);
 906     if (!cpu) {
 907         return cpu;
 908     }
 909
 910     object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
 911     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 912
 913     if (local_err) {
 914         if (cpu != NULL) {
 915             object_unref(OBJECT(cpu));
 916             cpu = NULL;
 917         }
 918         error_propagate(errp, local_err);
 919     }
 920     return cpu;
 921 }
 922
 923 static const char *current_cpu_model;
 924
 925 void pc_hot_add_cpu(const int64_t id, Error **errp)
 926 {
 927     DeviceState *icc_bridge;
 928     int64_t apic_id = x86_cpu_apic_id_from_index(id);
 929
 930     if (cpu_exists(apic_id)) {
 931         error_setg(errp, "Unable to add CPU: %" PRIi64
 932                    ", it already exists", id);
 933         return;
 934     }
 935
 936     if (id >= max_cpus) {
 937         error_setg(errp, "Unable to add CPU: %" PRIi64
 938                    ", max allowed: %d", id, max_cpus - 1);
 939         return;
 940     }
 941
 942     icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
 943                                                  TYPE_ICC_BRIDGE, NULL));
 944     pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
 945 }
 946
 947 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
 948 {
 949     int i;
 950     X86CPU *cpu = NULL;
 951     Error *error = NULL;
 952
 953     /* init CPUs */
 954     if (cpu_model == NULL) {
 955 #ifdef TARGET_X86_64
 956         cpu_model = "qemu64";
 957 #else
 958         cpu_model = "qemu32";
 959 #endif
 960     }
 961     current_cpu_model = cpu_model;
 962
 963     for (i = 0; i < smp_cpus; i++) {
 964         cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
 965                          icc_bridge, &error);
 966         if (error) {
 967             fprintf(stderr, "%s\n", error_get_pretty(error));
 968             error_free(error);
 969             exit(1);
 970         }
 971     }
 972
 973     /* map APIC MMIO area if CPU has APIC */
 974     if (cpu && cpu->env.apic_state) {
 975         /* XXX: what if the base changes? */
 976         sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
 977                                 APIC_DEFAULT_ADDRESS, 0x1000);
 978     }
 979 }
 980
 981 void pc_acpi_init(const char *default_dsdt)
 982 {
 983     char *filename;
 984
 985     if (acpi_tables != NULL) {
 986         /* manually set via -acpitable, leave it alone */
 987         return;
 988     }
 989
 990     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
 991     if (filename == NULL) {
 992         fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
 993     } else {
 994         char *arg;
 995         QemuOpts *opts;
 996         Error *err = NULL;
 997
 998         arg = g_strdup_printf("file=%s", filename);
 999
1000         /* creates a deep copy of "arg" */
1001         opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1002         g_assert(opts != NULL);
1003
1004         acpi_table_add(opts, &err);
1005         if (err) {
1006             fprintf(stderr, "WARNING: failed to load %s: %s\n", filename,
1007                     error_get_pretty(err));
1008             error_free(err);
1009         }
1010         g_free(arg);
1011         g_free(filename);
1012     }
1013 }
1014
1015 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
1016                            const char *kernel_filename,
1017                            const char *kernel_cmdline,
1018                            const char *initrd_filename,
1019                            ram_addr_t below_4g_mem_size,
1020                            ram_addr_t above_4g_mem_size,
1021                            MemoryRegion *rom_memory,
1022                            MemoryRegion **ram_memory)
1023 {
1024     int linux_boot, i;
1025     MemoryRegion *ram, *option_rom_mr;
1026     MemoryRegion *ram_below_4g, *ram_above_4g;
1027     FWCfgState *fw_cfg;
1028
1029     linux_boot = (kernel_filename != NULL);
1030
1031     /* Allocate RAM.  We allocate it as a single memory region and use
1032      * aliases to address portions of it, mostly for backwards compatibility
1033      * with older qemus that used qemu_ram_alloc().
1034      */
1035     ram = g_malloc(sizeof(*ram));
1036     memory_region_init_ram(ram, "pc.ram",
1037                            below_4g_mem_size + above_4g_mem_size);
1038     vmstate_register_ram_global(ram);
1039     *ram_memory = ram;
1040     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1041     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
1042                              0, below_4g_mem_size);
1043     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1044     if (above_4g_mem_size > 0) {
1045         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1046         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1047                                  below_4g_mem_size, above_4g_mem_size);
1048         memory_region_add_subregion(system_memory, 0x100000000ULL,
1049                                     ram_above_4g);
1050     }
1051
1052
1053     /* Initialize PC system firmware */
1054     pc_system_firmware_init(rom_memory);
1055
1056     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1057     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
1058     vmstate_register_ram_global(option_rom_mr);
1059     memory_region_add_subregion_overlap(rom_memory,
1060                                         PC_ROM_MIN_VGA,
1061                                         option_rom_mr,
1062                                         1);
1063
1064     fw_cfg = bochs_bios_init();
1065     rom_set_fw(fw_cfg);
1066
1067     if (linux_boot) {
1068         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1069     }
1070
1071     for (i = 0; i < nb_option_roms; i++) {
1072         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1073     }
1074     return fw_cfg;
1075 }
1076
1077 qemu_irq *pc_allocate_cpu_irq(void)
1078 {
1079     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1080 }
1081
1082 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1083 {
1084     DeviceState *dev = NULL;
1085
1086     if (pci_bus) {
1087         PCIDevice *pcidev = pci_vga_init(pci_bus);
1088         dev = pcidev ? &pcidev->qdev : NULL;
1089     } else if (isa_bus) {
1090         ISADevice *isadev = isa_vga_init(isa_bus);
1091         dev = isadev ? &isadev->qdev : NULL;
1092     }
1093     return dev;
1094 }
1095
1096 static void cpu_request_exit(void *opaque, int irq, int level)
1097 {
1098     CPUX86State *env = cpu_single_env;
1099
1100     if (env && level) {
1101         cpu_exit(env);
1102     }
1103 }
1104
1105 static const MemoryRegionOps ioport80_io_ops = {
1106     .write = ioport80_write,
1107     .read = ioport80_read,
1108     .endianness = DEVICE_NATIVE_ENDIAN,
1109     .impl = {
1110         .min_access_size = 1,
1111         .max_access_size = 1,
1112     },
1113 };
1114
1115 static const MemoryRegionOps ioportF0_io_ops = {
1116     .write = ioportF0_write,
1117     .read = ioportF0_read,
1118     .endianness = DEVICE_NATIVE_ENDIAN,
1119     .impl = {
1120         .min_access_size = 1,
1121         .max_access_size = 1,
1122     },
1123 };
1124
1125 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1126                           ISADevice **rtc_state,
1127                           ISADevice **floppy,
1128                           bool no_vmport)
1129 {
1130     int i;
1131     DriveInfo *fd[MAX_FD];
1132     DeviceState *hpet = NULL;
1133     int pit_isa_irq = 0;
1134     qemu_irq pit_alt_irq = NULL;
1135     qemu_irq rtc_irq = NULL;
1136     qemu_irq *a20_line;
1137     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1138     qemu_irq *cpu_exit_irq;
1139     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1140     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1141
1142     memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1);
1143     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1144
1145     memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1);
1146     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1147
1148     /*
1149      * Check if an HPET shall be created.
1150      *
1151      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1152      * when the HPET wants to take over. Thus we have to disable the latter.
1153      */
1154     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1155         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1156
1157         if (hpet) {
1158             for (i = 0; i < GSI_NUM_PINS; i++) {
1159                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1160             }
1161             pit_isa_irq = -1;
1162             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1163             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1164         }
1165     }
1166     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1167
1168     qemu_register_boot_set(pc_boot_set, *rtc_state);
1169
1170     if (!xen_enabled()) {
1171         if (kvm_irqchip_in_kernel()) {
1172             pit = kvm_pit_init(isa_bus, 0x40);
1173         } else {
1174             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1175         }
1176         if (hpet) {
1177             /* connect PIT to output control line of the HPET */
1178             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1179         }
1180         pcspk_init(isa_bus, pit);
1181     }
1182
1183     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1184         if (serial_hds[i]) {
1185             serial_isa_init(isa_bus, i, serial_hds[i]);
1186         }
1187     }
1188
1189     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1190         if (parallel_hds[i]) {
1191             parallel_init(isa_bus, i, parallel_hds[i]);
1192         }
1193     }
1194
1195     a20_line = qemu_allocate_irqs(handle_a20_line_change,
1196                                   x86_env_get_cpu(first_cpu), 2);
1197     i8042 = isa_create_simple(isa_bus, "i8042");
1198     i8042_setup_a20_line(i8042, &a20_line[0]);
1199     if (!no_vmport) {
1200         vmport_init(isa_bus);
1201         vmmouse = isa_try_create(isa_bus, "vmmouse");
1202     } else {
1203         vmmouse = NULL;
1204     }
1205     if (vmmouse) {
1206         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1207         qdev_init_nofail(&vmmouse->qdev);
1208     }
1209     port92 = isa_create_simple(isa_bus, "port92");
1210     port92_init(port92, &a20_line[1]);
1211
1212     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1213     DMA_init(0, cpu_exit_irq);
1214
1215     for(i = 0; i < MAX_FD; i++) {
1216         fd[i] = drive_get(IF_FLOPPY, 0, i);
1217     }
1218     *floppy = fdctrl_init_isa(isa_bus, fd);
1219 }
1220
1221 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1222 {
1223     int i;
1224
1225     for (i = 0; i < nb_nics; i++) {
1226         NICInfo *nd = &nd_table[i];
1227
1228         if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1229             pc_init_ne2k_isa(isa_bus, nd);
1230         } else {
1231             pci_nic_init_nofail(nd, "e1000", NULL);
1232         }
1233     }
1234 }
1235
1236 void pc_pci_device_init(PCIBus *pci_bus)
1237 {
1238     int max_bus;
1239     int bus;
1240
1241     max_bus = drive_get_max_bus(IF_SCSI);
1242     for (bus = 0; bus <= max_bus; bus++) {
1243         pci_create_simple(pci_bus, -1, "lsi53c895a");
1244     }
1245 }
1246
1247 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1248 {
1249     DeviceState *dev;
1250     SysBusDevice *d;
1251     unsigned int i;
1252
1253     if (kvm_irqchip_in_kernel()) {
1254         dev = qdev_create(NULL, "kvm-ioapic");
1255     } else {
1256         dev = qdev_create(NULL, "ioapic");
1257     }
1258     if (parent_name) {
1259         object_property_add_child(object_resolve_path(parent_name, NULL),
1260                                   "ioapic", OBJECT(dev), NULL);
1261     }
1262     qdev_init_nofail(dev);
1263     d = SYS_BUS_DEVICE(dev);
1264     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1265
1266     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1267         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1268     }
1269 }