hw/i386/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/i386/pc.h"
  26 #include "hw/char/serial.h"
  27 #include "hw/i386/apic.h"
  28 #include "hw/block/fdc.h"
  29 #include "hw/ide.h"
  30 #include "hw/pci/pci.h"
  31 #include "monitor/monitor.h"
  32 #include "hw/nvram/fw_cfg.h"
  33 #include "hw/timer/hpet.h"
  34 #include "hw/i386/smbios.h"
  35 #include "hw/loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "hw/timer/mc146818rtc.h"
  39 #include "hw/timer/i8254.h"
  40 #include "hw/audio/pcspk.h"
  41 #include "hw/pci/msi.h"
  42 #include "hw/sysbus.h"
  43 #include "sysemu/sysemu.h"
  44 #include "sysemu/kvm.h"
  45 #include "kvm_i386.h"
  46 #include "hw/xen/xen.h"
  47 #include "sysemu/blockdev.h"
  48 #include "hw/block/block.h"
  49 #include "ui/qemu-spice.h"
  50 #include "exec/memory.h"
  51 #include "exec/address-spaces.h"
  52 #include "sysemu/arch_init.h"
  53 #include "qemu/bitmap.h"
  54 #include "qemu/config-file.h"
  55 #include "hw/acpi/acpi.h"
  56
  57 /* debug PC/ISA interrupts */
  58 //#define DEBUG_IRQ
  59
  60 #ifdef DEBUG_IRQ
  61 #define DPRINTF(fmt, ...)                                       \
  62     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  63 #else
  64 #define DPRINTF(fmt, ...)
  65 #endif
  66
  67 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  68 #define ACPI_DATA_SIZE       0x10000
  69 #define BIOS_CFG_IOPORT 0x510
  70 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  71 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  72 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  73 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  74 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  75
  76 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000
  77
  78 #define E820_NR_ENTRIES         16
  79
  80 struct e820_entry {
  81     uint64_t address;
  82     uint64_t length;
  83     uint32_t type;
  84 } QEMU_PACKED __attribute((__aligned__(4)));
  85
  86 struct e820_table {
  87     uint32_t count;
  88     struct e820_entry entry[E820_NR_ENTRIES];
  89 } QEMU_PACKED __attribute((__aligned__(4)));
  90
  91 static struct e820_table e820_table;
  92 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  93
  94 void gsi_handler(void *opaque, int n, int level)
  95 {
  96     GSIState *s = opaque;
  97
  98     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  99     if (n < ISA_NUM_IRQS) {
 100         qemu_set_irq(s->i8259_irq[n], level);
 101     }
 102     qemu_set_irq(s->ioapic_irq[n], level);
 103 }
 104
 105 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
 106                            unsigned size)
 107 {
 108 }
 109
 110 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
 111 {
 112     return 0xffffffffffffffffULL;
 113 }
 114
 115 /* MSDOS compatibility mode FPU exception support */
 116 static qemu_irq ferr_irq;
 117
 118 void pc_register_ferr_irq(qemu_irq irq)
 119 {
 120     ferr_irq = irq;
 121 }
 122
 123 /* XXX: add IGNNE support */
 124 void cpu_set_ferr(CPUX86State *s)
 125 {
 126     qemu_irq_raise(ferr_irq);
 127 }
 128
 129 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
 130                            unsigned size)
 131 {
 132     qemu_irq_lower(ferr_irq);
 133 }
 134
 135 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
 136 {
 137     return 0xffffffffffffffffULL;
 138 }
 139
 140 /* TSC handling */
 141 uint64_t cpu_get_tsc(CPUX86State *env)
 142 {
 143     return cpu_get_ticks();
 144 }
 145
 146 /* SMM support */
 147
 148 static cpu_set_smm_t smm_set;
 149 static void *smm_arg;
 150
 151 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 152 {
 153     assert(smm_set == NULL);
 154     assert(smm_arg == NULL);
 155     smm_set = callback;
 156     smm_arg = arg;
 157 }
 158
 159 void cpu_smm_update(CPUX86State *env)
 160 {
 161     if (smm_set && smm_arg && env == first_cpu)
 162         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 163 }
 164
 165
 166 /* IRQ handling */
 167 int cpu_get_pic_interrupt(CPUX86State *env)
 168 {
 169     int intno;
 170
 171     intno = apic_get_interrupt(env->apic_state);
 172     if (intno >= 0) {
 173         return intno;
 174     }
 175     /* read the irq from the PIC */
 176     if (!apic_accept_pic_intr(env->apic_state)) {
 177         return -1;
 178     }
 179
 180     intno = pic_read_irq(isa_pic);
 181     return intno;
 182 }
 183
 184 static void pic_irq_request(void *opaque, int irq, int level)
 185 {
 186     CPUX86State *env = first_cpu;
 187
 188     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 189     if (env->apic_state) {
 190         while (env) {
 191             if (apic_accept_pic_intr(env->apic_state)) {
 192                 apic_deliver_pic_intr(env->apic_state, level);
 193             }
 194             env = env->next_cpu;
 195         }
 196     } else {
 197         CPUState *cs = CPU(x86_env_get_cpu(env));
 198         if (level) {
 199             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 200         } else {
 201             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 202         }
 203     }
 204 }
 205
 206 /* PC cmos mappings */
 207
 208 #define REG_EQUIPMENT_BYTE          0x14
 209
 210 static int cmos_get_fd_drive_type(FDriveType fd0)
 211 {
 212     int val;
 213
 214     switch (fd0) {
 215     case FDRIVE_DRV_144:
 216         /* 1.44 Mb 3"5 drive */
 217         val = 4;
 218         break;
 219     case FDRIVE_DRV_288:
 220         /* 2.88 Mb 3"5 drive */
 221         val = 5;
 222         break;
 223     case FDRIVE_DRV_120:
 224         /* 1.2 Mb 5"5 drive */
 225         val = 2;
 226         break;
 227     case FDRIVE_DRV_NONE:
 228     default:
 229         val = 0;
 230         break;
 231     }
 232     return val;
 233 }
 234
 235 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 236                          int16_t cylinders, int8_t heads, int8_t sectors)
 237 {
 238     rtc_set_memory(s, type_ofs, 47);
 239     rtc_set_memory(s, info_ofs, cylinders);
 240     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 241     rtc_set_memory(s, info_ofs + 2, heads);
 242     rtc_set_memory(s, info_ofs + 3, 0xff);
 243     rtc_set_memory(s, info_ofs + 4, 0xff);
 244     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 245     rtc_set_memory(s, info_ofs + 6, cylinders);
 246     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 247     rtc_set_memory(s, info_ofs + 8, sectors);
 248 }
 249
 250 /* convert boot_device letter to something recognizable by the bios */
 251 static int boot_device2nibble(char boot_device)
 252 {
 253     switch(boot_device) {
 254     case 'a':
 255     case 'b':
 256         return 0x01; /* floppy boot */
 257     case 'c':
 258         return 0x02; /* hard drive boot */
 259     case 'd':
 260         return 0x03; /* CD-ROM boot */
 261     case 'n':
 262         return 0x04; /* Network boot */
 263     }
 264     return 0;
 265 }
 266
 267 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 268 {
 269 #define PC_MAX_BOOT_DEVICES 3
 270     int nbds, bds[3] = { 0, };
 271     int i;
 272
 273     nbds = strlen(boot_device);
 274     if (nbds > PC_MAX_BOOT_DEVICES) {
 275         error_report("Too many boot devices for PC");
 276         return(1);
 277     }
 278     for (i = 0; i < nbds; i++) {
 279         bds[i] = boot_device2nibble(boot_device[i]);
 280         if (bds[i] == 0) {
 281             error_report("Invalid boot device for PC: '%c'",
 282                          boot_device[i]);
 283             return(1);
 284         }
 285     }
 286     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 287     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 288     return(0);
 289 }
 290
 291 static int pc_boot_set(void *opaque, const char *boot_device)
 292 {
 293     return set_boot_dev(opaque, boot_device, 0);
 294 }
 295
 296 typedef struct pc_cmos_init_late_arg {
 297     ISADevice *rtc_state;
 298     BusState *idebus[2];
 299 } pc_cmos_init_late_arg;
 300
 301 static void pc_cmos_init_late(void *opaque)
 302 {
 303     pc_cmos_init_late_arg *arg = opaque;
 304     ISADevice *s = arg->rtc_state;
 305     int16_t cylinders;
 306     int8_t heads, sectors;
 307     int val;
 308     int i, trans;
 309
 310     val = 0;
 311     if (ide_get_geometry(arg->idebus[0], 0,
 312                          &cylinders, &heads, &sectors) >= 0) {
 313         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 314         val |= 0xf0;
 315     }
 316     if (ide_get_geometry(arg->idebus[0], 1,
 317                          &cylinders, &heads, &sectors) >= 0) {
 318         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 319         val |= 0x0f;
 320     }
 321     rtc_set_memory(s, 0x12, val);
 322
 323     val = 0;
 324     for (i = 0; i < 4; i++) {
 325         /* NOTE: ide_get_geometry() returns the physical
 326            geometry.  It is always such that: 1 <= sects <= 63, 1
 327            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 328            geometry can be different if a translation is done. */
 329         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 330                              &cylinders, &heads, &sectors) >= 0) {
 331             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 332             assert((trans & ~3) == 0);
 333             val |= trans << (i * 2);
 334         }
 335     }
 336     rtc_set_memory(s, 0x39, val);
 337
 338     qemu_unregister_reset(pc_cmos_init_late, opaque);
 339 }
 340
 341 typedef struct RTCCPUHotplugArg {
 342     Notifier cpu_added_notifier;
 343     ISADevice *rtc_state;
 344 } RTCCPUHotplugArg;
 345
 346 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
 347 {
 348     RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
 349                                          cpu_added_notifier);
 350     ISADevice *s = arg->rtc_state;
 351
 352     /* increment the number of CPUs */
 353     rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
 354 }
 355
 356 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 357                   const char *boot_device,
 358                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 359                   ISADevice *s)
 360 {
 361     int val, nb, i;
 362     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 363     static pc_cmos_init_late_arg arg;
 364     static RTCCPUHotplugArg cpu_hotplug_cb;
 365
 366     /* various important CMOS locations needed by PC/Bochs bios */
 367
 368     /* memory size */
 369     /* base memory (first MiB) */
 370     val = MIN(ram_size / 1024, 640);
 371     rtc_set_memory(s, 0x15, val);
 372     rtc_set_memory(s, 0x16, val >> 8);
 373     /* extended memory (next 64MiB) */
 374     if (ram_size > 1024 * 1024) {
 375         val = (ram_size - 1024 * 1024) / 1024;
 376     } else {
 377         val = 0;
 378     }
 379     if (val > 65535)
 380         val = 65535;
 381     rtc_set_memory(s, 0x17, val);
 382     rtc_set_memory(s, 0x18, val >> 8);
 383     rtc_set_memory(s, 0x30, val);
 384     rtc_set_memory(s, 0x31, val >> 8);
 385     /* memory between 16MiB and 4GiB */
 386     if (ram_size > 16 * 1024 * 1024) {
 387         val = (ram_size - 16 * 1024 * 1024) / 65536;
 388     } else {
 389         val = 0;
 390     }
 391     if (val > 65535)
 392         val = 65535;
 393     rtc_set_memory(s, 0x34, val);
 394     rtc_set_memory(s, 0x35, val >> 8);
 395     /* memory above 4GiB */
 396     val = above_4g_mem_size / 65536;
 397     rtc_set_memory(s, 0x5b, val);
 398     rtc_set_memory(s, 0x5c, val >> 8);
 399     rtc_set_memory(s, 0x5d, val >> 16);
 400
 401     /* set the number of CPU */
 402     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 403     /* init CPU hotplug notifier */
 404     cpu_hotplug_cb.rtc_state = s;
 405     cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
 406     qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
 407
 408     /* set boot devices, and disable floppy signature check if requested */
 409     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 410         exit(1);
 411     }
 412
 413     /* floppy type */
 414     if (floppy) {
 415         for (i = 0; i < 2; i++) {
 416             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 417         }
 418     }
 419     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 420         cmos_get_fd_drive_type(fd_type[1]);
 421     rtc_set_memory(s, 0x10, val);
 422
 423     val = 0;
 424     nb = 0;
 425     if (fd_type[0] < FDRIVE_DRV_NONE) {
 426         nb++;
 427     }
 428     if (fd_type[1] < FDRIVE_DRV_NONE) {
 429         nb++;
 430     }
 431     switch (nb) {
 432     case 0:
 433         break;
 434     case 1:
 435         val |= 0x01; /* 1 drive, ready for boot */
 436         break;
 437     case 2:
 438         val |= 0x41; /* 2 drives, ready for boot */
 439         break;
 440     }
 441     val |= 0x02; /* FPU is there */
 442     val |= 0x04; /* PS/2 mouse installed */
 443     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 444
 445     /* hard drives */
 446     arg.rtc_state = s;
 447     arg.idebus[0] = idebus0;
 448     arg.idebus[1] = idebus1;
 449     qemu_register_reset(pc_cmos_init_late, &arg);
 450 }
 451
 452 #define TYPE_PORT92 "port92"
 453 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
 454
 455 /* port 92 stuff: could be split off */
 456 typedef struct Port92State {
 457     ISADevice parent_obj;
 458
 459     MemoryRegion io;
 460     uint8_t outport;
 461     qemu_irq *a20_out;
 462 } Port92State;
 463
 464 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 465                          unsigned size)
 466 {
 467     Port92State *s = opaque;
 468
 469     DPRINTF("port92: write 0x%02x\n", val);
 470     s->outport = val;
 471     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 472     if (val & 1) {
 473         qemu_system_reset_request();
 474     }
 475 }
 476
 477 static uint64_t port92_read(void *opaque, hwaddr addr,
 478                             unsigned size)
 479 {
 480     Port92State *s = opaque;
 481     uint32_t ret;
 482
 483     ret = s->outport;
 484     DPRINTF("port92: read 0x%02x\n", ret);
 485     return ret;
 486 }
 487
 488 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 489 {
 490     Port92State *s = PORT92(dev);
 491
 492     s->a20_out = a20_out;
 493 }
 494
 495 static const VMStateDescription vmstate_port92_isa = {
 496     .name = "port92",
 497     .version_id = 1,
 498     .minimum_version_id = 1,
 499     .minimum_version_id_old = 1,
 500     .fields      = (VMStateField []) {
 501         VMSTATE_UINT8(outport, Port92State),
 502         VMSTATE_END_OF_LIST()
 503     }
 504 };
 505
 506 static void port92_reset(DeviceState *d)
 507 {
 508     Port92State *s = PORT92(d);
 509
 510     s->outport &= ~1;
 511 }
 512
 513 static const MemoryRegionOps port92_ops = {
 514     .read = port92_read,
 515     .write = port92_write,
 516     .impl = {
 517         .min_access_size = 1,
 518         .max_access_size = 1,
 519     },
 520     .endianness = DEVICE_LITTLE_ENDIAN,
 521 };
 522
 523 static int port92_initfn(ISADevice *dev)
 524 {
 525     Port92State *s = PORT92(dev);
 526
 527     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 528     isa_register_ioport(dev, &s->io, 0x92);
 529
 530     s->outport = 0;
 531     return 0;
 532 }
 533
 534 static void port92_class_initfn(ObjectClass *klass, void *data)
 535 {
 536     DeviceClass *dc = DEVICE_CLASS(klass);
 537     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 538     ic->init = port92_initfn;
 539     dc->no_user = 1;
 540     dc->reset = port92_reset;
 541     dc->vmsd = &vmstate_port92_isa;
 542 }
 543
 544 static const TypeInfo port92_info = {
 545     .name          = TYPE_PORT92,
 546     .parent        = TYPE_ISA_DEVICE,
 547     .instance_size = sizeof(Port92State),
 548     .class_init    = port92_class_initfn,
 549 };
 550
 551 static void port92_register_types(void)
 552 {
 553     type_register_static(&port92_info);
 554 }
 555
 556 type_init(port92_register_types)
 557
 558 static void handle_a20_line_change(void *opaque, int irq, int level)
 559 {
 560     X86CPU *cpu = opaque;
 561
 562     /* XXX: send to all CPUs ? */
 563     /* XXX: add logic to handle multiple A20 line sources */
 564     x86_cpu_set_a20(cpu, level);
 565 }
 566
 567 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 568 {
 569     int index = le32_to_cpu(e820_table.count);
 570     struct e820_entry *entry;
 571
 572     if (index >= E820_NR_ENTRIES)
 573         return -EBUSY;
 574     entry = &e820_table.entry[index++];
 575
 576     entry->address = cpu_to_le64(address);
 577     entry->length = cpu_to_le64(length);
 578     entry->type = cpu_to_le32(type);
 579
 580     e820_table.count = cpu_to_le32(index);
 581     return index;
 582 }
 583
 584 /* Calculates the limit to CPU APIC ID values
 585  *
 586  * This function returns the limit for the APIC ID value, so that all
 587  * CPU APIC IDs are < pc_apic_id_limit().
 588  *
 589  * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
 590  */
 591 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
 592 {
 593     return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
 594 }
 595
 596 static void *bochs_bios_init(void)
 597 {
 598     void *fw_cfg;
 599     uint8_t *smbios_table;
 600     size_t smbios_len;
 601     uint64_t *numa_fw_cfg;
 602     int i, j;
 603     unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
 604
 605     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 606     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 607      *
 608      * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
 609      * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
 610      * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
 611      * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
 612      * may see".
 613      *
 614      * So, this means we must not use max_cpus, here, but the maximum possible
 615      * APIC ID value, plus one.
 616      *
 617      * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
 618      *     the APIC ID, not the "CPU index"
 619      */
 620     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
 621     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 622     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 623     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 624                      acpi_tables, acpi_tables_len);
 625     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 626
 627     smbios_table = smbios_get_table(&smbios_len);
 628     if (smbios_table)
 629         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 630                          smbios_table, smbios_len);
 631     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 632                      &e820_table, sizeof(e820_table));
 633
 634     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 635     /* allocate memory for the NUMA channel: one (64bit) word for the number
 636      * of nodes, one word for each VCPU->node and one word for each node to
 637      * hold the amount of memory.
 638      */
 639     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 640     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 641     for (i = 0; i < max_cpus; i++) {
 642         unsigned int apic_id = x86_cpu_apic_id_from_index(i);
 643         assert(apic_id < apic_id_limit);
 644         for (j = 0; j < nb_numa_nodes; j++) {
 645             if (test_bit(i, node_cpumask[j])) {
 646                 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
 647                 break;
 648             }
 649         }
 650     }
 651     for (i = 0; i < nb_numa_nodes; i++) {
 652         numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
 653     }
 654     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 655                      (1 + apic_id_limit + nb_numa_nodes) *
 656                      sizeof(*numa_fw_cfg));
 657
 658     return fw_cfg;
 659 }
 660
 661 static long get_file_size(FILE *f)
 662 {
 663     long where, size;
 664
 665     /* XXX: on Unix systems, using fstat() probably makes more sense */
 666
 667     where = ftell(f);
 668     fseek(f, 0, SEEK_END);
 669     size = ftell(f);
 670     fseek(f, where, SEEK_SET);
 671
 672     return size;
 673 }
 674
 675 static void load_linux(void *fw_cfg,
 676                        const char *kernel_filename,
 677                        const char *initrd_filename,
 678                        const char *kernel_cmdline,
 679                        hwaddr max_ram_size)
 680 {
 681     uint16_t protocol;
 682     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 683     uint32_t initrd_max;
 684     uint8_t header[8192], *setup, *kernel, *initrd_data;
 685     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 686     FILE *f;
 687     char *vmode;
 688
 689     /* Align to 16 bytes as a paranoia measure */
 690     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 691
 692     /* load the kernel header */
 693     f = fopen(kernel_filename, "rb");
 694     if (!f || !(kernel_size = get_file_size(f)) ||
 695         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 696         MIN(ARRAY_SIZE(header), kernel_size)) {
 697         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 698                 kernel_filename, strerror(errno));
 699         exit(1);
 700     }
 701
 702     /* kernel protocol version */
 703 #if 0
 704     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 705 #endif
 706     if (ldl_p(header+0x202) == 0x53726448) {
 707         protocol = lduw_p(header+0x206);
 708     } else {
 709         /* This looks like a multiboot kernel. If it is, let's stop
 710            treating it like a Linux kernel. */
 711         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 712                            kernel_cmdline, kernel_size, header)) {
 713             return;
 714         }
 715         protocol = 0;
 716     }
 717
 718     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 719         /* Low kernel */
 720         real_addr    = 0x90000;
 721         cmdline_addr = 0x9a000 - cmdline_size;
 722         prot_addr    = 0x10000;
 723     } else if (protocol < 0x202) {
 724         /* High but ancient kernel */
 725         real_addr    = 0x90000;
 726         cmdline_addr = 0x9a000 - cmdline_size;
 727         prot_addr    = 0x100000;
 728     } else {
 729         /* High and recent kernel */
 730         real_addr    = 0x10000;
 731         cmdline_addr = 0x20000;
 732         prot_addr    = 0x100000;
 733     }
 734
 735 #if 0
 736     fprintf(stderr,
 737             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 738             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 739             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 740             real_addr,
 741             cmdline_addr,
 742             prot_addr);
 743 #endif
 744
 745     /* highest address for loading the initrd */
 746     if (protocol >= 0x203) {
 747         initrd_max = ldl_p(header+0x22c);
 748     } else {
 749         initrd_max = 0x37ffffff;
 750     }
 751
 752     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 753         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 754
 755     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 756     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 757     fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
 758
 759     if (protocol >= 0x202) {
 760         stl_p(header+0x228, cmdline_addr);
 761     } else {
 762         stw_p(header+0x20, 0xA33F);
 763         stw_p(header+0x22, cmdline_addr-real_addr);
 764     }
 765
 766     /* handle vga= parameter */
 767     vmode = strstr(kernel_cmdline, "vga=");
 768     if (vmode) {
 769         unsigned int video_mode;
 770         /* skip "vga=" */
 771         vmode += 4;
 772         if (!strncmp(vmode, "normal", 6)) {
 773             video_mode = 0xffff;
 774         } else if (!strncmp(vmode, "ext", 3)) {
 775             video_mode = 0xfffe;
 776         } else if (!strncmp(vmode, "ask", 3)) {
 777             video_mode = 0xfffd;
 778         } else {
 779             video_mode = strtol(vmode, NULL, 0);
 780         }
 781         stw_p(header+0x1fa, video_mode);
 782     }
 783
 784     /* loader type */
 785     /* High nybble = B reserved for QEMU; low nybble is revision number.
 786        If this code is substantially changed, you may want to consider
 787        incrementing the revision. */
 788     if (protocol >= 0x200) {
 789         header[0x210] = 0xB0;
 790     }
 791     /* heap */
 792     if (protocol >= 0x201) {
 793         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 794         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 795     }
 796
 797     /* load initrd */
 798     if (initrd_filename) {
 799         if (protocol < 0x200) {
 800             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 801             exit(1);
 802         }
 803
 804         initrd_size = get_image_size(initrd_filename);
 805         if (initrd_size < 0) {
 806             fprintf(stderr, "qemu: error reading initrd %s\n",
 807                     initrd_filename);
 808             exit(1);
 809         }
 810
 811         initrd_addr = (initrd_max-initrd_size) & ~4095;
 812
 813         initrd_data = g_malloc(initrd_size);
 814         load_image(initrd_filename, initrd_data);
 815
 816         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 817         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 818         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 819
 820         stl_p(header+0x218, initrd_addr);
 821         stl_p(header+0x21c, initrd_size);
 822     }
 823
 824     /* load kernel and setup */
 825     setup_size = header[0x1f1];
 826     if (setup_size == 0) {
 827         setup_size = 4;
 828     }
 829     setup_size = (setup_size+1)*512;
 830     kernel_size -= setup_size;
 831
 832     setup  = g_malloc(setup_size);
 833     kernel = g_malloc(kernel_size);
 834     fseek(f, 0, SEEK_SET);
 835     if (fread(setup, 1, setup_size, f) != setup_size) {
 836         fprintf(stderr, "fread() failed\n");
 837         exit(1);
 838     }
 839     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 840         fprintf(stderr, "fread() failed\n");
 841         exit(1);
 842     }
 843     fclose(f);
 844     memcpy(setup, header, MIN(sizeof(header), setup_size));
 845
 846     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 847     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 848     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 849
 850     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 851     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 852     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 853
 854     option_rom[nb_option_roms].name = "linuxboot.bin";
 855     option_rom[nb_option_roms].bootindex = 0;
 856     nb_option_roms++;
 857 }
 858
 859 #define NE2000_NB_MAX 6
 860
 861 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 862                                               0x280, 0x380 };
 863 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 864
 865 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 866 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 867
 868 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 869 {
 870     static int nb_ne2k = 0;
 871
 872     if (nb_ne2k == NE2000_NB_MAX)
 873         return;
 874     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 875                     ne2000_irq[nb_ne2k], nd);
 876     nb_ne2k++;
 877 }
 878
 879 DeviceState *cpu_get_current_apic(void)
 880 {
 881     if (cpu_single_env) {
 882         return cpu_single_env->apic_state;
 883     } else {
 884         return NULL;
 885     }
 886 }
 887
 888 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 889 {
 890     X86CPU *cpu = opaque;
 891
 892     if (level) {
 893         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
 894     }
 895 }
 896
 897 void pc_cpus_init(const char *cpu_model)
 898 {
 899     int i;
 900
 901     /* init CPUs */
 902     if (cpu_model == NULL) {
 903 #ifdef TARGET_X86_64
 904         cpu_model = "qemu64";
 905 #else
 906         cpu_model = "qemu32";
 907 #endif
 908     }
 909
 910     for (i = 0; i < smp_cpus; i++) {
 911         if (!cpu_x86_init(cpu_model)) {
 912             exit(1);
 913         }
 914     }
 915 }
 916
 917 void pc_acpi_init(const char *default_dsdt)
 918 {
 919     char *filename;
 920
 921     if (acpi_tables != NULL) {
 922         /* manually set via -acpitable, leave it alone */
 923         return;
 924     }
 925
 926     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
 927     if (filename == NULL) {
 928         fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
 929     } else {
 930         char *arg;
 931         QemuOpts *opts;
 932         Error *err = NULL;
 933
 934         arg = g_strdup_printf("file=%s", filename);
 935
 936         /* creates a deep copy of "arg" */
 937         opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
 938         g_assert(opts != NULL);
 939
 940         acpi_table_add(opts, &err);
 941         if (err) {
 942             fprintf(stderr, "WARNING: failed to load %s: %s\n", filename,
 943                     error_get_pretty(err));
 944             error_free(err);
 945         }
 946         g_free(arg);
 947         g_free(filename);
 948     }
 949 }
 950
 951 void *pc_memory_init(MemoryRegion *system_memory,
 952                     const char *kernel_filename,
 953                     const char *kernel_cmdline,
 954                     const char *initrd_filename,
 955                     ram_addr_t below_4g_mem_size,
 956                     ram_addr_t above_4g_mem_size,
 957                     MemoryRegion *rom_memory,
 958                     MemoryRegion **ram_memory)
 959 {
 960     int linux_boot, i;
 961     MemoryRegion *ram, *option_rom_mr;
 962     MemoryRegion *ram_below_4g, *ram_above_4g;
 963     void *fw_cfg;
 964
 965     linux_boot = (kernel_filename != NULL);
 966
 967     /* Allocate RAM.  We allocate it as a single memory region and use
 968      * aliases to address portions of it, mostly for backwards compatibility
 969      * with older qemus that used qemu_ram_alloc().
 970      */
 971     ram = g_malloc(sizeof(*ram));
 972     memory_region_init_ram(ram, "pc.ram",
 973                            below_4g_mem_size + above_4g_mem_size);
 974     vmstate_register_ram_global(ram);
 975     *ram_memory = ram;
 976     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 977     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 978                              0, below_4g_mem_size);
 979     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 980     if (above_4g_mem_size > 0) {
 981         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
 982         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
 983                                  below_4g_mem_size, above_4g_mem_size);
 984         memory_region_add_subregion(system_memory, 0x100000000ULL,
 985                                     ram_above_4g);
 986     }
 987
 988
 989     /* Initialize PC system firmware */
 990     pc_system_firmware_init(rom_memory);
 991
 992     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
 993     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
 994     vmstate_register_ram_global(option_rom_mr);
 995     memory_region_add_subregion_overlap(rom_memory,
 996                                         PC_ROM_MIN_VGA,
 997                                         option_rom_mr,
 998                                         1);
 999
1000     fw_cfg = bochs_bios_init();
1001     rom_set_fw(fw_cfg);
1002
1003     if (linux_boot) {
1004         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1005     }
1006
1007     for (i = 0; i < nb_option_roms; i++) {
1008         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1009     }
1010     return fw_cfg;
1011 }
1012
1013 qemu_irq *pc_allocate_cpu_irq(void)
1014 {
1015     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1016 }
1017
1018 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1019 {
1020     DeviceState *dev = NULL;
1021
1022     if (pci_bus) {
1023         PCIDevice *pcidev = pci_vga_init(pci_bus);
1024         dev = pcidev ? &pcidev->qdev : NULL;
1025     } else if (isa_bus) {
1026         ISADevice *isadev = isa_vga_init(isa_bus);
1027         dev = isadev ? &isadev->qdev : NULL;
1028     }
1029     return dev;
1030 }
1031
1032 static void cpu_request_exit(void *opaque, int irq, int level)
1033 {
1034     CPUX86State *env = cpu_single_env;
1035
1036     if (env && level) {
1037         cpu_exit(env);
1038     }
1039 }
1040
1041 static const MemoryRegionOps ioport80_io_ops = {
1042     .write = ioport80_write,
1043     .read = ioport80_read,
1044     .endianness = DEVICE_NATIVE_ENDIAN,
1045     .impl = {
1046         .min_access_size = 1,
1047         .max_access_size = 1,
1048     },
1049 };
1050
1051 static const MemoryRegionOps ioportF0_io_ops = {
1052     .write = ioportF0_write,
1053     .read = ioportF0_read,
1054     .endianness = DEVICE_NATIVE_ENDIAN,
1055     .impl = {
1056         .min_access_size = 1,
1057         .max_access_size = 1,
1058     },
1059 };
1060
1061 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1062                           ISADevice **rtc_state,
1063                           ISADevice **floppy,
1064                           bool no_vmport)
1065 {
1066     int i;
1067     DriveInfo *fd[MAX_FD];
1068     DeviceState *hpet = NULL;
1069     int pit_isa_irq = 0;
1070     qemu_irq pit_alt_irq = NULL;
1071     qemu_irq rtc_irq = NULL;
1072     qemu_irq *a20_line;
1073     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1074     qemu_irq *cpu_exit_irq;
1075     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1076     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1077
1078     memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1);
1079     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1080
1081     memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1);
1082     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1083
1084     /*
1085      * Check if an HPET shall be created.
1086      *
1087      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1088      * when the HPET wants to take over. Thus we have to disable the latter.
1089      */
1090     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1091         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1092
1093         if (hpet) {
1094             for (i = 0; i < GSI_NUM_PINS; i++) {
1095                 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1096             }
1097             pit_isa_irq = -1;
1098             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1099             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1100         }
1101     }
1102     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1103
1104     qemu_register_boot_set(pc_boot_set, *rtc_state);
1105
1106     if (!xen_enabled()) {
1107         if (kvm_irqchip_in_kernel()) {
1108             pit = kvm_pit_init(isa_bus, 0x40);
1109         } else {
1110             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1111         }
1112         if (hpet) {
1113             /* connect PIT to output control line of the HPET */
1114             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1115         }
1116         pcspk_init(isa_bus, pit);
1117     }
1118
1119     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1120         if (serial_hds[i]) {
1121             serial_isa_init(isa_bus, i, serial_hds[i]);
1122         }
1123     }
1124
1125     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1126         if (parallel_hds[i]) {
1127             parallel_init(isa_bus, i, parallel_hds[i]);
1128         }
1129     }
1130
1131     a20_line = qemu_allocate_irqs(handle_a20_line_change,
1132                                   x86_env_get_cpu(first_cpu), 2);
1133     i8042 = isa_create_simple(isa_bus, "i8042");
1134     i8042_setup_a20_line(i8042, &a20_line[0]);
1135     if (!no_vmport) {
1136         vmport_init(isa_bus);
1137         vmmouse = isa_try_create(isa_bus, "vmmouse");
1138     } else {
1139         vmmouse = NULL;
1140     }
1141     if (vmmouse) {
1142         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1143         qdev_init_nofail(&vmmouse->qdev);
1144     }
1145     port92 = isa_create_simple(isa_bus, "port92");
1146     port92_init(port92, &a20_line[1]);
1147
1148     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1149     DMA_init(0, cpu_exit_irq);
1150
1151     for(i = 0; i < MAX_FD; i++) {
1152         fd[i] = drive_get(IF_FLOPPY, 0, i);
1153     }
1154     *floppy = fdctrl_init_isa(isa_bus, fd);
1155 }
1156
1157 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1158 {
1159     int i;
1160
1161     for (i = 0; i < nb_nics; i++) {
1162         NICInfo *nd = &nd_table[i];
1163
1164         if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1165             pc_init_ne2k_isa(isa_bus, nd);
1166         } else {
1167             pci_nic_init_nofail(nd, "e1000", NULL);
1168         }
1169     }
1170 }
1171
1172 void pc_pci_device_init(PCIBus *pci_bus)
1173 {
1174     int max_bus;
1175     int bus;
1176
1177     max_bus = drive_get_max_bus(IF_SCSI);
1178     for (bus = 0; bus <= max_bus; bus++) {
1179         pci_create_simple(pci_bus, -1, "lsi53c895a");
1180     }
1181 }
1182
1183 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1184 {
1185     DeviceState *dev;
1186     SysBusDevice *d;
1187     unsigned int i;
1188
1189     if (kvm_irqchip_in_kernel()) {
1190         dev = qdev_create(NULL, "kvm-ioapic");
1191     } else {
1192         dev = qdev_create(NULL, "ioapic");
1193     }
1194     if (parent_name) {
1195         object_property_add_child(object_resolve_path(parent_name, NULL),
1196                                   "ioapic", OBJECT(dev), NULL);
1197     }
1198     qdev_init_nofail(dev);
1199     d = SYS_BUS_DEVICE(dev);
1200     sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1201
1202     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1203         gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
1204     }
1205 }