hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/loader.h"
  32 #include "sysemu/arch_init.h"
  33 #include "hw/i2c/smbus.h"
  34 #include "hw/boards.h"
  35 #include "hw/timer/mc146818rtc.h"
  36 #include "hw/xen/xen.h"
  37 #include "sysemu/kvm.h"
  38 #include "hw/kvm/clock.h"
  39 #include "hw/pci-host/q35.h"
  40 #include "exec/address-spaces.h"
  41 #include "hw/i386/ich9.h"
  42 #include "hw/ide/pci.h"
  43 #include "hw/ide/ahci.h"
  44 #include "hw/usb.h"
  45 #include "hw/cpu/icc_bus.h"
  46
  47 /* ICH9 AHCI has 6 ports */
  48 #define MAX_SATA_PORTS     6
  49
  50 static bool has_pvpanic;
  51 static bool has_pci_info = true;
  52
  53 /* PC hardware initialisation */
  54 static void pc_q35_init(QEMUMachineInitArgs *args)
  55 {
  56     ram_addr_t ram_size = args->ram_size;
  57     const char *cpu_model = args->cpu_model;
  58     const char *kernel_filename = args->kernel_filename;
  59     const char *kernel_cmdline = args->kernel_cmdline;
  60     const char *initrd_filename = args->initrd_filename;
  61     const char *boot_device = args->boot_device;
  62     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  63     Q35PCIHost *q35_host;
  64     PCIHostState *phb;
  65     PCIBus *host_bus;
  66     PCIDevice *lpc;
  67     BusState *idebus[MAX_SATA_PORTS];
  68     ISADevice *rtc_state;
  69     ISADevice *floppy;
  70     MemoryRegion *pci_memory;
  71     MemoryRegion *rom_memory;
  72     MemoryRegion *ram_memory;
  73     GSIState *gsi_state;
  74     ISABus *isa_bus;
  75     int pci_enabled = 1;
  76     qemu_irq *cpu_irq;
  77     qemu_irq *gsi;
  78     qemu_irq *i8259;
  79     int i;
  80     ICH9LPCState *ich9_lpc;
  81     PCIDevice *ahci;
  82     DeviceState *icc_bridge;
  83     PcGuestInfo *guest_info;
  84
  85     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
  86     object_property_add_child(qdev_get_machine(), "icc-bridge",
  87                               OBJECT(icc_bridge), NULL);
  88
  89     pc_cpus_init(cpu_model, icc_bridge);
  90     pc_acpi_init("q35-acpi-dsdt.aml");
  91
  92     kvmclock_create();
  93
  94     if (ram_size >= 0xb0000000) {
  95         above_4g_mem_size = ram_size - 0xb0000000;
  96         below_4g_mem_size = 0xb0000000;
  97     } else {
  98         above_4g_mem_size = 0;
  99         below_4g_mem_size = ram_size;
 100     }
 101
 102     /* pci enabled */
 103     if (pci_enabled) {
 104         pci_memory = g_new(MemoryRegion, 1);
 105         memory_region_init(pci_memory, NULL, "pci", INT64_MAX);
 106         rom_memory = pci_memory;
 107     } else {
 108         pci_memory = NULL;
 109         rom_memory = get_system_memory();
 110     }
 111
 112     guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
 113     guest_info->has_pci_info = has_pci_info;
 114     guest_info->isapc_ram_fw = false;
 115
 116     /* allocate ram and load rom/bios */
 117     if (!xen_enabled()) {
 118         pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
 119                        initrd_filename, below_4g_mem_size, above_4g_mem_size,
 120                        rom_memory, &ram_memory, guest_info);
 121     }
 122
 123     /* irq lines */
 124     gsi_state = g_malloc0(sizeof(*gsi_state));
 125     if (kvm_irqchip_in_kernel()) {
 126         kvm_pc_setup_irq_routing(pci_enabled);
 127         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 128                                  GSI_NUM_PINS);
 129     } else {
 130         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 131     }
 132
 133     /* create pci host bus */
 134     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 135
 136     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 137     q35_host->mch.ram_memory = ram_memory;
 138     q35_host->mch.pci_address_space = pci_memory;
 139     q35_host->mch.system_memory = get_system_memory();
 140     q35_host->mch.address_space_io = get_system_io();
 141     q35_host->mch.below_4g_mem_size = below_4g_mem_size;
 142     q35_host->mch.above_4g_mem_size = above_4g_mem_size;
 143     q35_host->mch.guest_info = guest_info;
 144     /* pci */
 145     qdev_init_nofail(DEVICE(q35_host));
 146     phb = PCI_HOST_BRIDGE(q35_host);
 147     host_bus = phb->bus;
 148     /* create ISA bus */
 149     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 150                                           ICH9_LPC_FUNC), true,
 151                                           TYPE_ICH9_LPC_DEVICE);
 152     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 153     ich9_lpc->pic = gsi;
 154     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 155     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 156                  ICH9_LPC_NB_PIRQS);
 157     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 158     isa_bus = ich9_lpc->isa_bus;
 159
 160     /*end early*/
 161     isa_bus_irqs(isa_bus, gsi);
 162
 163     if (kvm_irqchip_in_kernel()) {
 164         i8259 = kvm_i8259_init(isa_bus);
 165     } else if (xen_enabled()) {
 166         i8259 = xen_interrupt_controller_init();
 167     } else {
 168         cpu_irq = pc_allocate_cpu_irq();
 169         i8259 = i8259_init(isa_bus, cpu_irq[0]);
 170     }
 171
 172     for (i = 0; i < ISA_NUM_IRQS; i++) {
 173         gsi_state->i8259_irq[i] = i8259[i];
 174     }
 175     if (pci_enabled) {
 176         ioapic_init_gsi(gsi_state, NULL);
 177     }
 178     qdev_init_nofail(icc_bridge);
 179
 180     pc_register_ferr_irq(gsi[13]);
 181
 182     /* init basic PC hardware */
 183     pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
 184
 185     /* connect pm stuff to lpc */
 186     ich9_lpc_pm_init(lpc);
 187
 188     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 189     ahci = pci_create_simple_multifunction(host_bus,
 190                                            PCI_DEVFN(ICH9_SATA1_DEV,
 191                                                      ICH9_SATA1_FUNC),
 192                                            true, "ich9-ahci");
 193     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 194     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 195
 196     if (usb_enabled(false)) {
 197         /* Should we create 6 UHCI according to ich9 spec? */
 198         ehci_create_ich9_with_companions(host_bus, 0x1d);
 199     }
 200
 201     /* TODO: Populate SPD eeprom data.  */
 202     smbus_eeprom_init(ich9_smb_init(host_bus,
 203                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 204                                     0xb100),
 205                       8, NULL, 0);
 206
 207     pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
 208                  floppy, idebus[0], idebus[1], rtc_state);
 209
 210     /* the rest devices to which pci devfn is automatically assigned */
 211     pc_vga_init(isa_bus, host_bus);
 212     pc_nic_init(isa_bus, host_bus);
 213     if (pci_enabled) {
 214         pc_pci_device_init(host_bus);
 215     }
 216
 217     if (has_pvpanic) {
 218         pvpanic_init(isa_bus);
 219     }
 220 }
 221
 222 static void pc_q35_init_1_6(QEMUMachineInitArgs *args)
 223 {
 224     has_pci_info = false;
 225     rom_file_in_ram = false;
 226     pc_q35_init(args);
 227 }
 228
 229 static void pc_q35_init_1_5(QEMUMachineInitArgs *args)
 230 {
 231     has_pvpanic = true;
 232     pc_q35_init_1_6(args);
 233 }
 234
 235 static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
 236 {
 237     x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
 238     x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
 239     /* 1.5 was special - it enabled pvpanic in builtin machine */
 240     pc_q35_init_1_6(args);
 241 }
 242
 243 static QEMUMachine pc_q35_machine_v1_6 = {
 244     .name = "pc-q35-1.6",
 245     .alias = "q35",
 246     .desc = "Standard PC (Q35 + ICH9, 2009)",
 247     .init = pc_q35_init_1_6,
 248     .hot_add_cpu = pc_hot_add_cpu,
 249     .max_cpus = 255,
 250     DEFAULT_MACHINE_OPTIONS,
 251 };
 252
 253 static QEMUMachine pc_q35_machine_v1_5 = {
 254     .name = "pc-q35-1.5",
 255     .desc = "Standard PC (Q35 + ICH9, 2009)",
 256     .init = pc_q35_init_1_5,
 257     .hot_add_cpu = pc_hot_add_cpu,
 258     .max_cpus = 255,
 259     .compat_props = (GlobalProperty[]) {
 260         PC_COMPAT_1_5,
 261         { /* end of list */ }
 262     },
 263     DEFAULT_MACHINE_OPTIONS,
 264 };
 265
 266 static QEMUMachine pc_q35_machine_v1_4 = {
 267     .name = "pc-q35-1.4",
 268     .desc = "Standard PC (Q35 + ICH9, 2009)",
 269     .init = pc_q35_init_1_4,
 270     .max_cpus = 255,
 271     .compat_props = (GlobalProperty[]) {
 272         PC_COMPAT_1_4,
 273         { /* end of list */ }
 274     },
 275     DEFAULT_MACHINE_OPTIONS,
 276 };
 277
 278 static void pc_q35_machine_init(void)
 279 {
 280     qemu_register_machine(&pc_q35_machine_v1_6);
 281     qemu_register_machine(&pc_q35_machine_v1_5);
 282     qemu_register_machine(&pc_q35_machine_v1_4);
 283 }
 284
 285 machine_init(pc_q35_machine_init);