hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "sysemu/arch_init.h"
  32 #include "hw/i2c/smbus.h"
  33 #include "hw/boards.h"
  34 #include "hw/timer/mc146818rtc.h"
  35 #include "hw/xen/xen.h"
  36 #include "sysemu/kvm.h"
  37 #include "hw/kvm/clock.h"
  38 #include "hw/pci-host/q35.h"
  39 #include "exec/address-spaces.h"
  40 #include "hw/i386/ich9.h"
  41 #include "hw/ide/pci.h"
  42 #include "hw/ide/ahci.h"
  43 #include "hw/usb.h"
  44 #include "hw/cpu/icc_bus.h"
  45
  46 /* ICH9 AHCI has 6 ports */
  47 #define MAX_SATA_PORTS     6
  48
  49 static bool has_pvpanic = true;
  50
  51 /* PC hardware initialisation */
  52 static void pc_q35_init(QEMUMachineInitArgs *args)
  53 {
  54     ram_addr_t ram_size = args->ram_size;
  55     const char *cpu_model = args->cpu_model;
  56     const char *kernel_filename = args->kernel_filename;
  57     const char *kernel_cmdline = args->kernel_cmdline;
  58     const char *initrd_filename = args->initrd_filename;
  59     const char *boot_device = args->boot_device;
  60     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  61     Q35PCIHost *q35_host;
  62     PCIBus *host_bus;
  63     PCIDevice *lpc;
  64     BusState *idebus[MAX_SATA_PORTS];
  65     ISADevice *rtc_state;
  66     ISADevice *floppy;
  67     MemoryRegion *pci_memory;
  68     MemoryRegion *rom_memory;
  69     MemoryRegion *ram_memory;
  70     GSIState *gsi_state;
  71     ISABus *isa_bus;
  72     int pci_enabled = 1;
  73     qemu_irq *cpu_irq;
  74     qemu_irq *gsi;
  75     qemu_irq *i8259;
  76     int i;
  77     ICH9LPCState *ich9_lpc;
  78     PCIDevice *ahci;
  79     DeviceState *icc_bridge;
  80
  81     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
  82     object_property_add_child(qdev_get_machine(), "icc-bridge",
  83                               OBJECT(icc_bridge), NULL);
  84
  85     pc_cpus_init(cpu_model, icc_bridge);
  86     pc_acpi_init("q35-acpi-dsdt.aml");
  87
  88     kvmclock_create();
  89
  90     if (ram_size >= 0xb0000000) {
  91         above_4g_mem_size = ram_size - 0xb0000000;
  92         below_4g_mem_size = 0xb0000000;
  93     } else {
  94         above_4g_mem_size = 0;
  95         below_4g_mem_size = ram_size;
  96     }
  97
  98     /* pci enabled */
  99     if (pci_enabled) {
 100         pci_memory = g_new(MemoryRegion, 1);
 101         memory_region_init(pci_memory, "pci", INT64_MAX);
 102         rom_memory = pci_memory;
 103     } else {
 104         pci_memory = NULL;
 105         rom_memory = get_system_memory();
 106     }
 107
 108     /* allocate ram and load rom/bios */
 109     if (!xen_enabled()) {
 110         pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
 111                        initrd_filename, below_4g_mem_size, above_4g_mem_size,
 112                        rom_memory, &ram_memory);
 113     }
 114
 115     /* irq lines */
 116     gsi_state = g_malloc0(sizeof(*gsi_state));
 117     if (kvm_irqchip_in_kernel()) {
 118         kvm_pc_setup_irq_routing(pci_enabled);
 119         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 120                                  GSI_NUM_PINS);
 121     } else {
 122         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 123     }
 124
 125     /* create pci host bus */
 126     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 127
 128     q35_host->mch.ram_memory = ram_memory;
 129     q35_host->mch.pci_address_space = pci_memory;
 130     q35_host->mch.system_memory = get_system_memory();
 131     q35_host->mch.address_space_io = get_system_io();
 132     q35_host->mch.below_4g_mem_size = below_4g_mem_size;
 133     q35_host->mch.above_4g_mem_size = above_4g_mem_size;
 134     /* pci */
 135     qdev_init_nofail(DEVICE(q35_host));
 136     host_bus = q35_host->host.pci.bus;
 137     /* create ISA bus */
 138     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 139                                           ICH9_LPC_FUNC), true,
 140                                           TYPE_ICH9_LPC_DEVICE);
 141     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 142     ich9_lpc->pic = gsi;
 143     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 144     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 145                  ICH9_LPC_NB_PIRQS);
 146     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 147     isa_bus = ich9_lpc->isa_bus;
 148
 149     /*end early*/
 150     isa_bus_irqs(isa_bus, gsi);
 151
 152     if (kvm_irqchip_in_kernel()) {
 153         i8259 = kvm_i8259_init(isa_bus);
 154     } else if (xen_enabled()) {
 155         i8259 = xen_interrupt_controller_init();
 156     } else {
 157         cpu_irq = pc_allocate_cpu_irq();
 158         i8259 = i8259_init(isa_bus, cpu_irq[0]);
 159     }
 160
 161     for (i = 0; i < ISA_NUM_IRQS; i++) {
 162         gsi_state->i8259_irq[i] = i8259[i];
 163     }
 164     if (pci_enabled) {
 165         ioapic_init_gsi(gsi_state, NULL);
 166     }
 167     qdev_init_nofail(icc_bridge);
 168
 169     pc_register_ferr_irq(gsi[13]);
 170
 171     /* init basic PC hardware */
 172     pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
 173
 174     /* connect pm stuff to lpc */
 175     ich9_lpc_pm_init(lpc);
 176
 177     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 178     ahci = pci_create_simple_multifunction(host_bus,
 179                                            PCI_DEVFN(ICH9_SATA1_DEV,
 180                                                      ICH9_SATA1_FUNC),
 181                                            true, "ich9-ahci");
 182     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 183     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 184
 185     if (usb_enabled(false)) {
 186         /* Should we create 6 UHCI according to ich9 spec? */
 187         ehci_create_ich9_with_companions(host_bus, 0x1d);
 188     }
 189
 190     /* TODO: Populate SPD eeprom data.  */
 191     smbus_eeprom_init(ich9_smb_init(host_bus,
 192                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 193                                     0xb100),
 194                       8, NULL, 0);
 195
 196     pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
 197                  floppy, idebus[0], idebus[1], rtc_state);
 198
 199     /* the rest devices to which pci devfn is automatically assigned */
 200     pc_vga_init(isa_bus, host_bus);
 201     pc_nic_init(isa_bus, host_bus);
 202     if (pci_enabled) {
 203         pc_pci_device_init(host_bus);
 204     }
 205
 206     if (has_pvpanic) {
 207         pvpanic_init(isa_bus);
 208     }
 209 }
 210
 211 static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
 212 {
 213     has_pvpanic = false;
 214     x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
 215     pc_q35_init(args);
 216 }
 217
 218 static QEMUMachine pc_q35_machine_v1_5 = {
 219     .name = "pc-q35-1.5",
 220     .alias = "q35",
 221     .desc = "Standard PC (Q35 + ICH9, 2009)",
 222     .init = pc_q35_init,
 223     .hot_add_cpu = pc_hot_add_cpu,
 224     .max_cpus = 255,
 225     DEFAULT_MACHINE_OPTIONS,
 226 };
 227
 228 static QEMUMachine pc_q35_machine_v1_4 = {
 229     .name = "pc-q35-1.4",
 230     .desc = "Standard PC (Q35 + ICH9, 2009)",
 231     .init = pc_q35_init_1_4,
 232     .max_cpus = 255,
 233     .compat_props = (GlobalProperty[]) {
 234         PC_COMPAT_1_4,
 235         { /* end of list */ }
 236     },
 237     DEFAULT_MACHINE_OPTIONS,
 238 };
 239
 240 static void pc_q35_machine_init(void)
 241 {
 242     qemu_register_machine(&pc_q35_machine_v1_5);
 243     qemu_register_machine(&pc_q35_machine_v1_4);
 244 }
 245
 246 machine_init(pc_q35_machine_init);