hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "sysemu/arch_init.h"
  32 #include "hw/i2c/smbus.h"
  33 #include "hw/boards.h"
  34 #include "hw/timer/mc146818rtc.h"
  35 #include "hw/xen/xen.h"
  36 #include "sysemu/kvm.h"
  37 #include "hw/kvm/clock.h"
  38 #include "hw/pci-host/q35.h"
  39 #include "exec/address-spaces.h"
  40 #include "hw/i386/ich9.h"
  41 #include "hw/ide/pci.h"
  42 #include "hw/ide/ahci.h"
  43 #include "hw/usb.h"
  44
  45 /* ICH9 AHCI has 6 ports */
  46 #define MAX_SATA_PORTS     6
  47
  48 /* PC hardware initialisation */
  49 static void pc_q35_init(QEMUMachineInitArgs *args)
  50 {
  51     ram_addr_t ram_size = args->ram_size;
  52     const char *cpu_model = args->cpu_model;
  53     const char *kernel_filename = args->kernel_filename;
  54     const char *kernel_cmdline = args->kernel_cmdline;
  55     const char *initrd_filename = args->initrd_filename;
  56     const char *boot_device = args->boot_device;
  57     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  58     Q35PCIHost *q35_host;
  59     PCIBus *host_bus;
  60     PCIDevice *lpc;
  61     BusState *idebus[MAX_SATA_PORTS];
  62     ISADevice *rtc_state;
  63     ISADevice *floppy;
  64     MemoryRegion *pci_memory;
  65     MemoryRegion *rom_memory;
  66     MemoryRegion *ram_memory;
  67     GSIState *gsi_state;
  68     ISABus *isa_bus;
  69     int pci_enabled = 1;
  70     qemu_irq *cpu_irq;
  71     qemu_irq *gsi;
  72     qemu_irq *i8259;
  73     int i;
  74     ICH9LPCState *ich9_lpc;
  75     PCIDevice *ahci;
  76
  77     pc_cpus_init(cpu_model);
  78     pc_acpi_init("q35-acpi-dsdt.aml");
  79
  80     kvmclock_create();
  81
  82     if (ram_size >= 0xb0000000) {
  83         above_4g_mem_size = ram_size - 0xb0000000;
  84         below_4g_mem_size = 0xb0000000;
  85     } else {
  86         above_4g_mem_size = 0;
  87         below_4g_mem_size = ram_size;
  88     }
  89
  90     /* pci enabled */
  91     if (pci_enabled) {
  92         pci_memory = g_new(MemoryRegion, 1);
  93         memory_region_init(pci_memory, "pci", INT64_MAX);
  94         rom_memory = pci_memory;
  95     } else {
  96         pci_memory = NULL;
  97         rom_memory = get_system_memory();
  98     }
  99
 100     /* allocate ram and load rom/bios */
 101     if (!xen_enabled()) {
 102         pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
 103                        initrd_filename, below_4g_mem_size, above_4g_mem_size,
 104                        rom_memory, &ram_memory);
 105     }
 106
 107     /* irq lines */
 108     gsi_state = g_malloc0(sizeof(*gsi_state));
 109     if (kvm_irqchip_in_kernel()) {
 110         kvm_pc_setup_irq_routing(pci_enabled);
 111         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 112                                  GSI_NUM_PINS);
 113     } else {
 114         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 115     }
 116
 117     /* create pci host bus */
 118     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 119
 120     q35_host->mch.ram_memory = ram_memory;
 121     q35_host->mch.pci_address_space = pci_memory;
 122     q35_host->mch.system_memory = get_system_memory();
 123     q35_host->mch.address_space_io = get_system_io();;
 124     q35_host->mch.below_4g_mem_size = below_4g_mem_size;
 125     q35_host->mch.above_4g_mem_size = above_4g_mem_size;
 126     /* pci */
 127     qdev_init_nofail(DEVICE(q35_host));
 128     host_bus = q35_host->host.pci.bus;
 129     /* create ISA bus */
 130     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 131                                           ICH9_LPC_FUNC), true,
 132                                           TYPE_ICH9_LPC_DEVICE);
 133     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 134     ich9_lpc->pic = gsi;
 135     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 136     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 137                  ICH9_LPC_NB_PIRQS);
 138     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 139     isa_bus = ich9_lpc->isa_bus;
 140
 141     /*end early*/
 142     isa_bus_irqs(isa_bus, gsi);
 143
 144     if (kvm_irqchip_in_kernel()) {
 145         i8259 = kvm_i8259_init(isa_bus);
 146     } else if (xen_enabled()) {
 147         i8259 = xen_interrupt_controller_init();
 148     } else {
 149         cpu_irq = pc_allocate_cpu_irq();
 150         i8259 = i8259_init(isa_bus, cpu_irq[0]);
 151     }
 152
 153     for (i = 0; i < ISA_NUM_IRQS; i++) {
 154         gsi_state->i8259_irq[i] = i8259[i];
 155     }
 156     if (pci_enabled) {
 157         ioapic_init_gsi(gsi_state, NULL);
 158     }
 159
 160     pc_register_ferr_irq(gsi[13]);
 161
 162     /* init basic PC hardware */
 163     pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
 164
 165     /* connect pm stuff to lpc */
 166     ich9_lpc_pm_init(lpc);
 167
 168     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 169     ahci = pci_create_simple_multifunction(host_bus,
 170                                            PCI_DEVFN(ICH9_SATA1_DEV,
 171                                                      ICH9_SATA1_FUNC),
 172                                            true, "ich9-ahci");
 173     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 174     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 175
 176     if (usb_enabled(false)) {
 177         /* Should we create 6 UHCI according to ich9 spec? */
 178         ehci_create_ich9_with_companions(host_bus, 0x1d);
 179     }
 180
 181     /* TODO: Populate SPD eeprom data.  */
 182     smbus_eeprom_init(ich9_smb_init(host_bus,
 183                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 184                                     0xb100),
 185                       8, NULL, 0);
 186
 187     pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
 188                  floppy, idebus[0], idebus[1], rtc_state);
 189
 190     /* the rest devices to which pci devfn is automatically assigned */
 191     pc_vga_init(isa_bus, host_bus);
 192     audio_init(isa_bus, host_bus);
 193     pc_nic_init(isa_bus, host_bus);
 194     if (pci_enabled) {
 195         pc_pci_device_init(host_bus);
 196     }
 197 }
 198
 199 static QEMUMachine pc_q35_machine_v1_5 = {
 200     .name = "pc-q35-1.5",
 201     .alias = "q35",
 202     .desc = "Standard PC (Q35 + ICH9, 2009)",
 203     .init = pc_q35_init,
 204     .max_cpus = 255,
 205     DEFAULT_MACHINE_OPTIONS,
 206 };
 207
 208 static QEMUMachine pc_q35_machine_v1_4 = {
 209     .name = "pc-q35-1.4",
 210     .desc = "Standard PC (Q35 + ICH9, 2009)",
 211     .init = pc_q35_init,
 212     .max_cpus = 255,
 213     .compat_props = (GlobalProperty[]) {
 214         PC_COMPAT_1_4,
 215         { /* end of list */ }
 216     },
 217     DEFAULT_MACHINE_OPTIONS,
 218 };
 219
 220 static void pc_q35_machine_init(void)
 221 {
 222     qemu_register_machine(&pc_q35_machine_v1_5);
 223     qemu_register_machine(&pc_q35_machine_v1_4);
 224 }
 225
 226 machine_init(pc_q35_machine_init);