hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "sysemu/arch_init.h"
  32 #include "hw/i2c/smbus.h"
  33 #include "hw/boards.h"
  34 #include "hw/timer/mc146818rtc.h"
  35 #include "hw/xen/xen.h"
  36 #include "sysemu/kvm.h"
  37 #include "hw/kvm/clock.h"
  38 #include "hw/pci-host/q35.h"
  39 #include "exec/address-spaces.h"
  40 #include "hw/i386/ich9.h"
  41 #include "hw/ide/pci.h"
  42 #include "hw/ide/ahci.h"
  43 #include "hw/usb.h"
  44 #include "hw/cpu/icc_bus.h"
  45
  46 /* ICH9 AHCI has 6 ports */
  47 #define MAX_SATA_PORTS     6
  48
  49 static bool has_pvpanic = true;
  50 static bool has_pci_info = true;
  51
  52 /* PC hardware initialisation */
  53 static void pc_q35_init(QEMUMachineInitArgs *args)
  54 {
  55     ram_addr_t ram_size = args->ram_size;
  56     const char *cpu_model = args->cpu_model;
  57     const char *kernel_filename = args->kernel_filename;
  58     const char *kernel_cmdline = args->kernel_cmdline;
  59     const char *initrd_filename = args->initrd_filename;
  60     const char *boot_device = args->boot_device;
  61     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  62     Q35PCIHost *q35_host;
  63     PCIHostState *phb;
  64     PCIBus *host_bus;
  65     PCIDevice *lpc;
  66     BusState *idebus[MAX_SATA_PORTS];
  67     ISADevice *rtc_state;
  68     ISADevice *floppy;
  69     MemoryRegion *pci_memory;
  70     MemoryRegion *rom_memory;
  71     MemoryRegion *ram_memory;
  72     GSIState *gsi_state;
  73     ISABus *isa_bus;
  74     int pci_enabled = 1;
  75     qemu_irq *cpu_irq;
  76     qemu_irq *gsi;
  77     qemu_irq *i8259;
  78     int i;
  79     ICH9LPCState *ich9_lpc;
  80     PCIDevice *ahci;
  81     DeviceState *icc_bridge;
  82     PcGuestInfo *guest_info;
  83
  84     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
  85     object_property_add_child(qdev_get_machine(), "icc-bridge",
  86                               OBJECT(icc_bridge), NULL);
  87
  88     pc_cpus_init(cpu_model, icc_bridge);
  89     pc_acpi_init("q35-acpi-dsdt.aml");
  90
  91     kvmclock_create();
  92
  93     if (ram_size >= 0xb0000000) {
  94         above_4g_mem_size = ram_size - 0xb0000000;
  95         below_4g_mem_size = 0xb0000000;
  96     } else {
  97         above_4g_mem_size = 0;
  98         below_4g_mem_size = ram_size;
  99     }
 100
 101     /* pci enabled */
 102     if (pci_enabled) {
 103         pci_memory = g_new(MemoryRegion, 1);
 104         memory_region_init(pci_memory, NULL, "pci", INT64_MAX);
 105         rom_memory = pci_memory;
 106     } else {
 107         pci_memory = NULL;
 108         rom_memory = get_system_memory();
 109     }
 110
 111     guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
 112     guest_info->has_pci_info = has_pci_info;
 113
 114     /* allocate ram and load rom/bios */
 115     if (!xen_enabled()) {
 116         pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
 117                        initrd_filename, below_4g_mem_size, above_4g_mem_size,
 118                        rom_memory, &ram_memory, guest_info);
 119     }
 120
 121     /* irq lines */
 122     gsi_state = g_malloc0(sizeof(*gsi_state));
 123     if (kvm_irqchip_in_kernel()) {
 124         kvm_pc_setup_irq_routing(pci_enabled);
 125         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 126                                  GSI_NUM_PINS);
 127     } else {
 128         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 129     }
 130
 131     /* create pci host bus */
 132     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 133
 134     q35_host->mch.ram_memory = ram_memory;
 135     q35_host->mch.pci_address_space = pci_memory;
 136     q35_host->mch.system_memory = get_system_memory();
 137     q35_host->mch.address_space_io = get_system_io();
 138     q35_host->mch.below_4g_mem_size = below_4g_mem_size;
 139     q35_host->mch.above_4g_mem_size = above_4g_mem_size;
 140     q35_host->mch.guest_info = guest_info;
 141     /* pci */
 142     qdev_init_nofail(DEVICE(q35_host));
 143     phb = PCI_HOST_BRIDGE(q35_host);
 144     host_bus = phb->bus;
 145     /* create ISA bus */
 146     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 147                                           ICH9_LPC_FUNC), true,
 148                                           TYPE_ICH9_LPC_DEVICE);
 149     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 150     ich9_lpc->pic = gsi;
 151     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 152     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 153                  ICH9_LPC_NB_PIRQS);
 154     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 155     isa_bus = ich9_lpc->isa_bus;
 156
 157     /*end early*/
 158     isa_bus_irqs(isa_bus, gsi);
 159
 160     if (kvm_irqchip_in_kernel()) {
 161         i8259 = kvm_i8259_init(isa_bus);
 162     } else if (xen_enabled()) {
 163         i8259 = xen_interrupt_controller_init();
 164     } else {
 165         cpu_irq = pc_allocate_cpu_irq();
 166         i8259 = i8259_init(isa_bus, cpu_irq[0]);
 167     }
 168
 169     for (i = 0; i < ISA_NUM_IRQS; i++) {
 170         gsi_state->i8259_irq[i] = i8259[i];
 171     }
 172     if (pci_enabled) {
 173         ioapic_init_gsi(gsi_state, NULL);
 174     }
 175     qdev_init_nofail(icc_bridge);
 176
 177     pc_register_ferr_irq(gsi[13]);
 178
 179     /* init basic PC hardware */
 180     pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
 181
 182     /* connect pm stuff to lpc */
 183     ich9_lpc_pm_init(lpc);
 184
 185     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 186     ahci = pci_create_simple_multifunction(host_bus,
 187                                            PCI_DEVFN(ICH9_SATA1_DEV,
 188                                                      ICH9_SATA1_FUNC),
 189                                            true, "ich9-ahci");
 190     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 191     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 192
 193     if (usb_enabled(false)) {
 194         /* Should we create 6 UHCI according to ich9 spec? */
 195         ehci_create_ich9_with_companions(host_bus, 0x1d);
 196     }
 197
 198     /* TODO: Populate SPD eeprom data.  */
 199     smbus_eeprom_init(ich9_smb_init(host_bus,
 200                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 201                                     0xb100),
 202                       8, NULL, 0);
 203
 204     pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
 205                  floppy, idebus[0], idebus[1], rtc_state);
 206
 207     /* the rest devices to which pci devfn is automatically assigned */
 208     pc_vga_init(isa_bus, host_bus);
 209     pc_nic_init(isa_bus, host_bus);
 210     if (pci_enabled) {
 211         pc_pci_device_init(host_bus);
 212     }
 213
 214     if (has_pvpanic) {
 215         pvpanic_init(isa_bus);
 216     }
 217 }
 218
 219 static void pc_q35_init_1_5(QEMUMachineInitArgs *args)
 220 {
 221     has_pci_info = false;
 222     pc_q35_init(args);
 223 }
 224
 225 static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
 226 {
 227     has_pvpanic = false;
 228     x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
 229     pc_q35_init_1_5(args);
 230 }
 231
 232 static QEMUMachine pc_q35_machine_v1_6 = {
 233     .name = "pc-q35-1.6",
 234     .alias = "q35",
 235     .desc = "Standard PC (Q35 + ICH9, 2009)",
 236     .init = pc_q35_init,
 237     .hot_add_cpu = pc_hot_add_cpu,
 238     .max_cpus = 255,
 239     DEFAULT_MACHINE_OPTIONS,
 240 };
 241
 242 static QEMUMachine pc_q35_machine_v1_5 = {
 243     .name = "pc-q35-1.5",
 244     .desc = "Standard PC (Q35 + ICH9, 2009)",
 245     .init = pc_q35_init_1_5,
 246     .hot_add_cpu = pc_hot_add_cpu,
 247     .max_cpus = 255,
 248     .compat_props = (GlobalProperty[]) {
 249         PC_COMPAT_1_5,
 250         { /* end of list */ }
 251     },
 252     DEFAULT_MACHINE_OPTIONS,
 253 };
 254
 255 static QEMUMachine pc_q35_machine_v1_4 = {
 256     .name = "pc-q35-1.4",
 257     .desc = "Standard PC (Q35 + ICH9, 2009)",
 258     .init = pc_q35_init_1_4,
 259     .max_cpus = 255,
 260     .compat_props = (GlobalProperty[]) {
 261         PC_COMPAT_1_4,
 262         { /* end of list */ }
 263     },
 264     DEFAULT_MACHINE_OPTIONS,
 265 };
 266
 267 static void pc_q35_machine_init(void)
 268 {
 269     qemu_register_machine(&pc_q35_machine_v1_6);
 270     qemu_register_machine(&pc_q35_machine_v1_5);
 271     qemu_register_machine(&pc_q35_machine_v1_4);
 272 }
 273
 274 machine_init(pc_q35_machine_init);