2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "hw/loader.h"
32 #include "sysemu/arch_init.h"
33 #include "hw/i2c/smbus.h"
34 #include "hw/boards.h"
35 #include "hw/timer/mc146818rtc.h"
36 #include "hw/xen/xen.h"
37 #include "sysemu/kvm.h"
38 #include "hw/kvm/clock.h"
39 #include "hw/pci-host/q35.h"
40 #include "exec/address-spaces.h"
41 #include "hw/i386/ich9.h"
42 #include "hw/ide/pci.h"
43 #include "hw/ide/ahci.h"
45 #include "hw/cpu/icc_bus.h"
47 /* ICH9 AHCI has 6 ports */
48 #define MAX_SATA_PORTS 6
50 static bool has_pvpanic
;
51 static bool has_pci_info
= true;
53 /* PC hardware initialisation */
54 static void pc_q35_init(QEMUMachineInitArgs
*args
)
56 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
61 BusState
*idebus
[MAX_SATA_PORTS
];
64 MemoryRegion
*pci_memory
;
65 MemoryRegion
*rom_memory
;
66 MemoryRegion
*ram_memory
;
74 ICH9LPCState
*ich9_lpc
;
76 DeviceState
*icc_bridge
;
77 PcGuestInfo
*guest_info
;
79 icc_bridge
= qdev_create(NULL
, TYPE_ICC_BRIDGE
);
80 object_property_add_child(qdev_get_machine(), "icc-bridge",
81 OBJECT(icc_bridge
), NULL
);
83 pc_cpus_init(args
->cpu_model
, icc_bridge
);
84 pc_acpi_init("q35-acpi-dsdt.aml");
88 if (args
->ram_size
>= 0xb0000000) {
89 above_4g_mem_size
= args
->ram_size
- 0xb0000000;
90 below_4g_mem_size
= 0xb0000000;
92 above_4g_mem_size
= 0;
93 below_4g_mem_size
= args
->ram_size
;
98 pci_memory
= g_new(MemoryRegion
, 1);
99 memory_region_init(pci_memory
, NULL
, "pci", INT64_MAX
);
100 rom_memory
= pci_memory
;
103 rom_memory
= get_system_memory();
106 guest_info
= pc_guest_info_init(below_4g_mem_size
, above_4g_mem_size
);
107 guest_info
->has_pci_info
= has_pci_info
;
108 guest_info
->isapc_ram_fw
= false;
110 /* allocate ram and load rom/bios */
111 if (!xen_enabled()) {
112 pc_memory_init(get_system_memory(),
113 args
->kernel_filename
, args
->kernel_cmdline
,
114 args
->initrd_filename
,
115 below_4g_mem_size
, above_4g_mem_size
,
116 rom_memory
, &ram_memory
, guest_info
);
120 gsi_state
= g_malloc0(sizeof(*gsi_state
));
121 if (kvm_irqchip_in_kernel()) {
122 kvm_pc_setup_irq_routing(pci_enabled
);
123 gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
126 gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
129 /* create pci host bus */
130 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
132 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host
), NULL
);
133 q35_host
->mch
.ram_memory
= ram_memory
;
134 q35_host
->mch
.pci_address_space
= pci_memory
;
135 q35_host
->mch
.system_memory
= get_system_memory();
136 q35_host
->mch
.address_space_io
= get_system_io();
137 q35_host
->mch
.below_4g_mem_size
= below_4g_mem_size
;
138 q35_host
->mch
.above_4g_mem_size
= above_4g_mem_size
;
139 q35_host
->mch
.guest_info
= guest_info
;
141 qdev_init_nofail(DEVICE(q35_host
));
142 phb
= PCI_HOST_BRIDGE(q35_host
);
145 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
146 ICH9_LPC_FUNC
), true,
147 TYPE_ICH9_LPC_DEVICE
);
148 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
150 ich9_lpc
->ioapic
= gsi_state
->ioapic_irq
;
151 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
153 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
154 isa_bus
= ich9_lpc
->isa_bus
;
157 isa_bus_irqs(isa_bus
, gsi
);
159 if (kvm_irqchip_in_kernel()) {
160 i8259
= kvm_i8259_init(isa_bus
);
161 } else if (xen_enabled()) {
162 i8259
= xen_interrupt_controller_init();
164 cpu_irq
= pc_allocate_cpu_irq();
165 i8259
= i8259_init(isa_bus
, cpu_irq
[0]);
168 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
169 gsi_state
->i8259_irq
[i
] = i8259
[i
];
172 ioapic_init_gsi(gsi_state
, NULL
);
174 qdev_init_nofail(icc_bridge
);
176 pc_register_ferr_irq(gsi
[13]);
178 /* init basic PC hardware */
179 pc_basic_device_init(isa_bus
, gsi
, &rtc_state
, &floppy
, false);
181 /* connect pm stuff to lpc */
182 ich9_lpc_pm_init(lpc
);
184 /* ahci and SATA device, for q35 1 ahci controller is built-in */
185 ahci
= pci_create_simple_multifunction(host_bus
,
186 PCI_DEVFN(ICH9_SATA1_DEV
,
189 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
190 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
192 if (usb_enabled(false)) {
193 /* Should we create 6 UHCI according to ich9 spec? */
194 ehci_create_ich9_with_companions(host_bus
, 0x1d);
197 /* TODO: Populate SPD eeprom data. */
198 smbus_eeprom_init(ich9_smb_init(host_bus
,
199 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
203 pc_cmos_init(below_4g_mem_size
, above_4g_mem_size
, args
->boot_order
,
204 floppy
, idebus
[0], idebus
[1], rtc_state
);
206 /* the rest devices to which pci devfn is automatically assigned */
207 pc_vga_init(isa_bus
, host_bus
);
208 pc_nic_init(isa_bus
, host_bus
);
210 pc_pci_device_init(host_bus
);
214 pvpanic_init(isa_bus
);
218 static void pc_compat_1_6(QEMUMachineInitArgs
*args
)
220 has_pci_info
= false;
221 rom_file_in_ram
= false;
224 static void pc_compat_1_5(QEMUMachineInitArgs
*args
)
230 static void pc_compat_1_4(QEMUMachineInitArgs
*args
)
234 x86_cpu_compat_set_features("n270", FEAT_1_ECX
, 0, CPUID_EXT_MOVBE
);
235 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX
, 0, CPUID_EXT_PCLMULQDQ
);
238 static void pc_q35_init_1_6(QEMUMachineInitArgs
*args
)
244 static void pc_q35_init_1_5(QEMUMachineInitArgs
*args
)
250 static void pc_q35_init_1_4(QEMUMachineInitArgs
*args
)
256 static QEMUMachine pc_q35_machine_v1_6
= {
257 .name
= "pc-q35-1.6",
259 .desc
= "Standard PC (Q35 + ICH9, 2009)",
260 .init
= pc_q35_init_1_6
,
261 .hot_add_cpu
= pc_hot_add_cpu
,
263 .default_boot_order
= "cad",
266 static QEMUMachine pc_q35_machine_v1_5
= {
267 .name
= "pc-q35-1.5",
268 .desc
= "Standard PC (Q35 + ICH9, 2009)",
269 .init
= pc_q35_init_1_5
,
270 .hot_add_cpu
= pc_hot_add_cpu
,
272 .default_boot_order
= "cad",
273 .compat_props
= (GlobalProperty
[]) {
275 { /* end of list */ }
279 static QEMUMachine pc_q35_machine_v1_4
= {
280 .name
= "pc-q35-1.4",
281 .desc
= "Standard PC (Q35 + ICH9, 2009)",
282 .init
= pc_q35_init_1_4
,
284 .default_boot_order
= "cad",
285 .compat_props
= (GlobalProperty
[]) {
287 { /* end of list */ }
291 static void pc_q35_machine_init(void)
293 qemu_register_machine(&pc_q35_machine_v1_6
);
294 qemu_register_machine(&pc_q35_machine_v1_5
);
295 qemu_register_machine(&pc_q35_machine_v1_4
);
298 machine_init(pc_q35_machine_init
);