2 * QEMU 8253/8254 interval timer emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #define RW_STATE_LSB 0
29 #define RW_STATE_MSB 1
30 #define RW_STATE_WORD0 2
31 #define RW_STATE_WORD1 3
32 #define RW_STATE_LATCHED_WORD0 4
33 #define RW_STATE_LATCHED_WORD1 5
35 PITChannelState pit_channels
[3];
37 static void pit_irq_timer_update(PITChannelState
*s
, int64_t current_time
);
39 static int pit_get_count(PITChannelState
*s
)
44 d
= muldiv64(qemu_get_clock(vm_clock
) - s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
50 counter
= (s
->count
- d
) & 0xffff;
53 /* XXX: may be incorrect for odd counts */
54 counter
= s
->count
- ((2 * d
) % s
->count
);
57 counter
= s
->count
- (d
% s
->count
);
63 /* get pit output bit */
64 int pit_get_out(PITChannelState
*s
, int64_t current_time
)
69 d
= muldiv64(current_time
- s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
73 out
= (d
>= s
->count
);
79 if ((d
% s
->count
) == 0 && d
!= 0)
85 out
= (d
% s
->count
) < ((s
->count
+ 1) >> 1);
89 out
= (d
== s
->count
);
95 /* return -1 if no transition will occur. */
96 static int64_t pit_get_next_transition_time(PITChannelState
*s
,
99 uint64_t d
, next_time
, base
;
102 d
= muldiv64(current_time
- s
->count_load_time
, PIT_FREQ
, ticks_per_sec
);
108 next_time
= s
->count
;
113 base
= (d
/ s
->count
) * s
->count
;
114 if ((d
- base
) == 0 && d
!= 0)
115 next_time
= base
+ s
->count
;
117 next_time
= base
+ s
->count
+ 1;
120 base
= (d
/ s
->count
) * s
->count
;
121 period2
= ((s
->count
+ 1) >> 1);
122 if ((d
- base
) < period2
)
123 next_time
= base
+ period2
;
125 next_time
= base
+ s
->count
;
130 next_time
= s
->count
;
131 else if (d
== s
->count
)
132 next_time
= s
->count
+ 1;
137 /* convert to timer units */
138 next_time
= s
->count_load_time
+ muldiv64(next_time
, ticks_per_sec
, PIT_FREQ
);
142 /* val must be 0 or 1 */
143 void pit_set_gate(PITChannelState
*s
, int val
)
149 /* XXX: just disable/enable counting */
154 /* restart counting on rising edge */
155 s
->count_load_time
= qemu_get_clock(vm_clock
);
156 pit_irq_timer_update(s
, s
->count_load_time
);
162 /* restart counting on rising edge */
163 s
->count_load_time
= qemu_get_clock(vm_clock
);
164 pit_irq_timer_update(s
, s
->count_load_time
);
166 /* XXX: disable/enable counting */
172 static inline void pit_load_count(PITChannelState
*s
, int val
)
176 s
->count_load_time
= qemu_get_clock(vm_clock
);
178 pit_irq_timer_update(s
, s
->count_load_time
);
181 static void pit_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
191 s
= &pit_channels
[channel
];
192 access
= (val
>> 4) & 3;
195 s
->latched_count
= pit_get_count(s
);
196 s
->rw_state
= RW_STATE_LATCHED_WORD0
;
199 s
->mode
= (val
>> 1) & 7;
201 s
->rw_state
= access
- 1 + RW_STATE_LSB
;
202 /* XXX: update irq timer ? */
206 s
= &pit_channels
[addr
];
207 switch(s
->rw_state
) {
209 pit_load_count(s
, val
);
212 pit_load_count(s
, val
<< 8);
216 if (s
->rw_state
& 1) {
217 pit_load_count(s
, (s
->latched_count
& 0xff) | (val
<< 8));
219 s
->latched_count
= val
;
227 static uint32_t pit_ioport_read(void *opaque
, uint32_t addr
)
233 s
= &pit_channels
[addr
];
234 switch(s
->rw_state
) {
239 count
= pit_get_count(s
);
241 ret
= (count
>> 8) & 0xff;
248 case RW_STATE_LATCHED_WORD0
:
249 case RW_STATE_LATCHED_WORD1
:
251 ret
= s
->latched_count
>> 8;
253 ret
= s
->latched_count
& 0xff;
260 static void pit_irq_timer_update(PITChannelState
*s
, int64_t current_time
)
267 expire_time
= pit_get_next_transition_time(s
, current_time
);
268 irq_level
= pit_get_out(s
, current_time
);
269 pic_set_irq(s
->irq
, irq_level
);
271 printf("irq_level=%d next_delay=%f\n",
273 (double)(expire_time
- current_time
) / ticks_per_sec
);
275 s
->next_transition_time
= expire_time
;
276 if (expire_time
!= -1)
277 qemu_mod_timer(s
->irq_timer
, expire_time
);
279 qemu_del_timer(s
->irq_timer
);
282 static void pit_irq_timer(void *opaque
)
284 PITChannelState
*s
= opaque
;
286 pit_irq_timer_update(s
, s
->next_transition_time
);
289 static void pit_save(QEMUFile
*f
, void *opaque
)
294 for(i
= 0; i
< 3; i
++) {
295 s
= &pit_channels
[i
];
296 qemu_put_be32s(f
, &s
->count
);
297 qemu_put_be16s(f
, &s
->latched_count
);
298 qemu_put_8s(f
, &s
->rw_state
);
299 qemu_put_8s(f
, &s
->mode
);
300 qemu_put_8s(f
, &s
->bcd
);
301 qemu_put_8s(f
, &s
->gate
);
302 qemu_put_be64s(f
, &s
->count_load_time
);
304 qemu_put_be64s(f
, &s
->next_transition_time
);
305 qemu_put_timer(f
, s
->irq_timer
);
310 static int pit_load(QEMUFile
*f
, void *opaque
, int version_id
)
318 for(i
= 0; i
< 3; i
++) {
319 s
= &pit_channels
[i
];
320 qemu_get_be32s(f
, &s
->count
);
321 qemu_get_be16s(f
, &s
->latched_count
);
322 qemu_get_8s(f
, &s
->rw_state
);
323 qemu_get_8s(f
, &s
->mode
);
324 qemu_get_8s(f
, &s
->bcd
);
325 qemu_get_8s(f
, &s
->gate
);
326 qemu_get_be64s(f
, &s
->count_load_time
);
328 qemu_get_be64s(f
, &s
->next_transition_time
);
329 qemu_get_timer(f
, s
->irq_timer
);
335 void pit_init(int base
, int irq
)
340 for(i
= 0;i
< 3; i
++) {
341 s
= &pit_channels
[i
];
343 /* the timer 0 is connected to an IRQ */
344 s
->irq_timer
= qemu_new_timer(vm_clock
, pit_irq_timer
, s
);
349 pit_load_count(s
, 0);
352 register_savevm("i8254", base
, 1, pit_save
, pit_load
, NULL
);
354 register_ioport_write(base
, 4, 1, pit_ioport_write
, NULL
);
355 register_ioport_read(base
, 3, 1, pit_ioport_read
, NULL
);