hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug PIC */
  27 //#define DEBUG_PIC
  28
  29 //#define DEBUG_IRQ_LATENCY
  30 //#define DEBUG_IRQ_COUNT
  31
  32 typedef struct PicState {
  33     uint8_t last_irr; /* edge detection */
  34     uint8_t irr; /* interrupt request register */
  35     uint8_t imr; /* interrupt mask register */
  36     uint8_t isr; /* interrupt service register */
  37     uint8_t priority_add; /* highest irq priority */
  38     uint8_t irq_base;
  39     uint8_t read_reg_select;
  40     uint8_t poll;
  41     uint8_t special_mask;
  42     uint8_t init_state;
  43     uint8_t auto_eoi;
  44     uint8_t rotate_on_auto_eoi;
  45     uint8_t special_fully_nested_mode;
  46     uint8_t init4; /* true if 4 byte init */
  47     uint8_t elcr; /* PIIX edge/trigger selection*/
  48     uint8_t elcr_mask;
  49 } PicState;
  50
  51 /* 0 is master pic, 1 is slave pic */
  52 static PicState pics[2];
  53
  54 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  55 static int irq_level[16];
  56 #endif
  57 #ifdef DEBUG_IRQ_COUNT
  58 static uint64_t irq_count[16];
  59 #endif
  60
  61 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  62 static inline void pic_set_irq1(PicState *s, int irq, int level)
  63 {
  64     int mask;
  65     mask = 1 << irq;
  66     if (s->elcr & mask) {
  67         /* level triggered */
  68         if (level) {
  69             s->irr |= mask;
  70             s->last_irr |= mask;
  71         } else {
  72             s->irr &= ~mask;
  73             s->last_irr &= ~mask;
  74         }
  75     } else {
  76         /* edge triggered */
  77         if (level) {
  78             if ((s->last_irr & mask) == 0)
  79                 s->irr |= mask;
  80             s->last_irr |= mask;
  81         } else {
  82             s->last_irr &= ~mask;
  83         }
  84     }
  85 }
  86
  87 /* return the highest priority found in mask (highest = smallest
  88    number). Return 8 if no irq */
  89 static inline int get_priority(PicState *s, int mask)
  90 {
  91     int priority;
  92     if (mask == 0)
  93         return 8;
  94     priority = 0;
  95     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  96         priority++;
  97     return priority;
  98 }
  99
 100 /* return the pic wanted interrupt. return -1 if none */
 101 static int pic_get_irq(PicState *s)
 102 {
 103     int mask, cur_priority, priority;
 104
 105     mask = s->irr & ~s->imr;
 106     priority = get_priority(s, mask);
 107     if (priority == 8)
 108         return -1;
 109     /* compute current priority. If special fully nested mode on the
 110        master, the IRQ coming from the slave is not taken into account
 111        for the priority computation. */
 112     mask = s->isr;
 113     if (s->special_fully_nested_mode && s == &pics[0])
 114         mask &= ~(1 << 2);
 115     cur_priority = get_priority(s, mask);
 116     if (priority < cur_priority) {
 117         /* higher priority found: an irq should be generated */
 118         return (priority + s->priority_add) & 7;
 119     } else {
 120         return -1;
 121     }
 122 }
 123
 124 /* raise irq to CPU if necessary. must be called every time the active
 125    irq may change */
 126 static void pic_update_irq(void)
 127 {
 128     int irq2, irq;
 129
 130     /* first look at slave pic */
 131     irq2 = pic_get_irq(&pics[1]);
 132     if (irq2 >= 0) {
 133         /* if irq request by slave pic, signal master PIC */
 134         pic_set_irq1(&pics[0], 2, 1);
 135         pic_set_irq1(&pics[0], 2, 0);
 136     }
 137     /* look at requested irq */
 138     irq = pic_get_irq(&pics[0]);
 139     if (irq >= 0) {
 140 #if defined(DEBUG_PIC)
 141         {
 142             int i;
 143             for(i = 0; i < 2; i++) {
 144                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 145                        i, pics[i].imr, pics[i].irr, pics[i].priority_add);
 146
 147             }
 148         }
 149         printf("pic: cpu_interrupt\n");
 150 #endif
 151         cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 152     }
 153 }
 154
 155 #ifdef DEBUG_IRQ_LATENCY
 156 int64_t irq_time[16];
 157 #endif
 158
 159 void pic_set_irq(int irq, int level)
 160 {
 161 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 162     if (level != irq_level[irq]) {
 163 #if defined(DEBUG_PIC)
 164         printf("pic_set_irq: irq=%d level=%d\n", irq, level);
 165 #endif
 166         irq_level[irq] = level;
 167 #ifdef DEBUG_IRQ_COUNT
 168         if (level == 1)
 169             irq_count[irq]++;
 170 #endif
 171     }
 172 #endif
 173 #ifdef DEBUG_IRQ_LATENCY
 174     if (level) {
 175         irq_time[irq] = qemu_get_clock(vm_clock);
 176     }
 177 #endif
 178     pic_set_irq1(&pics[irq >> 3], irq & 7, level);
 179     pic_update_irq();
 180 }
 181
 182 /* acknowledge interrupt 'irq' */
 183 static inline void pic_intack(PicState *s, int irq)
 184 {
 185     if (s->auto_eoi) {
 186         if (s->rotate_on_auto_eoi)
 187             s->priority_add = (irq + 1) & 7;
 188     } else {
 189         s->isr |= (1 << irq);
 190     }
 191     /* We don't clear a level sensitive interrupt here */
 192     if (!(s->elcr & (1 << irq)))
 193         s->irr &= ~(1 << irq);
 194 }
 195
 196 int cpu_get_pic_interrupt(CPUState *env)
 197 {
 198     int irq, irq2, intno;
 199
 200     /* read the irq from the PIC */
 201
 202     irq = pic_get_irq(&pics[0]);
 203     if (irq >= 0) {
 204         pic_intack(&pics[0], irq);
 205         if (irq == 2) {
 206             irq2 = pic_get_irq(&pics[1]);
 207             if (irq2 >= 0) {
 208                 pic_intack(&pics[1], irq2);
 209             } else {
 210                 /* spurious IRQ on slave controller */
 211                 irq2 = 7;
 212             }
 213             intno = pics[1].irq_base + irq2;
 214             irq = irq2 + 8;
 215         } else {
 216             intno = pics[0].irq_base + irq;
 217         }
 218     } else {
 219         /* spurious IRQ on host controller */
 220         irq = 7;
 221         intno = pics[0].irq_base + irq;
 222     }
 223     pic_update_irq();
 224
 225 #ifdef DEBUG_IRQ_LATENCY
 226     printf("IRQ%d latency=%0.3fus\n",
 227            irq,
 228            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 229 #endif
 230 #if defined(DEBUG_PIC)
 231     printf("pic_interrupt: irq=%d\n", irq);
 232 #endif
 233     return intno;
 234 }
 235
 236 static void pic_reset(void *opaque)
 237 {
 238     PicState *s = opaque;
 239     int tmp;
 240
 241     tmp = s->elcr_mask;
 242     memset(s, 0, sizeof(PicState));
 243     s->elcr_mask = tmp;
 244 }
 245
 246 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 247 {
 248     PicState *s = opaque;
 249     int priority, cmd, irq;
 250
 251 #ifdef DEBUG_PIC
 252     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 253 #endif
 254     addr &= 1;
 255     if (addr == 0) {
 256         if (val & 0x10) {
 257             /* init */
 258             pic_reset(s);
 259             /* deassert a pending interrupt */
 260             cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 261
 262             s->init_state = 1;
 263             s->init4 = val & 1;
 264             if (val & 0x02)
 265                 hw_error("single mode not supported");
 266             if (val & 0x08)
 267                 hw_error("level sensitive irq not supported");
 268         } else if (val & 0x08) {
 269             if (val & 0x04)
 270                 s->poll = 1;
 271             if (val & 0x02)
 272                 s->read_reg_select = val & 1;
 273             if (val & 0x40)
 274                 s->special_mask = (val >> 5) & 1;
 275         } else {
 276             cmd = val >> 5;
 277             switch(cmd) {
 278             case 0:
 279             case 4:
 280                 s->rotate_on_auto_eoi = cmd >> 2;
 281                 break;
 282             case 1: /* end of interrupt */
 283             case 5:
 284                 priority = get_priority(s, s->isr);
 285                 if (priority != 8) {
 286                     irq = (priority + s->priority_add) & 7;
 287                     s->isr &= ~(1 << irq);
 288                     if (cmd == 5)
 289                         s->priority_add = (irq + 1) & 7;
 290                     pic_update_irq();
 291                 }
 292                 break;
 293             case 3:
 294                 irq = val & 7;
 295                 s->isr &= ~(1 << irq);
 296                 pic_update_irq();
 297                 break;
 298             case 6:
 299                 s->priority_add = (val + 1) & 7;
 300                 pic_update_irq();
 301                 break;
 302             case 7:
 303                 irq = val & 7;
 304                 s->isr &= ~(1 << irq);
 305                 s->priority_add = (irq + 1) & 7;
 306                 pic_update_irq();
 307                 break;
 308             default:
 309                 /* no operation */
 310                 break;
 311             }
 312         }
 313     } else {
 314         switch(s->init_state) {
 315         case 0:
 316             /* normal mode */
 317             s->imr = val;
 318             pic_update_irq();
 319             break;
 320         case 1:
 321             s->irq_base = val & 0xf8;
 322             s->init_state = 2;
 323             break;
 324         case 2:
 325             if (s->init4) {
 326                 s->init_state = 3;
 327             } else {
 328                 s->init_state = 0;
 329             }
 330             break;
 331         case 3:
 332             s->special_fully_nested_mode = (val >> 4) & 1;
 333             s->auto_eoi = (val >> 1) & 1;
 334             s->init_state = 0;
 335             break;
 336         }
 337     }
 338 }
 339
 340 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 341 {
 342     int ret;
 343
 344     ret = pic_get_irq(s);
 345     if (ret >= 0) {
 346         if (addr1 >> 7) {
 347             pics[0].isr &= ~(1 << 2);
 348             pics[0].irr &= ~(1 << 2);
 349         }
 350         s->irr &= ~(1 << ret);
 351         s->isr &= ~(1 << ret);
 352         if (addr1 >> 7 || ret != 2)
 353             pic_update_irq();
 354     } else {
 355         ret = 0x07;
 356         pic_update_irq();
 357     }
 358
 359     return ret;
 360 }
 361
 362 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 363 {
 364     PicState *s = opaque;
 365     unsigned int addr;
 366     int ret;
 367
 368     addr = addr1;
 369     addr &= 1;
 370     if (s->poll) {
 371         ret = pic_poll_read(s, addr1);
 372         s->poll = 0;
 373     } else {
 374         if (addr == 0) {
 375             if (s->read_reg_select)
 376                 ret = s->isr;
 377             else
 378                 ret = s->irr;
 379         } else {
 380             ret = s->imr;
 381         }
 382     }
 383 #ifdef DEBUG_PIC
 384     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 385 #endif
 386     return ret;
 387 }
 388
 389 /* memory mapped interrupt status */
 390 uint32_t pic_intack_read(CPUState *env)
 391 {
 392     int ret;
 393
 394     ret = pic_poll_read(&pics[0], 0x00);
 395     if (ret == 2)
 396         ret = pic_poll_read(&pics[1], 0x80) + 8;
 397     /* Prepare for ISR read */
 398     pics[0].read_reg_select = 1;
 399
 400     return ret;
 401 }
 402
 403 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 404 {
 405     PicState *s = opaque;
 406     s->elcr = val & s->elcr_mask;
 407 }
 408
 409 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 410 {
 411     PicState *s = opaque;
 412     return s->elcr;
 413 }
 414
 415 static void pic_save(QEMUFile *f, void *opaque)
 416 {
 417     PicState *s = opaque;
 418
 419     qemu_put_8s(f, &s->last_irr);
 420     qemu_put_8s(f, &s->irr);
 421     qemu_put_8s(f, &s->imr);
 422     qemu_put_8s(f, &s->isr);
 423     qemu_put_8s(f, &s->priority_add);
 424     qemu_put_8s(f, &s->irq_base);
 425     qemu_put_8s(f, &s->read_reg_select);
 426     qemu_put_8s(f, &s->poll);
 427     qemu_put_8s(f, &s->special_mask);
 428     qemu_put_8s(f, &s->init_state);
 429     qemu_put_8s(f, &s->auto_eoi);
 430     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 431     qemu_put_8s(f, &s->special_fully_nested_mode);
 432     qemu_put_8s(f, &s->init4);
 433     qemu_put_8s(f, &s->elcr);
 434 }
 435
 436 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 437 {
 438     PicState *s = opaque;
 439
 440     if (version_id != 1)
 441         return -EINVAL;
 442
 443     qemu_get_8s(f, &s->last_irr);
 444     qemu_get_8s(f, &s->irr);
 445     qemu_get_8s(f, &s->imr);
 446     qemu_get_8s(f, &s->isr);
 447     qemu_get_8s(f, &s->priority_add);
 448     qemu_get_8s(f, &s->irq_base);
 449     qemu_get_8s(f, &s->read_reg_select);
 450     qemu_get_8s(f, &s->poll);
 451     qemu_get_8s(f, &s->special_mask);
 452     qemu_get_8s(f, &s->init_state);
 453     qemu_get_8s(f, &s->auto_eoi);
 454     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 455     qemu_get_8s(f, &s->special_fully_nested_mode);
 456     qemu_get_8s(f, &s->init4);
 457     qemu_get_8s(f, &s->elcr);
 458     return 0;
 459 }
 460
 461 /* XXX: add generic master/slave system */
 462 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 463 {
 464     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 465     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 466     if (elcr_addr >= 0) {
 467         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 468         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 469     }
 470     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 471     qemu_register_reset(pic_reset, s);
 472 }
 473
 474 void pic_info(void)
 475 {
 476     int i;
 477     PicState *s;
 478
 479     for(i=0;i<2;i++) {
 480         s = &pics[i];
 481         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 482                     i, s->irr, s->imr, s->isr, s->priority_add,
 483                     s->irq_base, s->read_reg_select, s->elcr,
 484                     s->special_fully_nested_mode);
 485     }
 486 }
 487
 488 void irq_info(void)
 489 {
 490 #ifndef DEBUG_IRQ_COUNT
 491     term_printf("irq statistic code not compiled.\n");
 492 #else
 493     int i;
 494     int64_t count;
 495
 496     term_printf("IRQ statistics:\n");
 497     for (i = 0; i < 16; i++) {
 498         count = irq_count[i];
 499         if (count > 0)
 500             term_printf("%2d: %lld\n", i, count);
 501     }
 502 #endif
 503 }
 504
 505 void pic_init(void)
 506 {
 507     pic_init1(0x20, 0x4d0, &pics[0]);
 508     pic_init1(0xa0, 0x4d1, &pics[1]);
 509     pics[0].elcr_mask = 0xf8;
 510     pics[1].elcr_mask = 0xde;
 511 }
 512