hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug PIC */
  27 //#define DEBUG_PIC
  28
  29 //#define DEBUG_IRQ_LATENCY
  30 //#define DEBUG_IRQ_COUNT
  31
  32 typedef struct PicState {
  33     uint8_t last_irr; /* edge detection */
  34     uint8_t irr; /* interrupt request register */
  35     uint8_t imr; /* interrupt mask register */
  36     uint8_t isr; /* interrupt service register */
  37     uint8_t priority_add; /* highest irq priority */
  38     uint8_t irq_base;
  39     uint8_t read_reg_select;
  40     uint8_t poll;
  41     uint8_t special_mask;
  42     uint8_t init_state;
  43     uint8_t auto_eoi;
  44     uint8_t rotate_on_auto_eoi;
  45     uint8_t special_fully_nested_mode;
  46     uint8_t init4; /* true if 4 byte init */
  47     uint8_t elcr; /* PIIX edge/trigger selection*/
  48     uint8_t elcr_mask;
  49 } PicState;
  50
  51 /* 0 is master pic, 1 is slave pic */
  52 static PicState pics[2];
  53
  54 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  55 static int irq_level[16];
  56 #endif
  57 #ifdef DEBUG_IRQ_COUNT
  58 static uint64_t irq_count[16];
  59 #endif
  60
  61 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  62 static inline void pic_set_irq1(PicState *s, int irq, int level)
  63 {
  64     int mask;
  65     mask = 1 << irq;
  66     if (s->elcr & mask) {
  67         /* level triggered */
  68         if (level) {
  69             s->irr |= mask;
  70             s->last_irr |= mask;
  71         } else {
  72             s->irr &= ~mask;
  73             s->last_irr &= ~mask;
  74         }
  75     } else {
  76         /* edge triggered */
  77         if (level) {
  78             if ((s->last_irr & mask) == 0)
  79                 s->irr |= mask;
  80             s->last_irr |= mask;
  81         } else {
  82             s->last_irr &= ~mask;
  83         }
  84     }
  85 }
  86
  87 /* return the highest priority found in mask (highest = smallest
  88    number). Return 8 if no irq */
  89 static inline int get_priority(PicState *s, int mask)
  90 {
  91     int priority;
  92     if (mask == 0)
  93         return 8;
  94     priority = 0;
  95     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  96         priority++;
  97     return priority;
  98 }
  99
 100 /* return the pic wanted interrupt. return -1 if none */
 101 static int pic_get_irq(PicState *s)
 102 {
 103     int mask, cur_priority, priority;
 104
 105     mask = s->irr & ~s->imr;
 106     priority = get_priority(s, mask);
 107     if (priority == 8)
 108         return -1;
 109     /* compute current priority. If special fully nested mode on the
 110        master, the IRQ coming from the slave is not taken into account
 111        for the priority computation. */
 112     mask = s->isr;
 113     if (s->special_fully_nested_mode && s == &pics[0])
 114         mask &= ~(1 << 2);
 115     cur_priority = get_priority(s, mask);
 116     if (priority < cur_priority) {
 117         /* higher priority found: an irq should be generated */
 118         return (priority + s->priority_add) & 7;
 119     } else {
 120         return -1;
 121     }
 122 }
 123
 124 /* raise irq to CPU if necessary. must be called every time the active
 125    irq may change */
 126 static void pic_update_irq(void)
 127 {
 128     int irq2, irq;
 129
 130     /* first look at slave pic */
 131     irq2 = pic_get_irq(&pics[1]);
 132     if (irq2 >= 0) {
 133         /* if irq request by slave pic, signal master PIC */
 134         pic_set_irq1(&pics[0], 2, 1);
 135         pic_set_irq1(&pics[0], 2, 0);
 136     }
 137     /* look at requested irq */
 138     irq = pic_get_irq(&pics[0]);
 139     if (irq >= 0) {
 140 #if defined(DEBUG_PIC)
 141         {
 142             int i;
 143             for(i = 0; i < 2; i++) {
 144                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 145                        i, pics[i].imr, pics[i].irr, pics[i].priority_add);
 146
 147             }
 148         }
 149         printf("pic: cpu_interrupt\n");
 150 #endif
 151         cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 152     }
 153 }
 154
 155 #ifdef DEBUG_IRQ_LATENCY
 156 int64_t irq_time[16];
 157 #endif
 158
 159 void pic_set_irq(int irq, int level)
 160 {
 161 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 162     if (level != irq_level[irq]) {
 163 #if defined(DEBUG_PIC)
 164         printf("pic_set_irq: irq=%d level=%d\n", irq, level);
 165 #endif
 166         irq_level[irq] = level;
 167 #ifdef DEBUG_IRQ_COUNT
 168         if (level == 1)
 169             irq_count[irq]++;
 170 #endif
 171     }
 172 #endif
 173 #ifdef DEBUG_IRQ_LATENCY
 174     if (level) {
 175         irq_time[irq] = qemu_get_clock(vm_clock);
 176     }
 177 #endif
 178     pic_set_irq1(&pics[irq >> 3], irq & 7, level);
 179     pic_update_irq();
 180 }
 181
 182 /* this function should be used to have the controller context */
 183 void pic_set_irq_new(void *opaque, int irq, int level)
 184 {
 185     pic_set_irq(irq, level);
 186 }
 187
 188 /* acknowledge interrupt 'irq' */
 189 static inline void pic_intack(PicState *s, int irq)
 190 {
 191     if (s->auto_eoi) {
 192         if (s->rotate_on_auto_eoi)
 193             s->priority_add = (irq + 1) & 7;
 194     } else {
 195         s->isr |= (1 << irq);
 196     }
 197     /* We don't clear a level sensitive interrupt here */
 198     if (!(s->elcr & (1 << irq)))
 199         s->irr &= ~(1 << irq);
 200 }
 201
 202 int cpu_get_pic_interrupt(CPUState *env)
 203 {
 204     int irq, irq2, intno;
 205
 206 #ifdef TARGET_X86_64
 207     intno = apic_get_interrupt(env);
 208     if (intno >= 0) {
 209         /* set irq request if a PIC irq is still pending */
 210         /* XXX: improve that */
 211         pic_update_irq();
 212         return intno;
 213     }
 214 #endif
 215     /* read the irq from the PIC */
 216
 217     irq = pic_get_irq(&pics[0]);
 218     if (irq >= 0) {
 219         pic_intack(&pics[0], irq);
 220         if (irq == 2) {
 221             irq2 = pic_get_irq(&pics[1]);
 222             if (irq2 >= 0) {
 223                 pic_intack(&pics[1], irq2);
 224             } else {
 225                 /* spurious IRQ on slave controller */
 226                 irq2 = 7;
 227             }
 228             intno = pics[1].irq_base + irq2;
 229             irq = irq2 + 8;
 230         } else {
 231             intno = pics[0].irq_base + irq;
 232         }
 233     } else {
 234         /* spurious IRQ on host controller */
 235         irq = 7;
 236         intno = pics[0].irq_base + irq;
 237     }
 238     pic_update_irq();
 239
 240 #ifdef DEBUG_IRQ_LATENCY
 241     printf("IRQ%d latency=%0.3fus\n",
 242            irq,
 243            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 244 #endif
 245 #if defined(DEBUG_PIC)
 246     printf("pic_interrupt: irq=%d\n", irq);
 247 #endif
 248     return intno;
 249 }
 250
 251 static void pic_reset(void *opaque)
 252 {
 253     PicState *s = opaque;
 254     int tmp;
 255
 256     tmp = s->elcr_mask;
 257     memset(s, 0, sizeof(PicState));
 258     s->elcr_mask = tmp;
 259 }
 260
 261 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 262 {
 263     PicState *s = opaque;
 264     int priority, cmd, irq;
 265
 266 #ifdef DEBUG_PIC
 267     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 268 #endif
 269     addr &= 1;
 270     if (addr == 0) {
 271         if (val & 0x10) {
 272             /* init */
 273             pic_reset(s);
 274             /* deassert a pending interrupt */
 275             cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 276
 277             s->init_state = 1;
 278             s->init4 = val & 1;
 279             if (val & 0x02)
 280                 hw_error("single mode not supported");
 281             if (val & 0x08)
 282                 hw_error("level sensitive irq not supported");
 283         } else if (val & 0x08) {
 284             if (val & 0x04)
 285                 s->poll = 1;
 286             if (val & 0x02)
 287                 s->read_reg_select = val & 1;
 288             if (val & 0x40)
 289                 s->special_mask = (val >> 5) & 1;
 290         } else {
 291             cmd = val >> 5;
 292             switch(cmd) {
 293             case 0:
 294             case 4:
 295                 s->rotate_on_auto_eoi = cmd >> 2;
 296                 break;
 297             case 1: /* end of interrupt */
 298             case 5:
 299                 priority = get_priority(s, s->isr);
 300                 if (priority != 8) {
 301                     irq = (priority + s->priority_add) & 7;
 302                     s->isr &= ~(1 << irq);
 303                     if (cmd == 5)
 304                         s->priority_add = (irq + 1) & 7;
 305                     pic_update_irq();
 306                 }
 307                 break;
 308             case 3:
 309                 irq = val & 7;
 310                 s->isr &= ~(1 << irq);
 311                 pic_update_irq();
 312                 break;
 313             case 6:
 314                 s->priority_add = (val + 1) & 7;
 315                 pic_update_irq();
 316                 break;
 317             case 7:
 318                 irq = val & 7;
 319                 s->isr &= ~(1 << irq);
 320                 s->priority_add = (irq + 1) & 7;
 321                 pic_update_irq();
 322                 break;
 323             default:
 324                 /* no operation */
 325                 break;
 326             }
 327         }
 328     } else {
 329         switch(s->init_state) {
 330         case 0:
 331             /* normal mode */
 332             s->imr = val;
 333             pic_update_irq();
 334             break;
 335         case 1:
 336             s->irq_base = val & 0xf8;
 337             s->init_state = 2;
 338             break;
 339         case 2:
 340             if (s->init4) {
 341                 s->init_state = 3;
 342             } else {
 343                 s->init_state = 0;
 344             }
 345             break;
 346         case 3:
 347             s->special_fully_nested_mode = (val >> 4) & 1;
 348             s->auto_eoi = (val >> 1) & 1;
 349             s->init_state = 0;
 350             break;
 351         }
 352     }
 353 }
 354
 355 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 356 {
 357     int ret;
 358
 359     ret = pic_get_irq(s);
 360     if (ret >= 0) {
 361         if (addr1 >> 7) {
 362             pics[0].isr &= ~(1 << 2);
 363             pics[0].irr &= ~(1 << 2);
 364         }
 365         s->irr &= ~(1 << ret);
 366         s->isr &= ~(1 << ret);
 367         if (addr1 >> 7 || ret != 2)
 368             pic_update_irq();
 369     } else {
 370         ret = 0x07;
 371         pic_update_irq();
 372     }
 373
 374     return ret;
 375 }
 376
 377 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 378 {
 379     PicState *s = opaque;
 380     unsigned int addr;
 381     int ret;
 382
 383     addr = addr1;
 384     addr &= 1;
 385     if (s->poll) {
 386         ret = pic_poll_read(s, addr1);
 387         s->poll = 0;
 388     } else {
 389         if (addr == 0) {
 390             if (s->read_reg_select)
 391                 ret = s->isr;
 392             else
 393                 ret = s->irr;
 394         } else {
 395             ret = s->imr;
 396         }
 397     }
 398 #ifdef DEBUG_PIC
 399     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 400 #endif
 401     return ret;
 402 }
 403
 404 /* memory mapped interrupt status */
 405 uint32_t pic_intack_read(CPUState *env)
 406 {
 407     int ret;
 408
 409     ret = pic_poll_read(&pics[0], 0x00);
 410     if (ret == 2)
 411         ret = pic_poll_read(&pics[1], 0x80) + 8;
 412     /* Prepare for ISR read */
 413     pics[0].read_reg_select = 1;
 414
 415     return ret;
 416 }
 417
 418 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 419 {
 420     PicState *s = opaque;
 421     s->elcr = val & s->elcr_mask;
 422 }
 423
 424 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 425 {
 426     PicState *s = opaque;
 427     return s->elcr;
 428 }
 429
 430 static void pic_save(QEMUFile *f, void *opaque)
 431 {
 432     PicState *s = opaque;
 433
 434     qemu_put_8s(f, &s->last_irr);
 435     qemu_put_8s(f, &s->irr);
 436     qemu_put_8s(f, &s->imr);
 437     qemu_put_8s(f, &s->isr);
 438     qemu_put_8s(f, &s->priority_add);
 439     qemu_put_8s(f, &s->irq_base);
 440     qemu_put_8s(f, &s->read_reg_select);
 441     qemu_put_8s(f, &s->poll);
 442     qemu_put_8s(f, &s->special_mask);
 443     qemu_put_8s(f, &s->init_state);
 444     qemu_put_8s(f, &s->auto_eoi);
 445     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 446     qemu_put_8s(f, &s->special_fully_nested_mode);
 447     qemu_put_8s(f, &s->init4);
 448     qemu_put_8s(f, &s->elcr);
 449 }
 450
 451 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 452 {
 453     PicState *s = opaque;
 454
 455     if (version_id != 1)
 456         return -EINVAL;
 457
 458     qemu_get_8s(f, &s->last_irr);
 459     qemu_get_8s(f, &s->irr);
 460     qemu_get_8s(f, &s->imr);
 461     qemu_get_8s(f, &s->isr);
 462     qemu_get_8s(f, &s->priority_add);
 463     qemu_get_8s(f, &s->irq_base);
 464     qemu_get_8s(f, &s->read_reg_select);
 465     qemu_get_8s(f, &s->poll);
 466     qemu_get_8s(f, &s->special_mask);
 467     qemu_get_8s(f, &s->init_state);
 468     qemu_get_8s(f, &s->auto_eoi);
 469     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 470     qemu_get_8s(f, &s->special_fully_nested_mode);
 471     qemu_get_8s(f, &s->init4);
 472     qemu_get_8s(f, &s->elcr);
 473     return 0;
 474 }
 475
 476 /* XXX: add generic master/slave system */
 477 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 478 {
 479     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 480     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 481     if (elcr_addr >= 0) {
 482         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 483         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 484     }
 485     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 486     qemu_register_reset(pic_reset, s);
 487 }
 488
 489 void pic_info(void)
 490 {
 491     int i;
 492     PicState *s;
 493
 494     for(i=0;i<2;i++) {
 495         s = &pics[i];
 496         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 497                     i, s->irr, s->imr, s->isr, s->priority_add,
 498                     s->irq_base, s->read_reg_select, s->elcr,
 499                     s->special_fully_nested_mode);
 500     }
 501 }
 502
 503 void irq_info(void)
 504 {
 505 #ifndef DEBUG_IRQ_COUNT
 506     term_printf("irq statistic code not compiled.\n");
 507 #else
 508     int i;
 509     int64_t count;
 510
 511     term_printf("IRQ statistics:\n");
 512     for (i = 0; i < 16; i++) {
 513         count = irq_count[i];
 514         if (count > 0)
 515             term_printf("%2d: %lld\n", i, count);
 516     }
 517 #endif
 518 }
 519
 520 void pic_init(void)
 521 {
 522     pic_init1(0x20, 0x4d0, &pics[0]);
 523     pic_init1(0xa0, 0x4d1, &pics[1]);
 524     pics[0].elcr_mask = 0xf8;
 525     pics[1].elcr_mask = 0xde;
 526 }
 527