2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 //#define DEBUG_IRQ_LATENCY
31 typedef struct PicState
{
32 uint8_t last_irr
; /* edge detection */
33 uint8_t irr
; /* interrupt request register */
34 uint8_t imr
; /* interrupt mask register */
35 uint8_t isr
; /* interrupt service register */
36 uint8_t priority_add
; /* highest irq priority */
38 uint8_t read_reg_select
;
43 uint8_t rotate_on_auto_eoi
;
44 uint8_t special_fully_nested_mode
;
45 uint8_t init4
; /* true if 4 byte init */
46 uint8_t elcr
; /* PIIX edge/trigger selection*/
50 /* 0 is master pic, 1 is slave pic */
51 static PicState pics
[2];
52 static int pic_irq_requested
;
54 /* set irq level. If an edge is detected, then the IRR is set to 1 */
55 static inline void pic_set_irq1(PicState
*s
, int irq
, int level
)
71 if ((s
->last_irr
& mask
) == 0)
80 /* return the highest priority found in mask (highest = smallest
81 number). Return 8 if no irq */
82 static inline int get_priority(PicState
*s
, int mask
)
88 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
93 /* return the pic wanted interrupt. return -1 if none */
94 static int pic_get_irq(PicState
*s
)
96 int mask
, cur_priority
, priority
;
98 mask
= s
->irr
& ~s
->imr
;
99 priority
= get_priority(s
, mask
);
102 /* compute current priority. If special fully nested mode on the
103 master, the IRQ coming from the slave is not taken into account
104 for the priority computation. */
106 if (s
->special_fully_nested_mode
&& s
== &pics
[0])
108 cur_priority
= get_priority(s
, mask
);
109 if (priority
< cur_priority
) {
110 /* higher priority found: an irq should be generated */
111 return (priority
+ s
->priority_add
) & 7;
117 /* raise irq to CPU if necessary. must be called every time the active
119 static void pic_update_irq(void)
123 /* first look at slave pic */
124 irq2
= pic_get_irq(&pics
[1]);
126 /* if irq request by slave pic, signal master PIC */
127 pic_set_irq1(&pics
[0], 2, 1);
128 pic_set_irq1(&pics
[0], 2, 0);
130 /* look at requested irq */
131 irq
= pic_get_irq(&pics
[0]);
135 pic_irq_requested
= 8 + irq2
;
137 /* from master pic */
138 pic_irq_requested
= irq
;
140 #if defined(DEBUG_PIC)
143 for(i
= 0; i
< 2; i
++) {
144 printf("pic%d: imr=%x irr=%x padd=%d\n",
145 i
, pics
[i
].imr
, pics
[i
].irr
, pics
[i
].priority_add
);
149 printf("pic: cpu_interrupt req=%d\n", pic_irq_requested
);
151 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HARD
);
155 #ifdef DEBUG_IRQ_LATENCY
156 int64_t irq_time
[16];
158 #if defined(DEBUG_PIC)
162 void pic_set_irq(int irq
, int level
)
164 #if defined(DEBUG_PIC)
165 if (level
!= irq_level
[irq
]) {
166 printf("pic_set_irq: irq=%d level=%d\n", irq
, level
);
167 irq_level
[irq
] = level
;
170 #ifdef DEBUG_IRQ_LATENCY
172 irq_time
[irq
] = cpu_get_ticks();
175 pic_set_irq1(&pics
[irq
>> 3], irq
& 7, level
);
179 /* acknowledge interrupt 'irq' */
180 static inline void pic_intack(PicState
*s
, int irq
)
183 if (s
->rotate_on_auto_eoi
)
184 s
->priority_add
= (irq
+ 1) & 7;
186 s
->isr
|= (1 << irq
);
188 s
->irr
&= ~(1 << irq
);
191 int cpu_get_pic_interrupt(CPUState
*env
)
193 int irq
, irq2
, intno
;
195 /* signal the pic that the irq was acked by the CPU */
196 irq
= pic_irq_requested
;
197 #ifdef DEBUG_IRQ_LATENCY
198 printf("IRQ%d latency=%0.3fus\n",
200 (double)(cpu_get_ticks() - irq_time
[irq
]) * 1000000.0 / ticks_per_sec
);
202 #if defined(DEBUG_PIC)
203 printf("pic_interrupt: irq=%d\n", irq
);
208 pic_intack(&pics
[1], irq2
);
210 intno
= pics
[1].irq_base
+ irq2
;
212 intno
= pics
[0].irq_base
+ irq
;
214 pic_intack(&pics
[0], irq
);
219 static void pic_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
221 PicState
*s
= opaque
;
222 int priority
, cmd
, irq
, tmp
;
225 printf("pic_write: addr=0x%02x val=0x%02x\n", addr
, val
);
232 memset(s
, 0, sizeof(PicState
));
234 /* deassert a pending interrupt */
235 cpu_reset_interrupt(cpu_single_env
, CPU_INTERRUPT_HARD
);
240 hw_error("single mode not supported");
242 hw_error("level sensitive irq not supported");
243 } else if (val
& 0x08) {
247 s
->read_reg_select
= val
& 1;
249 s
->special_mask
= (val
>> 5) & 1;
255 s
->rotate_on_auto_eoi
= cmd
>> 2;
257 case 1: /* end of interrupt */
259 priority
= get_priority(s
, s
->isr
);
261 irq
= (priority
+ s
->priority_add
) & 7;
262 s
->isr
&= ~(1 << irq
);
264 s
->priority_add
= (irq
+ 1) & 7;
270 s
->isr
&= ~(1 << irq
);
274 s
->priority_add
= (val
+ 1) & 7;
279 s
->isr
&= ~(1 << irq
);
280 s
->priority_add
= (irq
+ 1) & 7;
289 switch(s
->init_state
) {
296 s
->irq_base
= val
& 0xf8;
307 s
->special_fully_nested_mode
= (val
>> 4) & 1;
308 s
->auto_eoi
= (val
>> 1) & 1;
315 static uint32_t pic_poll_read (PicState
*s
, uint32_t addr1
)
319 ret
= pic_get_irq(s
);
322 pics
[0].isr
&= ~(1 << 2);
323 pics
[0].irr
&= ~(1 << 2);
325 s
->irr
&= ~(1 << ret
);
326 s
->isr
&= ~(1 << ret
);
327 if (addr1
>> 7 || ret
!= 2)
337 static uint32_t pic_ioport_read(void *opaque
, uint32_t addr1
)
339 PicState
*s
= opaque
;
346 ret
= pic_poll_read(s
, addr1
);
350 if (s
->read_reg_select
)
359 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1
, ret
);
364 /* memory mapped interrupt status */
365 uint32_t pic_intack_read(CPUState
*env
)
369 ret
= pic_poll_read(&pics
[0], 0x00);
371 ret
= pic_poll_read(&pics
[1], 0x80) + 8;
372 /* Prepare for ISR read */
373 pics
[0].read_reg_select
= 1;
378 static void elcr_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
380 PicState
*s
= opaque
;
381 s
->elcr
= val
& s
->elcr_mask
;
384 static uint32_t elcr_ioport_read(void *opaque
, uint32_t addr1
)
386 PicState
*s
= opaque
;
390 static void pic_save(QEMUFile
*f
, void *opaque
)
392 PicState
*s
= opaque
;
394 qemu_put_8s(f
, &s
->last_irr
);
395 qemu_put_8s(f
, &s
->irr
);
396 qemu_put_8s(f
, &s
->imr
);
397 qemu_put_8s(f
, &s
->isr
);
398 qemu_put_8s(f
, &s
->priority_add
);
399 qemu_put_8s(f
, &s
->irq_base
);
400 qemu_put_8s(f
, &s
->read_reg_select
);
401 qemu_put_8s(f
, &s
->poll
);
402 qemu_put_8s(f
, &s
->special_mask
);
403 qemu_put_8s(f
, &s
->init_state
);
404 qemu_put_8s(f
, &s
->auto_eoi
);
405 qemu_put_8s(f
, &s
->rotate_on_auto_eoi
);
406 qemu_put_8s(f
, &s
->special_fully_nested_mode
);
407 qemu_put_8s(f
, &s
->init4
);
408 qemu_put_8s(f
, &s
->elcr
);
411 static int pic_load(QEMUFile
*f
, void *opaque
, int version_id
)
413 PicState
*s
= opaque
;
418 qemu_get_8s(f
, &s
->last_irr
);
419 qemu_get_8s(f
, &s
->irr
);
420 qemu_get_8s(f
, &s
->imr
);
421 qemu_get_8s(f
, &s
->isr
);
422 qemu_get_8s(f
, &s
->priority_add
);
423 qemu_get_8s(f
, &s
->irq_base
);
424 qemu_get_8s(f
, &s
->read_reg_select
);
425 qemu_get_8s(f
, &s
->poll
);
426 qemu_get_8s(f
, &s
->special_mask
);
427 qemu_get_8s(f
, &s
->init_state
);
428 qemu_get_8s(f
, &s
->auto_eoi
);
429 qemu_get_8s(f
, &s
->rotate_on_auto_eoi
);
430 qemu_get_8s(f
, &s
->special_fully_nested_mode
);
431 qemu_get_8s(f
, &s
->init4
);
432 qemu_get_8s(f
, &s
->elcr
);
436 /* XXX: add generic master/slave system */
437 static void pic_init1(int io_addr
, int elcr_addr
, PicState
*s
)
439 register_ioport_write(io_addr
, 2, 1, pic_ioport_write
, s
);
440 register_ioport_read(io_addr
, 2, 1, pic_ioport_read
, s
);
441 if (elcr_addr
>= 0) {
442 register_ioport_write(elcr_addr
, 1, 1, elcr_ioport_write
, s
);
443 register_ioport_read(elcr_addr
, 1, 1, elcr_ioport_read
, s
);
445 register_savevm("i8259", io_addr
, 1, pic_save
, pic_load
, s
);
455 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x\n",
456 i
, s
->irr
, s
->imr
, s
->isr
, s
->priority_add
,
457 s
->irq_base
, s
->read_reg_select
, s
->elcr
);
464 pic_init1(0x20, 0x4d0, &pics
[0]);
465 pic_init1(0xa0, 0x4d1, &pics
[1]);
466 pics
[0].elcr_mask
= 0xf8;
467 pics
[1].elcr_mask
= 0xde;