hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 /* debug PIC */
  31 //#define DEBUG_PIC
  32
  33 #ifdef DEBUG_PIC
  34 #define DPRINTF(fmt, ...)                                       \
  35     do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 //#define DEBUG_IRQ_LATENCY
  41 //#define DEBUG_IRQ_COUNT
  42
  43 struct PicState {
  44     uint8_t last_irr; /* edge detection */
  45     uint8_t irr; /* interrupt request register */
  46     uint8_t imr; /* interrupt mask register */
  47     uint8_t isr; /* interrupt service register */
  48     uint8_t priority_add; /* highest irq priority */
  49     uint8_t irq_base;
  50     uint8_t read_reg_select;
  51     uint8_t poll;
  52     uint8_t special_mask;
  53     uint8_t init_state;
  54     uint8_t auto_eoi;
  55     uint8_t rotate_on_auto_eoi;
  56     uint8_t special_fully_nested_mode;
  57     uint8_t init4; /* true if 4 byte init */
  58     uint8_t single_mode; /* true if slave pic is not initialized */
  59     uint8_t elcr; /* PIIX edge/trigger selection*/
  60     uint8_t elcr_mask;
  61     qemu_irq int_out;
  62     bool master; /* reflects /SP input pin */
  63     MemoryRegion base_io;
  64     MemoryRegion elcr_io;
  65 };
  66
  67 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  68 static int irq_level[16];
  69 #endif
  70 #ifdef DEBUG_IRQ_COUNT
  71 static uint64_t irq_count[16];
  72 #endif
  73 PicState *isa_pic;
  74 static PicState *slave_pic;
  75
  76 /* return the highest priority found in mask (highest = smallest
  77    number). Return 8 if no irq */
  78 static int get_priority(PicState *s, int mask)
  79 {
  80     int priority;
  81     if (mask == 0)
  82         return 8;
  83     priority = 0;
  84     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  85         priority++;
  86     return priority;
  87 }
  88
  89 /* return the pic wanted interrupt. return -1 if none */
  90 static int pic_get_irq(PicState *s)
  91 {
  92     int mask, cur_priority, priority;
  93
  94     mask = s->irr & ~s->imr;
  95     priority = get_priority(s, mask);
  96     if (priority == 8)
  97         return -1;
  98     /* compute current priority. If special fully nested mode on the
  99        master, the IRQ coming from the slave is not taken into account
 100        for the priority computation. */
 101     mask = s->isr;
 102     if (s->special_mask)
 103         mask &= ~s->imr;
 104     if (s->special_fully_nested_mode && s->master) {
 105         mask &= ~(1 << 2);
 106     }
 107     cur_priority = get_priority(s, mask);
 108     if (priority < cur_priority) {
 109         /* higher priority found: an irq should be generated */
 110         return (priority + s->priority_add) & 7;
 111     } else {
 112         return -1;
 113     }
 114 }
 115
 116 /* Update INT output. Must be called every time the output may have changed. */
 117 static void pic_update_irq(PicState *s)
 118 {
 119     int irq;
 120
 121     irq = pic_get_irq(s);
 122     if (irq >= 0) {
 123         DPRINTF("pic%d: imr=%x irr=%x padd=%d\n",
 124                 s->master ? 0 : 1, s->imr, s->irr, s->priority_add);
 125         qemu_irq_raise(s->int_out);
 126     } else {
 127         qemu_irq_lower(s->int_out);
 128     }
 129 }
 130
 131 /* set irq level. If an edge is detected, then the IRR is set to 1 */
 132 static void pic_set_irq1(PicState *s, int irq, int level)
 133 {
 134     int mask;
 135     mask = 1 << irq;
 136     if (s->elcr & mask) {
 137         /* level triggered */
 138         if (level) {
 139             s->irr |= mask;
 140             s->last_irr |= mask;
 141         } else {
 142             s->irr &= ~mask;
 143             s->last_irr &= ~mask;
 144         }
 145     } else {
 146         /* edge triggered */
 147         if (level) {
 148             if ((s->last_irr & mask) == 0) {
 149                 s->irr |= mask;
 150             }
 151             s->last_irr |= mask;
 152         } else {
 153             s->last_irr &= ~mask;
 154         }
 155     }
 156     pic_update_irq(s);
 157 }
 158
 159 #ifdef DEBUG_IRQ_LATENCY
 160 int64_t irq_time[16];
 161 #endif
 162
 163 static void i8259_set_irq(void *opaque, int irq, int level)
 164 {
 165     PicState *s = irq <= 7 ? isa_pic : slave_pic;
 166
 167 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 168     if (level != irq_level[irq]) {
 169         DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
 170         irq_level[irq] = level;
 171 #ifdef DEBUG_IRQ_COUNT
 172         if (level == 1)
 173             irq_count[irq]++;
 174 #endif
 175     }
 176 #endif
 177 #ifdef DEBUG_IRQ_LATENCY
 178     if (level) {
 179         irq_time[irq] = qemu_get_clock_ns(vm_clock);
 180     }
 181 #endif
 182     pic_set_irq1(s, irq & 7, level);
 183 }
 184
 185 /* acknowledge interrupt 'irq' */
 186 static void pic_intack(PicState *s, int irq)
 187 {
 188     if (s->auto_eoi) {
 189         if (s->rotate_on_auto_eoi)
 190             s->priority_add = (irq + 1) & 7;
 191     } else {
 192         s->isr |= (1 << irq);
 193     }
 194     /* We don't clear a level sensitive interrupt here */
 195     if (!(s->elcr & (1 << irq)))
 196         s->irr &= ~(1 << irq);
 197     pic_update_irq(s);
 198 }
 199
 200 int pic_read_irq(PicState *s)
 201 {
 202     int irq, irq2, intno;
 203
 204     irq = pic_get_irq(s);
 205     if (irq >= 0) {
 206         if (irq == 2) {
 207             irq2 = pic_get_irq(slave_pic);
 208             if (irq2 >= 0) {
 209                 pic_intack(slave_pic, irq2);
 210             } else {
 211                 /* spurious IRQ on slave controller */
 212                 irq2 = 7;
 213             }
 214             intno = slave_pic->irq_base + irq2;
 215         } else {
 216             intno = s->irq_base + irq;
 217         }
 218         pic_intack(s, irq);
 219     } else {
 220         /* spurious IRQ on host controller */
 221         irq = 7;
 222         intno = s->irq_base + irq;
 223     }
 224
 225 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
 226     if (irq == 2) {
 227         irq = irq2 + 8;
 228     }
 229 #endif
 230 #ifdef DEBUG_IRQ_LATENCY
 231     printf("IRQ%d latency=%0.3fus\n",
 232            irq,
 233            (double)(qemu_get_clock_ns(vm_clock) -
 234                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 235 #endif
 236     DPRINTF("pic_interrupt: irq=%d\n", irq);
 237     return intno;
 238 }
 239
 240 static void pic_init_reset(PicState *s)
 241 {
 242     s->last_irr = 0;
 243     s->irr = 0;
 244     s->imr = 0;
 245     s->isr = 0;
 246     s->priority_add = 0;
 247     s->irq_base = 0;
 248     s->read_reg_select = 0;
 249     s->poll = 0;
 250     s->special_mask = 0;
 251     s->init_state = 0;
 252     s->auto_eoi = 0;
 253     s->rotate_on_auto_eoi = 0;
 254     s->special_fully_nested_mode = 0;
 255     s->init4 = 0;
 256     s->single_mode = 0;
 257     /* Note: ELCR is not reset */
 258     pic_update_irq(s);
 259 }
 260
 261 static void pic_reset(void *opaque)
 262 {
 263     PicState *s = opaque;
 264
 265     pic_init_reset(s);
 266     s->elcr = 0;
 267 }
 268
 269 static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
 270                              uint64_t val64, unsigned size)
 271 {
 272     PicState *s = opaque;
 273     uint32_t addr = addr64;
 274     uint32_t val = val64;
 275     int priority, cmd, irq;
 276
 277     DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
 278     if (addr == 0) {
 279         if (val & 0x10) {
 280             pic_init_reset(s);
 281             s->init_state = 1;
 282             s->init4 = val & 1;
 283             s->single_mode = val & 2;
 284             if (val & 0x08)
 285                 hw_error("level sensitive irq not supported");
 286         } else if (val & 0x08) {
 287             if (val & 0x04)
 288                 s->poll = 1;
 289             if (val & 0x02)
 290                 s->read_reg_select = val & 1;
 291             if (val & 0x40)
 292                 s->special_mask = (val >> 5) & 1;
 293         } else {
 294             cmd = val >> 5;
 295             switch(cmd) {
 296             case 0:
 297             case 4:
 298                 s->rotate_on_auto_eoi = cmd >> 2;
 299                 break;
 300             case 1: /* end of interrupt */
 301             case 5:
 302                 priority = get_priority(s, s->isr);
 303                 if (priority != 8) {
 304                     irq = (priority + s->priority_add) & 7;
 305                     s->isr &= ~(1 << irq);
 306                     if (cmd == 5)
 307                         s->priority_add = (irq + 1) & 7;
 308                     pic_update_irq(s);
 309                 }
 310                 break;
 311             case 3:
 312                 irq = val & 7;
 313                 s->isr &= ~(1 << irq);
 314                 pic_update_irq(s);
 315                 break;
 316             case 6:
 317                 s->priority_add = (val + 1) & 7;
 318                 pic_update_irq(s);
 319                 break;
 320             case 7:
 321                 irq = val & 7;
 322                 s->isr &= ~(1 << irq);
 323                 s->priority_add = (irq + 1) & 7;
 324                 pic_update_irq(s);
 325                 break;
 326             default:
 327                 /* no operation */
 328                 break;
 329             }
 330         }
 331     } else {
 332         switch(s->init_state) {
 333         case 0:
 334             /* normal mode */
 335             s->imr = val;
 336             pic_update_irq(s);
 337             break;
 338         case 1:
 339             s->irq_base = val & 0xf8;
 340             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 341             break;
 342         case 2:
 343             if (s->init4) {
 344                 s->init_state = 3;
 345             } else {
 346                 s->init_state = 0;
 347             }
 348             break;
 349         case 3:
 350             s->special_fully_nested_mode = (val >> 4) & 1;
 351             s->auto_eoi = (val >> 1) & 1;
 352             s->init_state = 0;
 353             break;
 354         }
 355     }
 356 }
 357
 358 static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
 359                                 unsigned size)
 360 {
 361     PicState *s = opaque;
 362     int ret;
 363
 364     if (s->poll) {
 365         ret = pic_get_irq(s);
 366         if (ret >= 0) {
 367             pic_intack(s, ret);
 368             ret |= 0x80;
 369         } else {
 370             ret = 0;
 371         }
 372         s->poll = 0;
 373     } else {
 374         if (addr == 0) {
 375             if (s->read_reg_select)
 376                 ret = s->isr;
 377             else
 378                 ret = s->irr;
 379         } else {
 380             ret = s->imr;
 381         }
 382     }
 383     DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
 384     return ret;
 385 }
 386
 387 int pic_get_output(PicState *s)
 388 {
 389     return (pic_get_irq(s) >= 0);
 390 }
 391
 392 static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
 393                               uint64_t val, unsigned size)
 394 {
 395     PicState *s = opaque;
 396     s->elcr = val & s->elcr_mask;
 397 }
 398
 399 static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
 400                                  unsigned size)
 401 {
 402     PicState *s = opaque;
 403     return s->elcr;
 404 }
 405
 406 static const VMStateDescription vmstate_pic = {
 407     .name = "i8259",
 408     .version_id = 1,
 409     .minimum_version_id = 1,
 410     .minimum_version_id_old = 1,
 411     .fields      = (VMStateField []) {
 412         VMSTATE_UINT8(last_irr, PicState),
 413         VMSTATE_UINT8(irr, PicState),
 414         VMSTATE_UINT8(imr, PicState),
 415         VMSTATE_UINT8(isr, PicState),
 416         VMSTATE_UINT8(priority_add, PicState),
 417         VMSTATE_UINT8(irq_base, PicState),
 418         VMSTATE_UINT8(read_reg_select, PicState),
 419         VMSTATE_UINT8(poll, PicState),
 420         VMSTATE_UINT8(special_mask, PicState),
 421         VMSTATE_UINT8(init_state, PicState),
 422         VMSTATE_UINT8(auto_eoi, PicState),
 423         VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
 424         VMSTATE_UINT8(special_fully_nested_mode, PicState),
 425         VMSTATE_UINT8(init4, PicState),
 426         VMSTATE_UINT8(single_mode, PicState),
 427         VMSTATE_UINT8(elcr, PicState),
 428         VMSTATE_END_OF_LIST()
 429     }
 430 };
 431
 432 static const MemoryRegionOps pic_base_ioport_ops = {
 433     .read = pic_ioport_read,
 434     .write = pic_ioport_write,
 435     .impl = {
 436         .min_access_size = 1,
 437         .max_access_size = 1,
 438     },
 439 };
 440
 441 static const MemoryRegionOps pic_elcr_ioport_ops = {
 442     .read = elcr_ioport_read,
 443     .write = elcr_ioport_write,
 444     .impl = {
 445         .min_access_size = 1,
 446         .max_access_size = 1,
 447     },
 448 };
 449
 450 /* XXX: add generic master/slave system */
 451 static void pic_init(int io_addr, int elcr_addr, PicState *s, qemu_irq int_out,
 452                      bool master)
 453 {
 454     s->int_out = int_out;
 455     s->master = master;
 456
 457     memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
 458     memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
 459
 460     isa_register_ioport(NULL, &s->base_io, io_addr);
 461     if (elcr_addr >= 0) {
 462         isa_register_ioport(NULL, &s->elcr_io, elcr_addr);
 463     }
 464
 465     vmstate_register(NULL, io_addr, &vmstate_pic, s);
 466     qemu_register_reset(pic_reset, s);
 467 }
 468
 469 void pic_info(Monitor *mon)
 470 {
 471     int i;
 472     PicState *s;
 473
 474     if (!isa_pic)
 475         return;
 476
 477     for (i = 0; i < 2; i++) {
 478         s = i == 0 ? isa_pic : slave_pic;
 479         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 480                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 481                        i, s->irr, s->imr, s->isr, s->priority_add,
 482                        s->irq_base, s->read_reg_select, s->elcr,
 483                        s->special_fully_nested_mode);
 484     }
 485 }
 486
 487 void irq_info(Monitor *mon)
 488 {
 489 #ifndef DEBUG_IRQ_COUNT
 490     monitor_printf(mon, "irq statistic code not compiled.\n");
 491 #else
 492     int i;
 493     int64_t count;
 494
 495     monitor_printf(mon, "IRQ statistics:\n");
 496     for (i = 0; i < 16; i++) {
 497         count = irq_count[i];
 498         if (count > 0)
 499             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 500     }
 501 #endif
 502 }
 503
 504 qemu_irq *i8259_init(qemu_irq parent_irq)
 505 {
 506     qemu_irq *irqs;
 507     PicState *s;
 508
 509     irqs = qemu_allocate_irqs(i8259_set_irq, NULL, 16);
 510
 511     s = g_malloc0(sizeof(PicState));
 512     pic_init(0x20, 0x4d0, s, parent_irq, true);
 513     s->elcr_mask = 0xf8;
 514     isa_pic = s;
 515
 516     s = g_malloc0(sizeof(PicState));
 517     pic_init(0xa0, 0x4d1, s, irqs[2], false);
 518     s->elcr_mask = 0xde;
 519     slave_pic = s;
 520
 521     return irqs;
 522 }