hw/ide/ahci.c

   1 /*
   2  * QEMU AHCI Emulation
   3  *
   4  * Copyright (c) 2010 qiaochong@loongson.cn
   5  * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
   6  * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
   7  * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23
  24 #include <hw/hw.h>
  25 #include <hw/pci/msi.h>
  26 #include <hw/pc.h>
  27 #include <hw/pci/pci.h>
  28 #include <hw/sysbus.h>
  29
  30 #include "monitor/monitor.h"
  31 #include "dma.h"
  32 #include "exec/cpu-common.h"
  33 #include "internal.h"
  34 #include <hw/ide/pci.h>
  35 #include <hw/ide/ahci.h>
  36
  37 /* #define DEBUG_AHCI */
  38
  39 #ifdef DEBUG_AHCI
  40 #define DPRINTF(port, fmt, ...) \
  41 do { fprintf(stderr, "ahci: %s: [%d] ", __FUNCTION__, port); \
  42      fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  43 #else
  44 #define DPRINTF(port, fmt, ...) do {} while(0)
  45 #endif
  46
  47 static void check_cmd(AHCIState *s, int port);
  48 static int handle_cmd(AHCIState *s,int port,int slot);
  49 static void ahci_reset_port(AHCIState *s, int port);
  50 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis);
  51 static void ahci_init_d2h(AHCIDevice *ad);
  52
  53 static uint32_t  ahci_port_read(AHCIState *s, int port, int offset)
  54 {
  55     uint32_t val;
  56     AHCIPortRegs *pr;
  57     pr = &s->dev[port].port_regs;
  58
  59     switch (offset) {
  60     case PORT_LST_ADDR:
  61         val = pr->lst_addr;
  62         break;
  63     case PORT_LST_ADDR_HI:
  64         val = pr->lst_addr_hi;
  65         break;
  66     case PORT_FIS_ADDR:
  67         val = pr->fis_addr;
  68         break;
  69     case PORT_FIS_ADDR_HI:
  70         val = pr->fis_addr_hi;
  71         break;
  72     case PORT_IRQ_STAT:
  73         val = pr->irq_stat;
  74         break;
  75     case PORT_IRQ_MASK:
  76         val = pr->irq_mask;
  77         break;
  78     case PORT_CMD:
  79         val = pr->cmd;
  80         break;
  81     case PORT_TFDATA:
  82         val = ((uint16_t)s->dev[port].port.ifs[0].error << 8) |
  83               s->dev[port].port.ifs[0].status;
  84         break;
  85     case PORT_SIG:
  86         val = pr->sig;
  87         break;
  88     case PORT_SCR_STAT:
  89         if (s->dev[port].port.ifs[0].bs) {
  90             val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
  91                   SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
  92         } else {
  93             val = SATA_SCR_SSTATUS_DET_NODEV;
  94         }
  95         break;
  96     case PORT_SCR_CTL:
  97         val = pr->scr_ctl;
  98         break;
  99     case PORT_SCR_ERR:
 100         val = pr->scr_err;
 101         break;
 102     case PORT_SCR_ACT:
 103         pr->scr_act &= ~s->dev[port].finished;
 104         s->dev[port].finished = 0;
 105         val = pr->scr_act;
 106         break;
 107     case PORT_CMD_ISSUE:
 108         val = pr->cmd_issue;
 109         break;
 110     case PORT_RESERVED:
 111     default:
 112         val = 0;
 113     }
 114     DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
 115     return val;
 116
 117 }
 118
 119 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
 120 {
 121     struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
 122
 123     DPRINTF(0, "raise irq\n");
 124
 125     if (msi_enabled(&d->card)) {
 126         msi_notify(&d->card, 0);
 127     } else {
 128         qemu_irq_raise(s->irq);
 129     }
 130 }
 131
 132 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
 133 {
 134     struct AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
 135
 136     DPRINTF(0, "lower irq\n");
 137
 138     if (!msi_enabled(&d->card)) {
 139         qemu_irq_lower(s->irq);
 140     }
 141 }
 142
 143 static void ahci_check_irq(AHCIState *s)
 144 {
 145     int i;
 146
 147     DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus);
 148
 149     s->control_regs.irqstatus = 0;
 150     for (i = 0; i < s->ports; i++) {
 151         AHCIPortRegs *pr = &s->dev[i].port_regs;
 152         if (pr->irq_stat & pr->irq_mask) {
 153             s->control_regs.irqstatus |= (1 << i);
 154         }
 155     }
 156
 157     if (s->control_regs.irqstatus &&
 158         (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
 159             ahci_irq_raise(s, NULL);
 160     } else {
 161         ahci_irq_lower(s, NULL);
 162     }
 163 }
 164
 165 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
 166                              int irq_type)
 167 {
 168     DPRINTF(d->port_no, "trigger irq %#x -> %x\n",
 169             irq_type, d->port_regs.irq_mask & irq_type);
 170
 171     d->port_regs.irq_stat |= irq_type;
 172     ahci_check_irq(s);
 173 }
 174
 175 static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted)
 176 {
 177     hwaddr len = wanted;
 178
 179     if (*ptr) {
 180         cpu_physical_memory_unmap(*ptr, len, 1, len);
 181     }
 182
 183     *ptr = cpu_physical_memory_map(addr, &len, 1);
 184     if (len < wanted) {
 185         cpu_physical_memory_unmap(*ptr, len, 1, len);
 186         *ptr = NULL;
 187     }
 188 }
 189
 190 static void  ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
 191 {
 192     AHCIPortRegs *pr = &s->dev[port].port_regs;
 193
 194     DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
 195     switch (offset) {
 196         case PORT_LST_ADDR:
 197             pr->lst_addr = val;
 198             map_page(&s->dev[port].lst,
 199                      ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
 200             s->dev[port].cur_cmd = NULL;
 201             break;
 202         case PORT_LST_ADDR_HI:
 203             pr->lst_addr_hi = val;
 204             map_page(&s->dev[port].lst,
 205                      ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
 206             s->dev[port].cur_cmd = NULL;
 207             break;
 208         case PORT_FIS_ADDR:
 209             pr->fis_addr = val;
 210             map_page(&s->dev[port].res_fis,
 211                      ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
 212             break;
 213         case PORT_FIS_ADDR_HI:
 214             pr->fis_addr_hi = val;
 215             map_page(&s->dev[port].res_fis,
 216                      ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
 217             break;
 218         case PORT_IRQ_STAT:
 219             pr->irq_stat &= ~val;
 220             ahci_check_irq(s);
 221             break;
 222         case PORT_IRQ_MASK:
 223             pr->irq_mask = val & 0xfdc000ff;
 224             ahci_check_irq(s);
 225             break;
 226         case PORT_CMD:
 227             pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
 228
 229             if (pr->cmd & PORT_CMD_START) {
 230                 pr->cmd |= PORT_CMD_LIST_ON;
 231             }
 232
 233             if (pr->cmd & PORT_CMD_FIS_RX) {
 234                 pr->cmd |= PORT_CMD_FIS_ON;
 235             }
 236
 237             /* XXX usually the FIS would be pending on the bus here and
 238                    issuing deferred until the OS enables FIS receival.
 239                    Instead, we only submit it once - which works in most
 240                    cases, but is a hack. */
 241             if ((pr->cmd & PORT_CMD_FIS_ON) &&
 242                 !s->dev[port].init_d2h_sent) {
 243                 ahci_init_d2h(&s->dev[port]);
 244                 s->dev[port].init_d2h_sent = 1;
 245             }
 246
 247             check_cmd(s, port);
 248             break;
 249         case PORT_TFDATA:
 250             s->dev[port].port.ifs[0].error = (val >> 8) & 0xff;
 251             s->dev[port].port.ifs[0].status = val & 0xff;
 252             break;
 253         case PORT_SIG:
 254             pr->sig = val;
 255             break;
 256         case PORT_SCR_STAT:
 257             pr->scr_stat = val;
 258             break;
 259         case PORT_SCR_CTL:
 260             if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
 261                 ((val & AHCI_SCR_SCTL_DET) == 0)) {
 262                 ahci_reset_port(s, port);
 263             }
 264             pr->scr_ctl = val;
 265             break;
 266         case PORT_SCR_ERR:
 267             pr->scr_err &= ~val;
 268             break;
 269         case PORT_SCR_ACT:
 270             /* RW1 */
 271             pr->scr_act |= val;
 272             break;
 273         case PORT_CMD_ISSUE:
 274             pr->cmd_issue |= val;
 275             check_cmd(s, port);
 276             break;
 277         default:
 278             break;
 279     }
 280 }
 281
 282 static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
 283                               unsigned size)
 284 {
 285     AHCIState *s = opaque;
 286     uint32_t val = 0;
 287
 288     if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
 289         switch (addr) {
 290         case HOST_CAP:
 291             val = s->control_regs.cap;
 292             break;
 293         case HOST_CTL:
 294             val = s->control_regs.ghc;
 295             break;
 296         case HOST_IRQ_STAT:
 297             val = s->control_regs.irqstatus;
 298             break;
 299         case HOST_PORTS_IMPL:
 300             val = s->control_regs.impl;
 301             break;
 302         case HOST_VERSION:
 303             val = s->control_regs.version;
 304             break;
 305         }
 306
 307         DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val);
 308     } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
 309                (addr < (AHCI_PORT_REGS_START_ADDR +
 310                 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
 311         val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
 312                              addr & AHCI_PORT_ADDR_OFFSET_MASK);
 313     }
 314
 315     return val;
 316 }
 317
 318
 319
 320 static void ahci_mem_write(void *opaque, hwaddr addr,
 321                            uint64_t val, unsigned size)
 322 {
 323     AHCIState *s = opaque;
 324
 325     /* Only aligned reads are allowed on AHCI */
 326     if (addr & 3) {
 327         fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
 328                 TARGET_FMT_plx "\n", addr);
 329         return;
 330     }
 331
 332     if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
 333         DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val);
 334
 335         switch (addr) {
 336             case HOST_CAP: /* R/WO, RO */
 337                 /* FIXME handle R/WO */
 338                 break;
 339             case HOST_CTL: /* R/W */
 340                 if (val & HOST_CTL_RESET) {
 341                     DPRINTF(-1, "HBA Reset\n");
 342                     ahci_reset(s);
 343                 } else {
 344                     s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
 345                     ahci_check_irq(s);
 346                 }
 347                 break;
 348             case HOST_IRQ_STAT: /* R/WC, RO */
 349                 s->control_regs.irqstatus &= ~val;
 350                 ahci_check_irq(s);
 351                 break;
 352             case HOST_PORTS_IMPL: /* R/WO, RO */
 353                 /* FIXME handle R/WO */
 354                 break;
 355             case HOST_VERSION: /* RO */
 356                 /* FIXME report write? */
 357                 break;
 358             default:
 359                 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr);
 360         }
 361     } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
 362                (addr < (AHCI_PORT_REGS_START_ADDR +
 363                 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
 364         ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
 365                         addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
 366     }
 367
 368 }
 369
 370 static const MemoryRegionOps ahci_mem_ops = {
 371     .read = ahci_mem_read,
 372     .write = ahci_mem_write,
 373     .endianness = DEVICE_LITTLE_ENDIAN,
 374 };
 375
 376 static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
 377                               unsigned size)
 378 {
 379     AHCIState *s = opaque;
 380
 381     if (addr == s->idp_offset) {
 382         /* index register */
 383         return s->idp_index;
 384     } else if (addr == s->idp_offset + 4) {
 385         /* data register - do memory read at location selected by index */
 386         return ahci_mem_read(opaque, s->idp_index, size);
 387     } else {
 388         return 0;
 389     }
 390 }
 391
 392 static void ahci_idp_write(void *opaque, hwaddr addr,
 393                            uint64_t val, unsigned size)
 394 {
 395     AHCIState *s = opaque;
 396
 397     if (addr == s->idp_offset) {
 398         /* index register - mask off reserved bits */
 399         s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3);
 400     } else if (addr == s->idp_offset + 4) {
 401         /* data register - do memory write at location selected by index */
 402         ahci_mem_write(opaque, s->idp_index, val, size);
 403     }
 404 }
 405
 406 static const MemoryRegionOps ahci_idp_ops = {
 407     .read = ahci_idp_read,
 408     .write = ahci_idp_write,
 409     .endianness = DEVICE_LITTLE_ENDIAN,
 410 };
 411
 412
 413 static void ahci_reg_init(AHCIState *s)
 414 {
 415     int i;
 416
 417     s->control_regs.cap = (s->ports - 1) |
 418                           (AHCI_NUM_COMMAND_SLOTS << 8) |
 419                           (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) |
 420                           HOST_CAP_NCQ | HOST_CAP_AHCI;
 421
 422     s->control_regs.impl = (1 << s->ports) - 1;
 423
 424     s->control_regs.version = AHCI_VERSION_1_0;
 425
 426     for (i = 0; i < s->ports; i++) {
 427         s->dev[i].port_state = STATE_RUN;
 428     }
 429 }
 430
 431 static void check_cmd(AHCIState *s, int port)
 432 {
 433     AHCIPortRegs *pr = &s->dev[port].port_regs;
 434     int slot;
 435
 436     if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {
 437         for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
 438             if ((pr->cmd_issue & (1 << slot)) &&
 439                 !handle_cmd(s, port, slot)) {
 440                 pr->cmd_issue &= ~(1 << slot);
 441             }
 442         }
 443     }
 444 }
 445
 446 static void ahci_check_cmd_bh(void *opaque)
 447 {
 448     AHCIDevice *ad = opaque;
 449
 450     qemu_bh_delete(ad->check_bh);
 451     ad->check_bh = NULL;
 452
 453     if ((ad->busy_slot != -1) &&
 454         !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) {
 455         /* no longer busy */
 456         ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
 457         ad->busy_slot = -1;
 458     }
 459
 460     check_cmd(ad->hba, ad->port_no);
 461 }
 462
 463 static void ahci_init_d2h(AHCIDevice *ad)
 464 {
 465     uint8_t init_fis[20];
 466     IDEState *ide_state = &ad->port.ifs[0];
 467
 468     memset(init_fis, 0, sizeof(init_fis));
 469
 470     init_fis[4] = 1;
 471     init_fis[12] = 1;
 472
 473     if (ide_state->drive_kind == IDE_CD) {
 474         init_fis[5] = ide_state->lcyl;
 475         init_fis[6] = ide_state->hcyl;
 476     }
 477
 478     ahci_write_fis_d2h(ad, init_fis);
 479 }
 480
 481 static void ahci_reset_port(AHCIState *s, int port)
 482 {
 483     AHCIDevice *d = &s->dev[port];
 484     AHCIPortRegs *pr = &d->port_regs;
 485     IDEState *ide_state = &d->port.ifs[0];
 486     int i;
 487
 488     DPRINTF(port, "reset port\n");
 489
 490     ide_bus_reset(&d->port);
 491     ide_state->ncq_queues = AHCI_MAX_CMDS;
 492
 493     pr->scr_stat = 0;
 494     pr->scr_err = 0;
 495     pr->scr_act = 0;
 496     d->busy_slot = -1;
 497     d->init_d2h_sent = 0;
 498
 499     ide_state = &s->dev[port].port.ifs[0];
 500     if (!ide_state->bs) {
 501         return;
 502     }
 503
 504     /* reset ncq queue */
 505     for (i = 0; i < AHCI_MAX_CMDS; i++) {
 506         NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i];
 507         if (!ncq_tfs->used) {
 508             continue;
 509         }
 510
 511         if (ncq_tfs->aiocb) {
 512             bdrv_aio_cancel(ncq_tfs->aiocb);
 513             ncq_tfs->aiocb = NULL;
 514         }
 515
 516         /* Maybe we just finished the request thanks to bdrv_aio_cancel() */
 517         if (!ncq_tfs->used) {
 518             continue;
 519         }
 520
 521         qemu_sglist_destroy(&ncq_tfs->sglist);
 522         ncq_tfs->used = 0;
 523     }
 524
 525     s->dev[port].port_state = STATE_RUN;
 526     if (!ide_state->bs) {
 527         s->dev[port].port_regs.sig = 0;
 528         ide_state->status = SEEK_STAT | WRERR_STAT;
 529     } else if (ide_state->drive_kind == IDE_CD) {
 530         s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM;
 531         ide_state->lcyl = 0x14;
 532         ide_state->hcyl = 0xeb;
 533         DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl);
 534         ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
 535     } else {
 536         s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK;
 537         ide_state->status = SEEK_STAT | WRERR_STAT;
 538     }
 539
 540     ide_state->error = 1;
 541     ahci_init_d2h(d);
 542 }
 543
 544 static void debug_print_fis(uint8_t *fis, int cmd_len)
 545 {
 546 #ifdef DEBUG_AHCI
 547     int i;
 548
 549     fprintf(stderr, "fis:");
 550     for (i = 0; i < cmd_len; i++) {
 551         if ((i & 0xf) == 0) {
 552             fprintf(stderr, "\n%02x:",i);
 553         }
 554         fprintf(stderr, "%02x ",fis[i]);
 555     }
 556     fprintf(stderr, "\n");
 557 #endif
 558 }
 559
 560 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)
 561 {
 562     AHCIPortRegs *pr = &s->dev[port].port_regs;
 563     IDEState *ide_state;
 564     uint8_t *sdb_fis;
 565
 566     if (!s->dev[port].res_fis ||
 567         !(pr->cmd & PORT_CMD_FIS_RX)) {
 568         return;
 569     }
 570
 571     sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS];
 572     ide_state = &s->dev[port].port.ifs[0];
 573
 574     /* clear memory */
 575     *(uint32_t*)sdb_fis = 0;
 576
 577     /* write values */
 578     sdb_fis[0] = ide_state->error;
 579     sdb_fis[2] = ide_state->status & 0x77;
 580     s->dev[port].finished |= finished;
 581     *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished);
 582
 583     ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_SDBS);
 584 }
 585
 586 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis)
 587 {
 588     AHCIPortRegs *pr = &ad->port_regs;
 589     uint8_t *d2h_fis;
 590     int i;
 591     dma_addr_t cmd_len = 0x80;
 592     int cmd_mapped = 0;
 593
 594     if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
 595         return;
 596     }
 597
 598     if (!cmd_fis) {
 599         /* map cmd_fis */
 600         uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);
 601         cmd_fis = dma_memory_map(ad->hba->dma, tbl_addr, &cmd_len,
 602                                  DMA_DIRECTION_TO_DEVICE);
 603         cmd_mapped = 1;
 604     }
 605
 606     d2h_fis = &ad->res_fis[RES_FIS_RFIS];
 607
 608     d2h_fis[0] = 0x34;
 609     d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
 610     d2h_fis[2] = ad->port.ifs[0].status;
 611     d2h_fis[3] = ad->port.ifs[0].error;
 612
 613     d2h_fis[4] = cmd_fis[4];
 614     d2h_fis[5] = cmd_fis[5];
 615     d2h_fis[6] = cmd_fis[6];
 616     d2h_fis[7] = cmd_fis[7];
 617     d2h_fis[8] = cmd_fis[8];
 618     d2h_fis[9] = cmd_fis[9];
 619     d2h_fis[10] = cmd_fis[10];
 620     d2h_fis[11] = cmd_fis[11];
 621     d2h_fis[12] = cmd_fis[12];
 622     d2h_fis[13] = cmd_fis[13];
 623     for (i = 14; i < 20; i++) {
 624         d2h_fis[i] = 0;
 625     }
 626
 627     if (d2h_fis[2] & ERR_STAT) {
 628         ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_TFES);
 629     }
 630
 631     ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);
 632
 633     if (cmd_mapped) {
 634         dma_memory_unmap(ad->hba->dma, cmd_fis, cmd_len,
 635                          DMA_DIRECTION_TO_DEVICE, cmd_len);
 636     }
 637 }
 638
 639 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, int offset)
 640 {
 641     AHCICmdHdr *cmd = ad->cur_cmd;
 642     uint32_t opts = le32_to_cpu(cmd->opts);
 643     uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80;
 644     int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN;
 645     dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG));
 646     dma_addr_t real_prdt_len = prdt_len;
 647     uint8_t *prdt;
 648     int i;
 649     int r = 0;
 650     int sum = 0;
 651     int off_idx = -1;
 652     int off_pos = -1;
 653     int tbl_entry_size;
 654
 655     if (!sglist_alloc_hint) {
 656         DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts);
 657         return -1;
 658     }
 659
 660     /* map PRDT */
 661     if (!(prdt = dma_memory_map(ad->hba->dma, prdt_addr, &prdt_len,
 662                                 DMA_DIRECTION_TO_DEVICE))){
 663         DPRINTF(ad->port_no, "map failed\n");
 664         return -1;
 665     }
 666
 667     if (prdt_len < real_prdt_len) {
 668         DPRINTF(ad->port_no, "mapped less than expected\n");
 669         r = -1;
 670         goto out;
 671     }
 672
 673     /* Get entries in the PRDT, init a qemu sglist accordingly */
 674     if (sglist_alloc_hint > 0) {
 675         AHCI_SG *tbl = (AHCI_SG *)prdt;
 676         sum = 0;
 677         for (i = 0; i < sglist_alloc_hint; i++) {
 678             /* flags_size is zero-based */
 679             tbl_entry_size = (le32_to_cpu(tbl[i].flags_size) + 1);
 680             if (offset <= (sum + tbl_entry_size)) {
 681                 off_idx = i;
 682                 off_pos = offset - sum;
 683                 break;
 684             }
 685             sum += tbl_entry_size;
 686         }
 687         if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) {
 688             DPRINTF(ad->port_no, "%s: Incorrect offset! "
 689                             "off_idx: %d, off_pos: %d\n",
 690                             __func__, off_idx, off_pos);
 691             r = -1;
 692             goto out;
 693         }
 694
 695         qemu_sglist_init(sglist, (sglist_alloc_hint - off_idx), ad->hba->dma);
 696         qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr + off_pos),
 697                         le32_to_cpu(tbl[off_idx].flags_size) + 1 - off_pos);
 698
 699         for (i = off_idx + 1; i < sglist_alloc_hint; i++) {
 700             /* flags_size is zero-based */
 701             qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
 702                             le32_to_cpu(tbl[i].flags_size) + 1);
 703         }
 704     }
 705
 706 out:
 707     dma_memory_unmap(ad->hba->dma, prdt, prdt_len,
 708                      DMA_DIRECTION_TO_DEVICE, prdt_len);
 709     return r;
 710 }
 711
 712 static void ncq_cb(void *opaque, int ret)
 713 {
 714     NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
 715     IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
 716
 717     /* Clear bit for this tag in SActive */
 718     ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag);
 719
 720     if (ret < 0) {
 721         /* error */
 722         ide_state->error = ABRT_ERR;
 723         ide_state->status = READY_STAT | ERR_STAT;
 724         ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag);
 725     } else {
 726         ide_state->status = READY_STAT | SEEK_STAT;
 727     }
 728
 729     ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
 730                        (1 << ncq_tfs->tag));
 731
 732     DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n",
 733             ncq_tfs->tag);
 734
 735     bdrv_acct_done(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct);
 736     qemu_sglist_destroy(&ncq_tfs->sglist);
 737     ncq_tfs->used = 0;
 738 }
 739
 740 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,
 741                                 int slot)
 742 {
 743     NCQFrame *ncq_fis = (NCQFrame*)cmd_fis;
 744     uint8_t tag = ncq_fis->tag >> 3;
 745     NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag];
 746
 747     if (ncq_tfs->used) {
 748         /* error - already in use */
 749         fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag);
 750         return;
 751     }
 752
 753     ncq_tfs->used = 1;
 754     ncq_tfs->drive = &s->dev[port];
 755     ncq_tfs->slot = slot;
 756     ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |
 757                    ((uint64_t)ncq_fis->lba4 << 32) |
 758                    ((uint64_t)ncq_fis->lba3 << 24) |
 759                    ((uint64_t)ncq_fis->lba2 << 16) |
 760                    ((uint64_t)ncq_fis->lba1 << 8) |
 761                    (uint64_t)ncq_fis->lba0;
 762
 763     /* Note: We calculate the sector count, but don't currently rely on it.
 764      * The total size of the DMA buffer tells us the transfer size instead. */
 765     ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) |
 766                                 ncq_fis->sector_count_low;
 767
 768     DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", "
 769             "drive max %"PRId64"\n",
 770             ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2,
 771             s->dev[port].port.ifs[0].nb_sectors - 1);
 772
 773     ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0);
 774     ncq_tfs->tag = tag;
 775
 776     switch(ncq_fis->command) {
 777         case READ_FPDMA_QUEUED:
 778             DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", "
 779                     "tag %d\n",
 780                     ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
 781
 782             DPRINTF(port, "tag %d aio read %"PRId64"\n",
 783                     ncq_tfs->tag, ncq_tfs->lba);
 784
 785             dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct,
 786                            &ncq_tfs->sglist, BDRV_ACCT_READ);
 787             ncq_tfs->aiocb = dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs,
 788                                            &ncq_tfs->sglist, ncq_tfs->lba,
 789                                            ncq_cb, ncq_tfs);
 790             break;
 791         case WRITE_FPDMA_QUEUED:
 792             DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n",
 793                     ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
 794
 795             DPRINTF(port, "tag %d aio write %"PRId64"\n",
 796                     ncq_tfs->tag, ncq_tfs->lba);
 797
 798             dma_acct_start(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->acct,
 799                            &ncq_tfs->sglist, BDRV_ACCT_WRITE);
 800             ncq_tfs->aiocb = dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs,
 801                                             &ncq_tfs->sglist, ncq_tfs->lba,
 802                                             ncq_cb, ncq_tfs);
 803             break;
 804         default:
 805             DPRINTF(port, "error: tried to process non-NCQ command as NCQ\n");
 806             qemu_sglist_destroy(&ncq_tfs->sglist);
 807             break;
 808     }
 809 }
 810
 811 static int handle_cmd(AHCIState *s, int port, int slot)
 812 {
 813     IDEState *ide_state;
 814     uint32_t opts;
 815     uint64_t tbl_addr;
 816     AHCICmdHdr *cmd;
 817     uint8_t *cmd_fis;
 818     dma_addr_t cmd_len;
 819
 820     if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
 821         /* Engine currently busy, try again later */
 822         DPRINTF(port, "engine busy\n");
 823         return -1;
 824     }
 825
 826     cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot];
 827
 828     if (!s->dev[port].lst) {
 829         DPRINTF(port, "error: lst not given but cmd handled");
 830         return -1;
 831     }
 832
 833     /* remember current slot handle for later */
 834     s->dev[port].cur_cmd = cmd;
 835
 836     opts = le32_to_cpu(cmd->opts);
 837     tbl_addr = le64_to_cpu(cmd->tbl_addr);
 838
 839     cmd_len = 0x80;
 840     cmd_fis = dma_memory_map(s->dma, tbl_addr, &cmd_len,
 841                              DMA_DIRECTION_FROM_DEVICE);
 842
 843     if (!cmd_fis) {
 844         DPRINTF(port, "error: guest passed us an invalid cmd fis\n");
 845         return -1;
 846     }
 847
 848     /* The device we are working for */
 849     ide_state = &s->dev[port].port.ifs[0];
 850
 851     if (!ide_state->bs) {
 852         DPRINTF(port, "error: guest accessed unused port");
 853         goto out;
 854     }
 855
 856     debug_print_fis(cmd_fis, 0x90);
 857     //debug_print_fis(cmd_fis, (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4);
 858
 859     switch (cmd_fis[0]) {
 860         case SATA_FIS_TYPE_REGISTER_H2D:
 861             break;
 862         default:
 863             DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
 864                           "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1],
 865                           cmd_fis[2]);
 866             goto out;
 867             break;
 868     }
 869
 870     switch (cmd_fis[1]) {
 871         case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER:
 872             break;
 873         case 0:
 874             break;
 875         default:
 876             DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
 877                           "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1],
 878                           cmd_fis[2]);
 879             goto out;
 880             break;
 881     }
 882
 883     switch (s->dev[port].port_state) {
 884         case STATE_RUN:
 885             if (cmd_fis[15] & ATA_SRST) {
 886                 s->dev[port].port_state = STATE_RESET;
 887             }
 888             break;
 889         case STATE_RESET:
 890             if (!(cmd_fis[15] & ATA_SRST)) {
 891                 ahci_reset_port(s, port);
 892             }
 893             break;
 894     }
 895
 896     if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) {
 897
 898         /* Check for NCQ command */
 899         if ((cmd_fis[2] == READ_FPDMA_QUEUED) ||
 900             (cmd_fis[2] == WRITE_FPDMA_QUEUED)) {
 901             process_ncq_command(s, port, cmd_fis, slot);
 902             goto out;
 903         }
 904
 905         /* Decompose the FIS  */
 906         ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]);
 907         ide_state->feature = cmd_fis[3];
 908         if (!ide_state->nsector) {
 909             ide_state->nsector = 256;
 910         }
 911
 912         if (ide_state->drive_kind != IDE_CD) {
 913             /*
 914              * We set the sector depending on the sector defined in the FIS.
 915              * Unfortunately, the spec isn't exactly obvious on this one.
 916              *
 917              * Apparently LBA48 commands set fis bytes 10,9,8,6,5,4 to the
 918              * 48 bit sector number. ATA_CMD_READ_DMA_EXT is an example for
 919              * such a command.
 920              *
 921              * Non-LBA48 commands however use 7[lower 4 bits],6,5,4 to define a
 922              * 28-bit sector number. ATA_CMD_READ_DMA is an example for such
 923              * a command.
 924              *
 925              * Since the spec doesn't explicitly state what each field should
 926              * do, I simply assume non-used fields as reserved and OR everything
 927              * together, independent of the command.
 928              */
 929             ide_set_sector(ide_state, ((uint64_t)cmd_fis[10] << 40)
 930                                     | ((uint64_t)cmd_fis[9] << 32)
 931                                     /* This is used for LBA48 commands */
 932                                     | ((uint64_t)cmd_fis[8] << 24)
 933                                     /* This is used for non-LBA48 commands */
 934                                     | ((uint64_t)(cmd_fis[7] & 0xf) << 24)
 935                                     | ((uint64_t)cmd_fis[6] << 16)
 936                                     | ((uint64_t)cmd_fis[5] << 8)
 937                                     | cmd_fis[4]);
 938         }
 939
 940         /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
 941          * table to ide_state->io_buffer
 942          */
 943         if (opts & AHCI_CMD_ATAPI) {
 944             memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
 945             ide_state->lcyl = 0x14;
 946             ide_state->hcyl = 0xeb;
 947             debug_print_fis(ide_state->io_buffer, 0x10);
 948             ide_state->feature = IDE_FEATURE_DMA;
 949             s->dev[port].done_atapi_packet = 0;
 950             /* XXX send PIO setup FIS */
 951         }
 952
 953         ide_state->error = 0;
 954
 955         /* Reset transferred byte counter */
 956         cmd->status = 0;
 957
 958         /* We're ready to process the command in FIS byte 2. */
 959         ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);
 960
 961         if (s->dev[port].port.ifs[0].status & READY_STAT) {
 962             ahci_write_fis_d2h(&s->dev[port], cmd_fis);
 963         }
 964     }
 965
 966 out:
 967     dma_memory_unmap(s->dma, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE,
 968                      cmd_len);
 969
 970     if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
 971         /* async command, complete later */
 972         s->dev[port].busy_slot = slot;
 973         return -1;
 974     }
 975
 976     /* done handling the command */
 977     return 0;
 978 }
 979
 980 /* DMA dev <-> ram */
 981 static int ahci_start_transfer(IDEDMA *dma)
 982 {
 983     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
 984     IDEState *s = &ad->port.ifs[0];
 985     uint32_t size = (uint32_t)(s->data_end - s->data_ptr);
 986     /* write == ram -> device */
 987     uint32_t opts = le32_to_cpu(ad->cur_cmd->opts);
 988     int is_write = opts & AHCI_CMD_WRITE;
 989     int is_atapi = opts & AHCI_CMD_ATAPI;
 990     int has_sglist = 0;
 991
 992     if (is_atapi && !ad->done_atapi_packet) {
 993         /* already prepopulated iobuffer */
 994         ad->done_atapi_packet = 1;
 995         goto out;
 996     }
 997
 998     if (!ahci_populate_sglist(ad, &s->sg, 0)) {
 999         has_sglist = 1;
1000     }
1001
1002     DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n",
1003             is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata",
1004             has_sglist ? "" : "o");
1005
1006     if (has_sglist && size) {
1007         if (is_write) {
1008             dma_buf_write(s->data_ptr, size, &s->sg);
1009         } else {
1010             dma_buf_read(s->data_ptr, size, &s->sg);
1011         }
1012     }
1013
1014     /* update number of transferred bytes */
1015     ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + size);
1016
1017 out:
1018     /* declare that we processed everything */
1019     s->data_ptr = s->data_end;
1020
1021     if (has_sglist) {
1022         qemu_sglist_destroy(&s->sg);
1023     }
1024
1025     s->end_transfer_func(s);
1026
1027     if (!(s->status & DRQ_STAT)) {
1028         /* done with DMA */
1029         ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS);
1030     }
1031
1032     return 0;
1033 }
1034
1035 static void ahci_start_dma(IDEDMA *dma, IDEState *s,
1036                            BlockDriverCompletionFunc *dma_cb)
1037 {
1038     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1039
1040     DPRINTF(ad->port_no, "\n");
1041     ad->dma_cb = dma_cb;
1042     ad->dma_status |= BM_STATUS_DMAING;
1043     s->io_buffer_offset = 0;
1044     dma_cb(s, 0);
1045 }
1046
1047 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write)
1048 {
1049     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1050     IDEState *s = &ad->port.ifs[0];
1051
1052     ahci_populate_sglist(ad, &s->sg, 0);
1053     s->io_buffer_size = s->sg.size;
1054
1055     DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size);
1056     return s->io_buffer_size != 0;
1057 }
1058
1059 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write)
1060 {
1061     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1062     IDEState *s = &ad->port.ifs[0];
1063     uint8_t *p = s->io_buffer + s->io_buffer_index;
1064     int l = s->io_buffer_size - s->io_buffer_index;
1065
1066     if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) {
1067         return 0;
1068     }
1069
1070     if (is_write) {
1071         dma_buf_read(p, l, &s->sg);
1072     } else {
1073         dma_buf_write(p, l, &s->sg);
1074     }
1075
1076     /* free sglist that was created in ahci_populate_sglist() */
1077     qemu_sglist_destroy(&s->sg);
1078
1079     /* update number of transferred bytes */
1080     ad->cur_cmd->status = cpu_to_le32(le32_to_cpu(ad->cur_cmd->status) + l);
1081     s->io_buffer_index += l;
1082     s->io_buffer_offset += l;
1083
1084     DPRINTF(ad->port_no, "len=%#x\n", l);
1085
1086     return 1;
1087 }
1088
1089 static int ahci_dma_set_unit(IDEDMA *dma, int unit)
1090 {
1091     /* only a single unit per link */
1092     return 0;
1093 }
1094
1095 static int ahci_dma_add_status(IDEDMA *dma, int status)
1096 {
1097     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1098     ad->dma_status |= status;
1099     DPRINTF(ad->port_no, "set status: %x\n", status);
1100
1101     if (status & BM_STATUS_INT) {
1102         ahci_trigger_irq(ad->hba, ad, PORT_IRQ_STAT_DSS);
1103     }
1104
1105     return 0;
1106 }
1107
1108 static int ahci_dma_set_inactive(IDEDMA *dma)
1109 {
1110     AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1111
1112     DPRINTF(ad->port_no, "dma done\n");
1113
1114     /* update d2h status */
1115     ahci_write_fis_d2h(ad, NULL);
1116
1117     ad->dma_cb = NULL;
1118
1119     if (!ad->check_bh) {
1120         /* maybe we still have something to process, check later */
1121         ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad);
1122         qemu_bh_schedule(ad->check_bh);
1123     }
1124
1125     return 0;
1126 }
1127
1128 static void ahci_irq_set(void *opaque, int n, int level)
1129 {
1130 }
1131
1132 static void ahci_dma_restart_cb(void *opaque, int running, RunState state)
1133 {
1134 }
1135
1136 static int ahci_dma_reset(IDEDMA *dma)
1137 {
1138     return 0;
1139 }
1140
1141 static const IDEDMAOps ahci_dma_ops = {
1142     .start_dma = ahci_start_dma,
1143     .start_transfer = ahci_start_transfer,
1144     .prepare_buf = ahci_dma_prepare_buf,
1145     .rw_buf = ahci_dma_rw_buf,
1146     .set_unit = ahci_dma_set_unit,
1147     .add_status = ahci_dma_add_status,
1148     .set_inactive = ahci_dma_set_inactive,
1149     .restart_cb = ahci_dma_restart_cb,
1150     .reset = ahci_dma_reset,
1151 };
1152
1153 void ahci_init(AHCIState *s, DeviceState *qdev, DMAContext *dma, int ports)
1154 {
1155     qemu_irq *irqs;
1156     int i;
1157
1158     s->dma = dma;
1159     s->ports = ports;
1160     s->dev = g_malloc0(sizeof(AHCIDevice) * ports);
1161     ahci_reg_init(s);
1162     /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1163     memory_region_init_io(&s->mem, &ahci_mem_ops, s, "ahci", AHCI_MEM_BAR_SIZE);
1164     memory_region_init_io(&s->idp, &ahci_idp_ops, s, "ahci-idp", 32);
1165
1166     irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
1167
1168     for (i = 0; i < s->ports; i++) {
1169         AHCIDevice *ad = &s->dev[i];
1170
1171         ide_bus_new(&ad->port, qdev, i);
1172         ide_init2(&ad->port, irqs[i]);
1173
1174         ad->hba = s;
1175         ad->port_no = i;
1176         ad->port.dma = &ad->dma;
1177         ad->port.dma->ops = &ahci_dma_ops;
1178     }
1179 }
1180
1181 void ahci_uninit(AHCIState *s)
1182 {
1183     memory_region_destroy(&s->mem);
1184     memory_region_destroy(&s->idp);
1185     g_free(s->dev);
1186 }
1187
1188 void ahci_reset(AHCIState *s)
1189 {
1190     AHCIPortRegs *pr;
1191     int i;
1192
1193     s->control_regs.irqstatus = 0;
1194     s->control_regs.ghc = 0;
1195
1196     for (i = 0; i < s->ports; i++) {
1197         pr = &s->dev[i].port_regs;
1198         pr->irq_stat = 0;
1199         pr->irq_mask = 0;
1200         pr->scr_ctl = 0;
1201         pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
1202         ahci_reset_port(s, i);
1203     }
1204 }
1205
1206 typedef struct SysbusAHCIState {
1207     SysBusDevice busdev;
1208     AHCIState ahci;
1209     uint32_t num_ports;
1210 } SysbusAHCIState;
1211
1212 static const VMStateDescription vmstate_sysbus_ahci = {
1213     .name = "sysbus-ahci",
1214     .unmigratable = 1,
1215 };
1216
1217 static void sysbus_ahci_reset(DeviceState *dev)
1218 {
1219     SysbusAHCIState *s = DO_UPCAST(SysbusAHCIState, busdev.qdev, dev);
1220
1221     ahci_reset(&s->ahci);
1222 }
1223
1224 static int sysbus_ahci_init(SysBusDevice *dev)
1225 {
1226     SysbusAHCIState *s = FROM_SYSBUS(SysbusAHCIState, dev);
1227     ahci_init(&s->ahci, &dev->qdev, NULL, s->num_ports);
1228
1229     sysbus_init_mmio(dev, &s->ahci.mem);
1230     sysbus_init_irq(dev, &s->ahci.irq);
1231     return 0;
1232 }
1233
1234 static Property sysbus_ahci_properties[] = {
1235     DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
1236     DEFINE_PROP_END_OF_LIST(),
1237 };
1238
1239 static void sysbus_ahci_class_init(ObjectClass *klass, void *data)
1240 {
1241     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1242     DeviceClass *dc = DEVICE_CLASS(klass);
1243
1244     sbc->init = sysbus_ahci_init;
1245     dc->vmsd = &vmstate_sysbus_ahci;
1246     dc->props = sysbus_ahci_properties;
1247     dc->reset = sysbus_ahci_reset;
1248 }
1249
1250 static TypeInfo sysbus_ahci_info = {
1251     .name          = "sysbus-ahci",
1252     .parent        = TYPE_SYS_BUS_DEVICE,
1253     .instance_size = sizeof(SysbusAHCIState),
1254     .class_init    = sysbus_ahci_class_init,
1255 };
1256
1257 static void sysbus_ahci_register_types(void)
1258 {
1259     type_register_static(&sysbus_ahci_info);
1260 }
1261
1262 type_init(sysbus_ahci_register_types)