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[qemu.git] / hw / ide / core.c
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/pc.h>
27 #include <hw/pci.h>
28 #include <hw/isa.h>
29 #include "qemu-error.h"
30 #include "qemu-timer.h"
31 #include "sysemu.h"
32 #include "dma.h"
33 #include "blockdev.h"
34
35 #include <hw/ide/internal.h>
36
37 /* These values were based on a Seagate ST3500418AS but have been modified
38 to make more sense in QEMU */
39 static const int smart_attributes[][12] = {
40 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
41 /* raw read error rate*/
42 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
43 /* spin up */
44 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
45 /* start stop count */
46 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
47 /* remapped sectors */
48 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
49 /* power on hours */
50 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
51 /* power cycle count */
52 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
53 /* airflow-temperature-celsius */
54 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
55 /* end of list */
56 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
57 };
58
59 static int ide_handle_rw_error(IDEState *s, int error, int op);
60 static void ide_dummy_transfer_stop(IDEState *s);
61
62 static void padstr(char *str, const char *src, int len)
63 {
64 int i, v;
65 for(i = 0; i < len; i++) {
66 if (*src)
67 v = *src++;
68 else
69 v = ' ';
70 str[i^1] = v;
71 }
72 }
73
74 static void put_le16(uint16_t *p, unsigned int v)
75 {
76 *p = cpu_to_le16(v);
77 }
78
79 static void ide_identify(IDEState *s)
80 {
81 uint16_t *p;
82 unsigned int oldsize;
83 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
84
85 if (s->identify_set) {
86 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
87 return;
88 }
89
90 memset(s->io_buffer, 0, 512);
91 p = (uint16_t *)s->io_buffer;
92 put_le16(p + 0, 0x0040);
93 put_le16(p + 1, s->cylinders);
94 put_le16(p + 3, s->heads);
95 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
96 put_le16(p + 5, 512); /* XXX: retired, remove ? */
97 put_le16(p + 6, s->sectors);
98 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
99 put_le16(p + 20, 3); /* XXX: retired, remove ? */
100 put_le16(p + 21, 512); /* cache size in sectors */
101 put_le16(p + 22, 4); /* ecc bytes */
102 padstr((char *)(p + 23), s->version, 8); /* firmware version */
103 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
104 #if MAX_MULT_SECTORS > 1
105 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
106 #endif
107 put_le16(p + 48, 1); /* dword I/O */
108 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
109 put_le16(p + 51, 0x200); /* PIO transfer cycle */
110 put_le16(p + 52, 0x200); /* DMA transfer cycle */
111 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
112 put_le16(p + 54, s->cylinders);
113 put_le16(p + 55, s->heads);
114 put_le16(p + 56, s->sectors);
115 oldsize = s->cylinders * s->heads * s->sectors;
116 put_le16(p + 57, oldsize);
117 put_le16(p + 58, oldsize >> 16);
118 if (s->mult_sectors)
119 put_le16(p + 59, 0x100 | s->mult_sectors);
120 put_le16(p + 60, s->nb_sectors);
121 put_le16(p + 61, s->nb_sectors >> 16);
122 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
123 put_le16(p + 63, 0x07); /* mdma0-2 supported */
124 put_le16(p + 64, 0x03); /* pio3-4 supported */
125 put_le16(p + 65, 120);
126 put_le16(p + 66, 120);
127 put_le16(p + 67, 120);
128 put_le16(p + 68, 120);
129 if (dev && dev->conf.discard_granularity) {
130 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
131 }
132
133 if (s->ncq_queues) {
134 put_le16(p + 75, s->ncq_queues - 1);
135 /* NCQ supported */
136 put_le16(p + 76, (1 << 8));
137 }
138
139 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
140 put_le16(p + 81, 0x16); /* conforms to ata5 */
141 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
142 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
143 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
144 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
145 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
146 if (s->wwn) {
147 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
148 } else {
149 put_le16(p + 84, (1 << 14) | 0);
150 }
151 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
152 if (bdrv_enable_write_cache(s->bs))
153 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
154 else
155 put_le16(p + 85, (1 << 14) | 1);
156 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
157 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
158 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
159 if (s->wwn) {
160 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
161 } else {
162 put_le16(p + 87, (1 << 14) | 0);
163 }
164 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
165 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
166 put_le16(p + 100, s->nb_sectors);
167 put_le16(p + 101, s->nb_sectors >> 16);
168 put_le16(p + 102, s->nb_sectors >> 32);
169 put_le16(p + 103, s->nb_sectors >> 48);
170
171 if (dev && dev->conf.physical_block_size)
172 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
173 if (s->wwn) {
174 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
175 put_le16(p + 108, s->wwn >> 48);
176 put_le16(p + 109, s->wwn >> 32);
177 put_le16(p + 110, s->wwn >> 16);
178 put_le16(p + 111, s->wwn);
179 }
180 if (dev && dev->conf.discard_granularity) {
181 put_le16(p + 169, 1); /* TRIM support */
182 }
183
184 memcpy(s->identify_data, p, sizeof(s->identify_data));
185 s->identify_set = 1;
186 }
187
188 static void ide_atapi_identify(IDEState *s)
189 {
190 uint16_t *p;
191
192 if (s->identify_set) {
193 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
194 return;
195 }
196
197 memset(s->io_buffer, 0, 512);
198 p = (uint16_t *)s->io_buffer;
199 /* Removable CDROM, 50us response, 12 byte packets */
200 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
201 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
202 put_le16(p + 20, 3); /* buffer type */
203 put_le16(p + 21, 512); /* cache size in sectors */
204 put_le16(p + 22, 4); /* ecc bytes */
205 padstr((char *)(p + 23), s->version, 8); /* firmware version */
206 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
207 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
208 #ifdef USE_DMA_CDROM
209 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
210 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
211 put_le16(p + 62, 7); /* single word dma0-2 supported */
212 put_le16(p + 63, 7); /* mdma0-2 supported */
213 #else
214 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
215 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
216 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
217 #endif
218 put_le16(p + 64, 3); /* pio3-4 supported */
219 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
220 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
221 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
222 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
223
224 put_le16(p + 71, 30); /* in ns */
225 put_le16(p + 72, 30); /* in ns */
226
227 if (s->ncq_queues) {
228 put_le16(p + 75, s->ncq_queues - 1);
229 /* NCQ supported */
230 put_le16(p + 76, (1 << 8));
231 }
232
233 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
234 #ifdef USE_DMA_CDROM
235 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
236 #endif
237 memcpy(s->identify_data, p, sizeof(s->identify_data));
238 s->identify_set = 1;
239 }
240
241 static void ide_cfata_identify(IDEState *s)
242 {
243 uint16_t *p;
244 uint32_t cur_sec;
245
246 p = (uint16_t *) s->identify_data;
247 if (s->identify_set)
248 goto fill_buffer;
249
250 memset(p, 0, sizeof(s->identify_data));
251
252 cur_sec = s->cylinders * s->heads * s->sectors;
253
254 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
255 put_le16(p + 1, s->cylinders); /* Default cylinders */
256 put_le16(p + 3, s->heads); /* Default heads */
257 put_le16(p + 6, s->sectors); /* Default sectors per track */
258 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
259 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
260 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
261 put_le16(p + 22, 0x0004); /* ECC bytes */
262 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
263 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
264 #if MAX_MULT_SECTORS > 1
265 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
266 #else
267 put_le16(p + 47, 0x0000);
268 #endif
269 put_le16(p + 49, 0x0f00); /* Capabilities */
270 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
271 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
272 put_le16(p + 53, 0x0003); /* Translation params valid */
273 put_le16(p + 54, s->cylinders); /* Current cylinders */
274 put_le16(p + 55, s->heads); /* Current heads */
275 put_le16(p + 56, s->sectors); /* Current sectors */
276 put_le16(p + 57, cur_sec); /* Current capacity */
277 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
278 if (s->mult_sectors) /* Multiple sector setting */
279 put_le16(p + 59, 0x100 | s->mult_sectors);
280 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
281 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
282 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
283 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
284 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
285 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
286 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
287 put_le16(p + 82, 0x400c); /* Command Set supported */
288 put_le16(p + 83, 0x7068); /* Command Set supported */
289 put_le16(p + 84, 0x4000); /* Features supported */
290 put_le16(p + 85, 0x000c); /* Command Set enabled */
291 put_le16(p + 86, 0x7044); /* Command Set enabled */
292 put_le16(p + 87, 0x4000); /* Features enabled */
293 put_le16(p + 91, 0x4060); /* Current APM level */
294 put_le16(p + 129, 0x0002); /* Current features option */
295 put_le16(p + 130, 0x0005); /* Reassigned sectors */
296 put_le16(p + 131, 0x0001); /* Initial power mode */
297 put_le16(p + 132, 0x0000); /* User signature */
298 put_le16(p + 160, 0x8100); /* Power requirement */
299 put_le16(p + 161, 0x8001); /* CF command set */
300
301 s->identify_set = 1;
302
303 fill_buffer:
304 memcpy(s->io_buffer, p, sizeof(s->identify_data));
305 }
306
307 static void ide_set_signature(IDEState *s)
308 {
309 s->select &= 0xf0; /* clear head */
310 /* put signature */
311 s->nsector = 1;
312 s->sector = 1;
313 if (s->drive_kind == IDE_CD) {
314 s->lcyl = 0x14;
315 s->hcyl = 0xeb;
316 } else if (s->bs) {
317 s->lcyl = 0;
318 s->hcyl = 0;
319 } else {
320 s->lcyl = 0xff;
321 s->hcyl = 0xff;
322 }
323 }
324
325 typedef struct TrimAIOCB {
326 BlockDriverAIOCB common;
327 QEMUBH *bh;
328 int ret;
329 } TrimAIOCB;
330
331 static void trim_aio_cancel(BlockDriverAIOCB *acb)
332 {
333 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
334
335 qemu_bh_delete(iocb->bh);
336 iocb->bh = NULL;
337 qemu_aio_release(iocb);
338 }
339
340 static AIOPool trim_aio_pool = {
341 .aiocb_size = sizeof(TrimAIOCB),
342 .cancel = trim_aio_cancel,
343 };
344
345 static void ide_trim_bh_cb(void *opaque)
346 {
347 TrimAIOCB *iocb = opaque;
348
349 iocb->common.cb(iocb->common.opaque, iocb->ret);
350
351 qemu_bh_delete(iocb->bh);
352 iocb->bh = NULL;
353
354 qemu_aio_release(iocb);
355 }
356
357 BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
358 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
359 BlockDriverCompletionFunc *cb, void *opaque)
360 {
361 TrimAIOCB *iocb;
362 int i, j, ret;
363
364 iocb = qemu_aio_get(&trim_aio_pool, bs, cb, opaque);
365 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
366 iocb->ret = 0;
367
368 for (j = 0; j < qiov->niov; j++) {
369 uint64_t *buffer = qiov->iov[j].iov_base;
370
371 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) {
372 /* 6-byte LBA + 2-byte range per entry */
373 uint64_t entry = le64_to_cpu(buffer[i]);
374 uint64_t sector = entry & 0x0000ffffffffffffULL;
375 uint16_t count = entry >> 48;
376
377 if (count == 0) {
378 break;
379 }
380
381 ret = bdrv_discard(bs, sector, count);
382 if (!iocb->ret) {
383 iocb->ret = ret;
384 }
385 }
386 }
387
388 qemu_bh_schedule(iocb->bh);
389
390 return &iocb->common;
391 }
392
393 static inline void ide_abort_command(IDEState *s)
394 {
395 s->status = READY_STAT | ERR_STAT;
396 s->error = ABRT_ERR;
397 }
398
399 /* prepare data transfer and tell what to do after */
400 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
401 EndTransferFunc *end_transfer_func)
402 {
403 s->end_transfer_func = end_transfer_func;
404 s->data_ptr = buf;
405 s->data_end = buf + size;
406 if (!(s->status & ERR_STAT)) {
407 s->status |= DRQ_STAT;
408 }
409 s->bus->dma->ops->start_transfer(s->bus->dma);
410 }
411
412 void ide_transfer_stop(IDEState *s)
413 {
414 s->end_transfer_func = ide_transfer_stop;
415 s->data_ptr = s->io_buffer;
416 s->data_end = s->io_buffer;
417 s->status &= ~DRQ_STAT;
418 }
419
420 int64_t ide_get_sector(IDEState *s)
421 {
422 int64_t sector_num;
423 if (s->select & 0x40) {
424 /* lba */
425 if (!s->lba48) {
426 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
427 (s->lcyl << 8) | s->sector;
428 } else {
429 sector_num = ((int64_t)s->hob_hcyl << 40) |
430 ((int64_t) s->hob_lcyl << 32) |
431 ((int64_t) s->hob_sector << 24) |
432 ((int64_t) s->hcyl << 16) |
433 ((int64_t) s->lcyl << 8) | s->sector;
434 }
435 } else {
436 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
437 (s->select & 0x0f) * s->sectors + (s->sector - 1);
438 }
439 return sector_num;
440 }
441
442 void ide_set_sector(IDEState *s, int64_t sector_num)
443 {
444 unsigned int cyl, r;
445 if (s->select & 0x40) {
446 if (!s->lba48) {
447 s->select = (s->select & 0xf0) | (sector_num >> 24);
448 s->hcyl = (sector_num >> 16);
449 s->lcyl = (sector_num >> 8);
450 s->sector = (sector_num);
451 } else {
452 s->sector = sector_num;
453 s->lcyl = sector_num >> 8;
454 s->hcyl = sector_num >> 16;
455 s->hob_sector = sector_num >> 24;
456 s->hob_lcyl = sector_num >> 32;
457 s->hob_hcyl = sector_num >> 40;
458 }
459 } else {
460 cyl = sector_num / (s->heads * s->sectors);
461 r = sector_num % (s->heads * s->sectors);
462 s->hcyl = cyl >> 8;
463 s->lcyl = cyl;
464 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
465 s->sector = (r % s->sectors) + 1;
466 }
467 }
468
469 static void ide_rw_error(IDEState *s) {
470 ide_abort_command(s);
471 ide_set_irq(s->bus);
472 }
473
474 void ide_sector_read(IDEState *s)
475 {
476 int64_t sector_num;
477 int ret, n;
478
479 s->status = READY_STAT | SEEK_STAT;
480 s->error = 0; /* not needed by IDE spec, but needed by Windows */
481 sector_num = ide_get_sector(s);
482 n = s->nsector;
483 if (n == 0) {
484 /* no more sector to read from disk */
485 ide_transfer_stop(s);
486 } else {
487 #if defined(DEBUG_IDE)
488 printf("read sector=%" PRId64 "\n", sector_num);
489 #endif
490 if (n > s->req_nb_sectors)
491 n = s->req_nb_sectors;
492
493 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
494 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
495 bdrv_acct_done(s->bs, &s->acct);
496 if (ret != 0) {
497 if (ide_handle_rw_error(s, -ret,
498 BM_STATUS_PIO_RETRY | BM_STATUS_RETRY_READ))
499 {
500 return;
501 }
502 }
503 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
504 ide_set_irq(s->bus);
505 ide_set_sector(s, sector_num + n);
506 s->nsector -= n;
507 }
508 }
509
510 static void dma_buf_commit(IDEState *s)
511 {
512 qemu_sglist_destroy(&s->sg);
513 }
514
515 void ide_set_inactive(IDEState *s)
516 {
517 s->bus->dma->aiocb = NULL;
518 s->bus->dma->ops->set_inactive(s->bus->dma);
519 }
520
521 void ide_dma_error(IDEState *s)
522 {
523 ide_transfer_stop(s);
524 s->error = ABRT_ERR;
525 s->status = READY_STAT | ERR_STAT;
526 ide_set_inactive(s);
527 ide_set_irq(s->bus);
528 }
529
530 static int ide_handle_rw_error(IDEState *s, int error, int op)
531 {
532 int is_read = (op & BM_STATUS_RETRY_READ);
533 BlockErrorAction action = bdrv_get_on_error(s->bs, is_read);
534
535 if (action == BLOCK_ERR_IGNORE) {
536 bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_IGNORE, is_read);
537 return 0;
538 }
539
540 if ((error == ENOSPC && action == BLOCK_ERR_STOP_ENOSPC)
541 || action == BLOCK_ERR_STOP_ANY) {
542 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
543 s->bus->error_status = op;
544 bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_STOP, is_read);
545 vm_stop(RUN_STATE_IO_ERROR);
546 bdrv_iostatus_set_err(s->bs, error);
547 } else {
548 if (op & BM_STATUS_DMA_RETRY) {
549 dma_buf_commit(s);
550 ide_dma_error(s);
551 } else {
552 ide_rw_error(s);
553 }
554 bdrv_emit_qmp_error_event(s->bs, BDRV_ACTION_REPORT, is_read);
555 }
556
557 return 1;
558 }
559
560 void ide_dma_cb(void *opaque, int ret)
561 {
562 IDEState *s = opaque;
563 int n;
564 int64_t sector_num;
565
566 if (ret < 0) {
567 int op = BM_STATUS_DMA_RETRY;
568
569 if (s->dma_cmd == IDE_DMA_READ)
570 op |= BM_STATUS_RETRY_READ;
571 else if (s->dma_cmd == IDE_DMA_TRIM)
572 op |= BM_STATUS_RETRY_TRIM;
573
574 if (ide_handle_rw_error(s, -ret, op)) {
575 return;
576 }
577 }
578
579 n = s->io_buffer_size >> 9;
580 sector_num = ide_get_sector(s);
581 if (n > 0) {
582 dma_buf_commit(s);
583 sector_num += n;
584 ide_set_sector(s, sector_num);
585 s->nsector -= n;
586 }
587
588 /* end of transfer ? */
589 if (s->nsector == 0) {
590 s->status = READY_STAT | SEEK_STAT;
591 ide_set_irq(s->bus);
592 goto eot;
593 }
594
595 /* launch next transfer */
596 n = s->nsector;
597 s->io_buffer_index = 0;
598 s->io_buffer_size = n * 512;
599 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
600 /* The PRDs were too short. Reset the Active bit, but don't raise an
601 * interrupt. */
602 goto eot;
603 }
604
605 #ifdef DEBUG_AIO
606 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
607 sector_num, n, s->dma_cmd);
608 #endif
609
610 switch (s->dma_cmd) {
611 case IDE_DMA_READ:
612 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
613 ide_dma_cb, s);
614 break;
615 case IDE_DMA_WRITE:
616 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
617 ide_dma_cb, s);
618 break;
619 case IDE_DMA_TRIM:
620 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
621 ide_issue_trim, ide_dma_cb, s, true);
622 break;
623 }
624 return;
625
626 eot:
627 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
628 bdrv_acct_done(s->bs, &s->acct);
629 }
630 ide_set_inactive(s);
631 }
632
633 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
634 {
635 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
636 s->io_buffer_index = 0;
637 s->io_buffer_size = 0;
638 s->dma_cmd = dma_cmd;
639
640 switch (dma_cmd) {
641 case IDE_DMA_READ:
642 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
643 BDRV_ACCT_READ);
644 break;
645 case IDE_DMA_WRITE:
646 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
647 BDRV_ACCT_WRITE);
648 break;
649 default:
650 break;
651 }
652
653 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
654 }
655
656 static void ide_sector_write_timer_cb(void *opaque)
657 {
658 IDEState *s = opaque;
659 ide_set_irq(s->bus);
660 }
661
662 void ide_sector_write(IDEState *s)
663 {
664 int64_t sector_num;
665 int ret, n, n1;
666
667 s->status = READY_STAT | SEEK_STAT;
668 sector_num = ide_get_sector(s);
669 #if defined(DEBUG_IDE)
670 printf("write sector=%" PRId64 "\n", sector_num);
671 #endif
672 n = s->nsector;
673 if (n > s->req_nb_sectors)
674 n = s->req_nb_sectors;
675
676 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
677 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
678 bdrv_acct_done(s->bs, &s->acct);
679
680 if (ret != 0) {
681 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY))
682 return;
683 }
684
685 s->nsector -= n;
686 if (s->nsector == 0) {
687 /* no more sectors to write */
688 ide_transfer_stop(s);
689 } else {
690 n1 = s->nsector;
691 if (n1 > s->req_nb_sectors)
692 n1 = s->req_nb_sectors;
693 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
694 }
695 ide_set_sector(s, sector_num + n);
696
697 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
698 /* It seems there is a bug in the Windows 2000 installer HDD
699 IDE driver which fills the disk with empty logs when the
700 IDE write IRQ comes too early. This hack tries to correct
701 that at the expense of slower write performances. Use this
702 option _only_ to install Windows 2000. You must disable it
703 for normal use. */
704 qemu_mod_timer(s->sector_write_timer,
705 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
706 } else {
707 ide_set_irq(s->bus);
708 }
709 }
710
711 static void ide_flush_cb(void *opaque, int ret)
712 {
713 IDEState *s = opaque;
714
715 if (ret < 0) {
716 /* XXX: What sector number to set here? */
717 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
718 return;
719 }
720 }
721
722 bdrv_acct_done(s->bs, &s->acct);
723 s->status = READY_STAT | SEEK_STAT;
724 ide_set_irq(s->bus);
725 }
726
727 void ide_flush_cache(IDEState *s)
728 {
729 if (s->bs == NULL) {
730 ide_flush_cb(s, 0);
731 return;
732 }
733
734 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
735 bdrv_aio_flush(s->bs, ide_flush_cb, s);
736 }
737
738 static void ide_cfata_metadata_inquiry(IDEState *s)
739 {
740 uint16_t *p;
741 uint32_t spd;
742
743 p = (uint16_t *) s->io_buffer;
744 memset(p, 0, 0x200);
745 spd = ((s->mdata_size - 1) >> 9) + 1;
746
747 put_le16(p + 0, 0x0001); /* Data format revision */
748 put_le16(p + 1, 0x0000); /* Media property: silicon */
749 put_le16(p + 2, s->media_changed); /* Media status */
750 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
751 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
752 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
753 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
754 }
755
756 static void ide_cfata_metadata_read(IDEState *s)
757 {
758 uint16_t *p;
759
760 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
761 s->status = ERR_STAT;
762 s->error = ABRT_ERR;
763 return;
764 }
765
766 p = (uint16_t *) s->io_buffer;
767 memset(p, 0, 0x200);
768
769 put_le16(p + 0, s->media_changed); /* Media status */
770 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
771 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
772 s->nsector << 9), 0x200 - 2));
773 }
774
775 static void ide_cfata_metadata_write(IDEState *s)
776 {
777 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
778 s->status = ERR_STAT;
779 s->error = ABRT_ERR;
780 return;
781 }
782
783 s->media_changed = 0;
784
785 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
786 s->io_buffer + 2,
787 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
788 s->nsector << 9), 0x200 - 2));
789 }
790
791 /* called when the inserted state of the media has changed */
792 static void ide_cd_change_cb(void *opaque, bool load)
793 {
794 IDEState *s = opaque;
795 uint64_t nb_sectors;
796
797 s->tray_open = !load;
798 bdrv_get_geometry(s->bs, &nb_sectors);
799 s->nb_sectors = nb_sectors;
800
801 /*
802 * First indicate to the guest that a CD has been removed. That's
803 * done on the next command the guest sends us.
804 *
805 * Then we set UNIT_ATTENTION, by which the guest will
806 * detect a new CD in the drive. See ide_atapi_cmd() for details.
807 */
808 s->cdrom_changed = 1;
809 s->events.new_media = true;
810 s->events.eject_request = false;
811 ide_set_irq(s->bus);
812 }
813
814 static void ide_cd_eject_request_cb(void *opaque, bool force)
815 {
816 IDEState *s = opaque;
817
818 s->events.eject_request = true;
819 if (force) {
820 s->tray_locked = false;
821 }
822 ide_set_irq(s->bus);
823 }
824
825 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
826 {
827 s->lba48 = lba48;
828
829 /* handle the 'magic' 0 nsector count conversion here. to avoid
830 * fiddling with the rest of the read logic, we just store the
831 * full sector count in ->nsector and ignore ->hob_nsector from now
832 */
833 if (!s->lba48) {
834 if (!s->nsector)
835 s->nsector = 256;
836 } else {
837 if (!s->nsector && !s->hob_nsector)
838 s->nsector = 65536;
839 else {
840 int lo = s->nsector;
841 int hi = s->hob_nsector;
842
843 s->nsector = (hi << 8) | lo;
844 }
845 }
846 }
847
848 static void ide_clear_hob(IDEBus *bus)
849 {
850 /* any write clears HOB high bit of device control register */
851 bus->ifs[0].select &= ~(1 << 7);
852 bus->ifs[1].select &= ~(1 << 7);
853 }
854
855 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
856 {
857 IDEBus *bus = opaque;
858
859 #ifdef DEBUG_IDE
860 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
861 #endif
862
863 addr &= 7;
864
865 /* ignore writes to command block while busy with previous command */
866 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
867 return;
868
869 switch(addr) {
870 case 0:
871 break;
872 case 1:
873 ide_clear_hob(bus);
874 /* NOTE: data is written to the two drives */
875 bus->ifs[0].hob_feature = bus->ifs[0].feature;
876 bus->ifs[1].hob_feature = bus->ifs[1].feature;
877 bus->ifs[0].feature = val;
878 bus->ifs[1].feature = val;
879 break;
880 case 2:
881 ide_clear_hob(bus);
882 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
883 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
884 bus->ifs[0].nsector = val;
885 bus->ifs[1].nsector = val;
886 break;
887 case 3:
888 ide_clear_hob(bus);
889 bus->ifs[0].hob_sector = bus->ifs[0].sector;
890 bus->ifs[1].hob_sector = bus->ifs[1].sector;
891 bus->ifs[0].sector = val;
892 bus->ifs[1].sector = val;
893 break;
894 case 4:
895 ide_clear_hob(bus);
896 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
897 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
898 bus->ifs[0].lcyl = val;
899 bus->ifs[1].lcyl = val;
900 break;
901 case 5:
902 ide_clear_hob(bus);
903 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
904 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
905 bus->ifs[0].hcyl = val;
906 bus->ifs[1].hcyl = val;
907 break;
908 case 6:
909 /* FIXME: HOB readback uses bit 7 */
910 bus->ifs[0].select = (val & ~0x10) | 0xa0;
911 bus->ifs[1].select = (val | 0x10) | 0xa0;
912 /* select drive */
913 bus->unit = (val >> 4) & 1;
914 break;
915 default:
916 case 7:
917 /* command */
918 ide_exec_cmd(bus, val);
919 break;
920 }
921 }
922
923 #define HD_OK (1u << IDE_HD)
924 #define CD_OK (1u << IDE_CD)
925 #define CFA_OK (1u << IDE_CFATA)
926 #define HD_CFA_OK (HD_OK | CFA_OK)
927 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
928
929 /* See ACS-2 T13/2015-D Table B.2 Command codes */
930 static const uint8_t ide_cmd_table[0x100] = {
931 /* NOP not implemented, mandatory for CD */
932 [CFA_REQ_EXT_ERROR_CODE] = CFA_OK,
933 [WIN_DSM] = ALL_OK,
934 [WIN_DEVICE_RESET] = CD_OK,
935 [WIN_RECAL] = HD_CFA_OK,
936 [WIN_READ] = ALL_OK,
937 [WIN_READ_ONCE] = ALL_OK,
938 [WIN_READ_EXT] = HD_CFA_OK,
939 [WIN_READDMA_EXT] = HD_CFA_OK,
940 [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK,
941 [WIN_MULTREAD_EXT] = HD_CFA_OK,
942 [WIN_WRITE] = HD_CFA_OK,
943 [WIN_WRITE_ONCE] = HD_CFA_OK,
944 [WIN_WRITE_EXT] = HD_CFA_OK,
945 [WIN_WRITEDMA_EXT] = HD_CFA_OK,
946 [CFA_WRITE_SECT_WO_ERASE] = CFA_OK,
947 [WIN_MULTWRITE_EXT] = HD_CFA_OK,
948 [WIN_WRITE_VERIFY] = HD_CFA_OK,
949 [WIN_VERIFY] = HD_CFA_OK,
950 [WIN_VERIFY_ONCE] = HD_CFA_OK,
951 [WIN_VERIFY_EXT] = HD_CFA_OK,
952 [WIN_SEEK] = HD_CFA_OK,
953 [CFA_TRANSLATE_SECTOR] = CFA_OK,
954 [WIN_DIAGNOSE] = ALL_OK,
955 [WIN_SPECIFY] = HD_CFA_OK,
956 [WIN_STANDBYNOW2] = ALL_OK,
957 [WIN_IDLEIMMEDIATE2] = ALL_OK,
958 [WIN_STANDBY2] = ALL_OK,
959 [WIN_SETIDLE2] = ALL_OK,
960 [WIN_CHECKPOWERMODE2] = ALL_OK,
961 [WIN_SLEEPNOW2] = ALL_OK,
962 [WIN_PACKETCMD] = CD_OK,
963 [WIN_PIDENTIFY] = CD_OK,
964 [WIN_SMART] = HD_CFA_OK,
965 [CFA_ACCESS_METADATA_STORAGE] = CFA_OK,
966 [CFA_ERASE_SECTORS] = CFA_OK,
967 [WIN_MULTREAD] = HD_CFA_OK,
968 [WIN_MULTWRITE] = HD_CFA_OK,
969 [WIN_SETMULT] = HD_CFA_OK,
970 [WIN_READDMA] = HD_CFA_OK,
971 [WIN_READDMA_ONCE] = HD_CFA_OK,
972 [WIN_WRITEDMA] = HD_CFA_OK,
973 [WIN_WRITEDMA_ONCE] = HD_CFA_OK,
974 [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK,
975 [WIN_STANDBYNOW1] = ALL_OK,
976 [WIN_IDLEIMMEDIATE] = ALL_OK,
977 [WIN_STANDBY] = ALL_OK,
978 [WIN_SETIDLE1] = ALL_OK,
979 [WIN_CHECKPOWERMODE1] = ALL_OK,
980 [WIN_SLEEPNOW1] = ALL_OK,
981 [WIN_FLUSH_CACHE] = ALL_OK,
982 [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK,
983 [WIN_IDENTIFY] = ALL_OK,
984 [WIN_SETFEATURES] = ALL_OK,
985 [IBM_SENSE_CONDITION] = CFA_OK,
986 [CFA_WEAR_LEVEL] = CFA_OK,
987 [WIN_READ_NATIVE_MAX] = ALL_OK,
988 };
989
990 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
991 {
992 return cmd < ARRAY_SIZE(ide_cmd_table)
993 && (ide_cmd_table[cmd] & (1u << s->drive_kind));
994 }
995
996 void ide_exec_cmd(IDEBus *bus, uint32_t val)
997 {
998 IDEState *s;
999 int n;
1000 int lba48 = 0;
1001
1002 #if defined(DEBUG_IDE)
1003 printf("ide: CMD=%02x\n", val);
1004 #endif
1005 s = idebus_active_if(bus);
1006 /* ignore commands to non existent slave */
1007 if (s != bus->ifs && !s->bs)
1008 return;
1009
1010 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1011 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1012 return;
1013
1014 if (!ide_cmd_permitted(s, val)) {
1015 goto abort_cmd;
1016 }
1017
1018 switch(val) {
1019 case WIN_DSM:
1020 switch (s->feature) {
1021 case DSM_TRIM:
1022 if (!s->bs) {
1023 goto abort_cmd;
1024 }
1025 ide_sector_start_dma(s, IDE_DMA_TRIM);
1026 break;
1027 default:
1028 goto abort_cmd;
1029 }
1030 break;
1031 case WIN_IDENTIFY:
1032 if (s->bs && s->drive_kind != IDE_CD) {
1033 if (s->drive_kind != IDE_CFATA)
1034 ide_identify(s);
1035 else
1036 ide_cfata_identify(s);
1037 s->status = READY_STAT | SEEK_STAT;
1038 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1039 } else {
1040 if (s->drive_kind == IDE_CD) {
1041 ide_set_signature(s);
1042 }
1043 ide_abort_command(s);
1044 }
1045 ide_set_irq(s->bus);
1046 break;
1047 case WIN_SPECIFY:
1048 case WIN_RECAL:
1049 s->error = 0;
1050 s->status = READY_STAT | SEEK_STAT;
1051 ide_set_irq(s->bus);
1052 break;
1053 case WIN_SETMULT:
1054 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1055 /* Disable Read and Write Multiple */
1056 s->mult_sectors = 0;
1057 s->status = READY_STAT | SEEK_STAT;
1058 } else if ((s->nsector & 0xff) != 0 &&
1059 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1060 (s->nsector & (s->nsector - 1)) != 0)) {
1061 ide_abort_command(s);
1062 } else {
1063 s->mult_sectors = s->nsector & 0xff;
1064 s->status = READY_STAT | SEEK_STAT;
1065 }
1066 ide_set_irq(s->bus);
1067 break;
1068 case WIN_VERIFY_EXT:
1069 lba48 = 1;
1070 case WIN_VERIFY:
1071 case WIN_VERIFY_ONCE:
1072 /* do sector number check ? */
1073 ide_cmd_lba48_transform(s, lba48);
1074 s->status = READY_STAT | SEEK_STAT;
1075 ide_set_irq(s->bus);
1076 break;
1077 case WIN_READ_EXT:
1078 lba48 = 1;
1079 case WIN_READ:
1080 case WIN_READ_ONCE:
1081 if (s->drive_kind == IDE_CD) {
1082 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1083 goto abort_cmd;
1084 }
1085 if (!s->bs) {
1086 goto abort_cmd;
1087 }
1088 ide_cmd_lba48_transform(s, lba48);
1089 s->req_nb_sectors = 1;
1090 ide_sector_read(s);
1091 break;
1092 case WIN_WRITE_EXT:
1093 lba48 = 1;
1094 case WIN_WRITE:
1095 case WIN_WRITE_ONCE:
1096 case CFA_WRITE_SECT_WO_ERASE:
1097 case WIN_WRITE_VERIFY:
1098 if (!s->bs) {
1099 goto abort_cmd;
1100 }
1101 ide_cmd_lba48_transform(s, lba48);
1102 s->error = 0;
1103 s->status = SEEK_STAT | READY_STAT;
1104 s->req_nb_sectors = 1;
1105 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1106 s->media_changed = 1;
1107 break;
1108 case WIN_MULTREAD_EXT:
1109 lba48 = 1;
1110 case WIN_MULTREAD:
1111 if (!s->bs) {
1112 goto abort_cmd;
1113 }
1114 if (!s->mult_sectors) {
1115 goto abort_cmd;
1116 }
1117 ide_cmd_lba48_transform(s, lba48);
1118 s->req_nb_sectors = s->mult_sectors;
1119 ide_sector_read(s);
1120 break;
1121 case WIN_MULTWRITE_EXT:
1122 lba48 = 1;
1123 case WIN_MULTWRITE:
1124 case CFA_WRITE_MULTI_WO_ERASE:
1125 if (!s->bs) {
1126 goto abort_cmd;
1127 }
1128 if (!s->mult_sectors) {
1129 goto abort_cmd;
1130 }
1131 ide_cmd_lba48_transform(s, lba48);
1132 s->error = 0;
1133 s->status = SEEK_STAT | READY_STAT;
1134 s->req_nb_sectors = s->mult_sectors;
1135 n = s->nsector;
1136 if (n > s->req_nb_sectors)
1137 n = s->req_nb_sectors;
1138 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1139 s->media_changed = 1;
1140 break;
1141 case WIN_READDMA_EXT:
1142 lba48 = 1;
1143 case WIN_READDMA:
1144 case WIN_READDMA_ONCE:
1145 if (!s->bs) {
1146 goto abort_cmd;
1147 }
1148 ide_cmd_lba48_transform(s, lba48);
1149 ide_sector_start_dma(s, IDE_DMA_READ);
1150 break;
1151 case WIN_WRITEDMA_EXT:
1152 lba48 = 1;
1153 case WIN_WRITEDMA:
1154 case WIN_WRITEDMA_ONCE:
1155 if (!s->bs) {
1156 goto abort_cmd;
1157 }
1158 ide_cmd_lba48_transform(s, lba48);
1159 ide_sector_start_dma(s, IDE_DMA_WRITE);
1160 s->media_changed = 1;
1161 break;
1162 case WIN_READ_NATIVE_MAX_EXT:
1163 lba48 = 1;
1164 case WIN_READ_NATIVE_MAX:
1165 ide_cmd_lba48_transform(s, lba48);
1166 ide_set_sector(s, s->nb_sectors - 1);
1167 s->status = READY_STAT | SEEK_STAT;
1168 ide_set_irq(s->bus);
1169 break;
1170 case WIN_CHECKPOWERMODE1:
1171 case WIN_CHECKPOWERMODE2:
1172 s->error = 0;
1173 s->nsector = 0xff; /* device active or idle */
1174 s->status = READY_STAT | SEEK_STAT;
1175 ide_set_irq(s->bus);
1176 break;
1177 case WIN_SETFEATURES:
1178 if (!s->bs)
1179 goto abort_cmd;
1180 /* XXX: valid for CDROM ? */
1181 switch(s->feature) {
1182 case 0xcc: /* reverting to power-on defaults enable */
1183 case 0x66: /* reverting to power-on defaults disable */
1184 case 0x02: /* write cache enable */
1185 case 0x82: /* write cache disable */
1186 case 0xaa: /* read look-ahead enable */
1187 case 0x55: /* read look-ahead disable */
1188 case 0x05: /* set advanced power management mode */
1189 case 0x85: /* disable advanced power management mode */
1190 case 0x69: /* NOP */
1191 case 0x67: /* NOP */
1192 case 0x96: /* NOP */
1193 case 0x9a: /* NOP */
1194 case 0x42: /* enable Automatic Acoustic Mode */
1195 case 0xc2: /* disable Automatic Acoustic Mode */
1196 s->status = READY_STAT | SEEK_STAT;
1197 ide_set_irq(s->bus);
1198 break;
1199 case 0x03: { /* set transfer mode */
1200 uint8_t val = s->nsector & 0x07;
1201 uint16_t *identify_data = (uint16_t *)s->identify_data;
1202
1203 switch (s->nsector >> 3) {
1204 case 0x00: /* pio default */
1205 case 0x01: /* pio mode */
1206 put_le16(identify_data + 62,0x07);
1207 put_le16(identify_data + 63,0x07);
1208 put_le16(identify_data + 88,0x3f);
1209 break;
1210 case 0x02: /* sigle word dma mode*/
1211 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1212 put_le16(identify_data + 63,0x07);
1213 put_le16(identify_data + 88,0x3f);
1214 break;
1215 case 0x04: /* mdma mode */
1216 put_le16(identify_data + 62,0x07);
1217 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1218 put_le16(identify_data + 88,0x3f);
1219 break;
1220 case 0x08: /* udma mode */
1221 put_le16(identify_data + 62,0x07);
1222 put_le16(identify_data + 63,0x07);
1223 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
1224 break;
1225 default:
1226 goto abort_cmd;
1227 }
1228 s->status = READY_STAT | SEEK_STAT;
1229 ide_set_irq(s->bus);
1230 break;
1231 }
1232 default:
1233 goto abort_cmd;
1234 }
1235 break;
1236 case WIN_FLUSH_CACHE:
1237 case WIN_FLUSH_CACHE_EXT:
1238 ide_flush_cache(s);
1239 break;
1240 case WIN_STANDBY:
1241 case WIN_STANDBY2:
1242 case WIN_STANDBYNOW1:
1243 case WIN_STANDBYNOW2:
1244 case WIN_IDLEIMMEDIATE:
1245 case WIN_IDLEIMMEDIATE2:
1246 case WIN_SETIDLE1:
1247 case WIN_SETIDLE2:
1248 case WIN_SLEEPNOW1:
1249 case WIN_SLEEPNOW2:
1250 s->status = READY_STAT;
1251 ide_set_irq(s->bus);
1252 break;
1253 case WIN_SEEK:
1254 /* XXX: Check that seek is within bounds */
1255 s->status = READY_STAT | SEEK_STAT;
1256 ide_set_irq(s->bus);
1257 break;
1258 /* ATAPI commands */
1259 case WIN_PIDENTIFY:
1260 ide_atapi_identify(s);
1261 s->status = READY_STAT | SEEK_STAT;
1262 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1263 ide_set_irq(s->bus);
1264 break;
1265 case WIN_DIAGNOSE:
1266 ide_set_signature(s);
1267 if (s->drive_kind == IDE_CD)
1268 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1269 * devices to return a clear status register
1270 * with READY_STAT *not* set. */
1271 else
1272 s->status = READY_STAT | SEEK_STAT;
1273 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1274 * present.
1275 */
1276 ide_set_irq(s->bus);
1277 break;
1278 case WIN_DEVICE_RESET:
1279 ide_set_signature(s);
1280 s->status = 0x00; /* NOTE: READY is _not_ set */
1281 s->error = 0x01;
1282 break;
1283 case WIN_PACKETCMD:
1284 /* overlapping commands not supported */
1285 if (s->feature & 0x02)
1286 goto abort_cmd;
1287 s->status = READY_STAT | SEEK_STAT;
1288 s->atapi_dma = s->feature & 1;
1289 s->nsector = 1;
1290 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1291 ide_atapi_cmd);
1292 break;
1293 /* CF-ATA commands */
1294 case CFA_REQ_EXT_ERROR_CODE:
1295 s->error = 0x09; /* miscellaneous error */
1296 s->status = READY_STAT | SEEK_STAT;
1297 ide_set_irq(s->bus);
1298 break;
1299 case CFA_ERASE_SECTORS:
1300 case CFA_WEAR_LEVEL:
1301 if (val == CFA_WEAR_LEVEL)
1302 s->nsector = 0;
1303 if (val == CFA_ERASE_SECTORS)
1304 s->media_changed = 1;
1305 s->error = 0x00;
1306 s->status = READY_STAT | SEEK_STAT;
1307 ide_set_irq(s->bus);
1308 break;
1309 case CFA_TRANSLATE_SECTOR:
1310 s->error = 0x00;
1311 s->status = READY_STAT | SEEK_STAT;
1312 memset(s->io_buffer, 0, 0x200);
1313 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1314 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1315 s->io_buffer[0x02] = s->select; /* Head */
1316 s->io_buffer[0x03] = s->sector; /* Sector */
1317 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1318 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1319 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1320 s->io_buffer[0x13] = 0x00; /* Erase flag */
1321 s->io_buffer[0x18] = 0x00; /* Hot count */
1322 s->io_buffer[0x19] = 0x00; /* Hot count */
1323 s->io_buffer[0x1a] = 0x01; /* Hot count */
1324 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1325 ide_set_irq(s->bus);
1326 break;
1327 case CFA_ACCESS_METADATA_STORAGE:
1328 switch (s->feature) {
1329 case 0x02: /* Inquiry Metadata Storage */
1330 ide_cfata_metadata_inquiry(s);
1331 break;
1332 case 0x03: /* Read Metadata Storage */
1333 ide_cfata_metadata_read(s);
1334 break;
1335 case 0x04: /* Write Metadata Storage */
1336 ide_cfata_metadata_write(s);
1337 break;
1338 default:
1339 goto abort_cmd;
1340 }
1341 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1342 s->status = 0x00; /* NOTE: READY is _not_ set */
1343 ide_set_irq(s->bus);
1344 break;
1345 case IBM_SENSE_CONDITION:
1346 switch (s->feature) {
1347 case 0x01: /* sense temperature in device */
1348 s->nsector = 0x50; /* +20 C */
1349 break;
1350 default:
1351 goto abort_cmd;
1352 }
1353 s->status = READY_STAT | SEEK_STAT;
1354 ide_set_irq(s->bus);
1355 break;
1356
1357 case WIN_SMART:
1358 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
1359 goto abort_cmd;
1360 if (!s->smart_enabled && s->feature != SMART_ENABLE)
1361 goto abort_cmd;
1362 switch (s->feature) {
1363 case SMART_DISABLE:
1364 s->smart_enabled = 0;
1365 s->status = READY_STAT | SEEK_STAT;
1366 ide_set_irq(s->bus);
1367 break;
1368 case SMART_ENABLE:
1369 s->smart_enabled = 1;
1370 s->status = READY_STAT | SEEK_STAT;
1371 ide_set_irq(s->bus);
1372 break;
1373 case SMART_ATTR_AUTOSAVE:
1374 switch (s->sector) {
1375 case 0x00:
1376 s->smart_autosave = 0;
1377 break;
1378 case 0xf1:
1379 s->smart_autosave = 1;
1380 break;
1381 default:
1382 goto abort_cmd;
1383 }
1384 s->status = READY_STAT | SEEK_STAT;
1385 ide_set_irq(s->bus);
1386 break;
1387 case SMART_STATUS:
1388 if (!s->smart_errors) {
1389 s->hcyl = 0xc2;
1390 s->lcyl = 0x4f;
1391 } else {
1392 s->hcyl = 0x2c;
1393 s->lcyl = 0xf4;
1394 }
1395 s->status = READY_STAT | SEEK_STAT;
1396 ide_set_irq(s->bus);
1397 break;
1398 case SMART_READ_THRESH:
1399 memset(s->io_buffer, 0, 0x200);
1400 s->io_buffer[0] = 0x01; /* smart struct version */
1401 for (n=0; n<30; n++) {
1402 if (smart_attributes[n][0] == 0)
1403 break;
1404 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
1405 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
1406 }
1407 for (n=0; n<511; n++) /* checksum */
1408 s->io_buffer[511] += s->io_buffer[n];
1409 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1410 s->status = READY_STAT | SEEK_STAT;
1411 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1412 ide_set_irq(s->bus);
1413 break;
1414 case SMART_READ_DATA:
1415 memset(s->io_buffer, 0, 0x200);
1416 s->io_buffer[0] = 0x01; /* smart struct version */
1417 for (n=0; n<30; n++) {
1418 if (smart_attributes[n][0] == 0) {
1419 break;
1420 }
1421 int i;
1422 for(i = 0; i < 11; i++) {
1423 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1424 }
1425 }
1426 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1427 if (s->smart_selftest_count == 0) {
1428 s->io_buffer[363] = 0;
1429 } else {
1430 s->io_buffer[363] =
1431 s->smart_selftest_data[3 +
1432 (s->smart_selftest_count - 1) *
1433 24];
1434 }
1435 s->io_buffer[364] = 0x20;
1436 s->io_buffer[365] = 0x01;
1437 /* offline data collection capacity: execute + self-test*/
1438 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1439 s->io_buffer[368] = 0x03; /* smart capability (1) */
1440 s->io_buffer[369] = 0x00; /* smart capability (2) */
1441 s->io_buffer[370] = 0x01; /* error logging supported */
1442 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1443 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1444 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1445
1446 for (n=0; n<511; n++)
1447 s->io_buffer[511] += s->io_buffer[n];
1448 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1449 s->status = READY_STAT | SEEK_STAT;
1450 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1451 ide_set_irq(s->bus);
1452 break;
1453 case SMART_READ_LOG:
1454 switch (s->sector) {
1455 case 0x01: /* summary smart error log */
1456 memset(s->io_buffer, 0, 0x200);
1457 s->io_buffer[0] = 0x01;
1458 s->io_buffer[1] = 0x00; /* no error entries */
1459 s->io_buffer[452] = s->smart_errors & 0xff;
1460 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1461
1462 for (n=0; n<511; n++)
1463 s->io_buffer[511] += s->io_buffer[n];
1464 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1465 break;
1466 case 0x06: /* smart self test log */
1467 memset(s->io_buffer, 0, 0x200);
1468 s->io_buffer[0] = 0x01;
1469 if (s->smart_selftest_count == 0) {
1470 s->io_buffer[508] = 0;
1471 } else {
1472 s->io_buffer[508] = s->smart_selftest_count;
1473 for (n=2; n<506; n++)
1474 s->io_buffer[n] = s->smart_selftest_data[n];
1475 }
1476 for (n=0; n<511; n++)
1477 s->io_buffer[511] += s->io_buffer[n];
1478 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1479 break;
1480 default:
1481 goto abort_cmd;
1482 }
1483 s->status = READY_STAT | SEEK_STAT;
1484 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1485 ide_set_irq(s->bus);
1486 break;
1487 case SMART_EXECUTE_OFFLINE:
1488 switch (s->sector) {
1489 case 0: /* off-line routine */
1490 case 1: /* short self test */
1491 case 2: /* extended self test */
1492 s->smart_selftest_count++;
1493 if(s->smart_selftest_count > 21)
1494 s->smart_selftest_count = 0;
1495 n = 2 + (s->smart_selftest_count - 1) * 24;
1496 s->smart_selftest_data[n] = s->sector;
1497 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1498 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1499 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1500 s->status = READY_STAT | SEEK_STAT;
1501 ide_set_irq(s->bus);
1502 break;
1503 default:
1504 goto abort_cmd;
1505 }
1506 break;
1507 default:
1508 goto abort_cmd;
1509 }
1510 break;
1511 default:
1512 /* should not be reachable */
1513 abort_cmd:
1514 ide_abort_command(s);
1515 ide_set_irq(s->bus);
1516 break;
1517 }
1518 }
1519
1520 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1521 {
1522 IDEBus *bus = opaque;
1523 IDEState *s = idebus_active_if(bus);
1524 uint32_t addr;
1525 int ret, hob;
1526
1527 addr = addr1 & 7;
1528 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1529 //hob = s->select & (1 << 7);
1530 hob = 0;
1531 switch(addr) {
1532 case 0:
1533 ret = 0xff;
1534 break;
1535 case 1:
1536 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1537 (s != bus->ifs && !s->bs))
1538 ret = 0;
1539 else if (!hob)
1540 ret = s->error;
1541 else
1542 ret = s->hob_feature;
1543 break;
1544 case 2:
1545 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1546 ret = 0;
1547 else if (!hob)
1548 ret = s->nsector & 0xff;
1549 else
1550 ret = s->hob_nsector;
1551 break;
1552 case 3:
1553 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1554 ret = 0;
1555 else if (!hob)
1556 ret = s->sector;
1557 else
1558 ret = s->hob_sector;
1559 break;
1560 case 4:
1561 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1562 ret = 0;
1563 else if (!hob)
1564 ret = s->lcyl;
1565 else
1566 ret = s->hob_lcyl;
1567 break;
1568 case 5:
1569 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1570 ret = 0;
1571 else if (!hob)
1572 ret = s->hcyl;
1573 else
1574 ret = s->hob_hcyl;
1575 break;
1576 case 6:
1577 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
1578 ret = 0;
1579 else
1580 ret = s->select;
1581 break;
1582 default:
1583 case 7:
1584 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1585 (s != bus->ifs && !s->bs))
1586 ret = 0;
1587 else
1588 ret = s->status;
1589 qemu_irq_lower(bus->irq);
1590 break;
1591 }
1592 #ifdef DEBUG_IDE
1593 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1594 #endif
1595 return ret;
1596 }
1597
1598 uint32_t ide_status_read(void *opaque, uint32_t addr)
1599 {
1600 IDEBus *bus = opaque;
1601 IDEState *s = idebus_active_if(bus);
1602 int ret;
1603
1604 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1605 (s != bus->ifs && !s->bs))
1606 ret = 0;
1607 else
1608 ret = s->status;
1609 #ifdef DEBUG_IDE
1610 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1611 #endif
1612 return ret;
1613 }
1614
1615 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1616 {
1617 IDEBus *bus = opaque;
1618 IDEState *s;
1619 int i;
1620
1621 #ifdef DEBUG_IDE
1622 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1623 #endif
1624 /* common for both drives */
1625 if (!(bus->cmd & IDE_CMD_RESET) &&
1626 (val & IDE_CMD_RESET)) {
1627 /* reset low to high */
1628 for(i = 0;i < 2; i++) {
1629 s = &bus->ifs[i];
1630 s->status = BUSY_STAT | SEEK_STAT;
1631 s->error = 0x01;
1632 }
1633 } else if ((bus->cmd & IDE_CMD_RESET) &&
1634 !(val & IDE_CMD_RESET)) {
1635 /* high to low */
1636 for(i = 0;i < 2; i++) {
1637 s = &bus->ifs[i];
1638 if (s->drive_kind == IDE_CD)
1639 s->status = 0x00; /* NOTE: READY is _not_ set */
1640 else
1641 s->status = READY_STAT | SEEK_STAT;
1642 ide_set_signature(s);
1643 }
1644 }
1645
1646 bus->cmd = val;
1647 }
1648
1649 /*
1650 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1651 * transferred from the device to the guest), false if it's a PIO in
1652 */
1653 static bool ide_is_pio_out(IDEState *s)
1654 {
1655 if (s->end_transfer_func == ide_sector_write ||
1656 s->end_transfer_func == ide_atapi_cmd) {
1657 return false;
1658 } else if (s->end_transfer_func == ide_sector_read ||
1659 s->end_transfer_func == ide_transfer_stop ||
1660 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1661 s->end_transfer_func == ide_dummy_transfer_stop) {
1662 return true;
1663 }
1664
1665 abort();
1666 }
1667
1668 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1669 {
1670 IDEBus *bus = opaque;
1671 IDEState *s = idebus_active_if(bus);
1672 uint8_t *p;
1673
1674 /* PIO data access allowed only when DRQ bit is set. The result of a write
1675 * during PIO out is indeterminate, just ignore it. */
1676 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1677 return;
1678 }
1679
1680 p = s->data_ptr;
1681 *(uint16_t *)p = le16_to_cpu(val);
1682 p += 2;
1683 s->data_ptr = p;
1684 if (p >= s->data_end)
1685 s->end_transfer_func(s);
1686 }
1687
1688 uint32_t ide_data_readw(void *opaque, uint32_t addr)
1689 {
1690 IDEBus *bus = opaque;
1691 IDEState *s = idebus_active_if(bus);
1692 uint8_t *p;
1693 int ret;
1694
1695 /* PIO data access allowed only when DRQ bit is set. The result of a read
1696 * during PIO in is indeterminate, return 0 and don't move forward. */
1697 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1698 return 0;
1699 }
1700
1701 p = s->data_ptr;
1702 ret = cpu_to_le16(*(uint16_t *)p);
1703 p += 2;
1704 s->data_ptr = p;
1705 if (p >= s->data_end)
1706 s->end_transfer_func(s);
1707 return ret;
1708 }
1709
1710 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
1711 {
1712 IDEBus *bus = opaque;
1713 IDEState *s = idebus_active_if(bus);
1714 uint8_t *p;
1715
1716 /* PIO data access allowed only when DRQ bit is set. The result of a write
1717 * during PIO out is indeterminate, just ignore it. */
1718 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
1719 return;
1720 }
1721
1722 p = s->data_ptr;
1723 *(uint32_t *)p = le32_to_cpu(val);
1724 p += 4;
1725 s->data_ptr = p;
1726 if (p >= s->data_end)
1727 s->end_transfer_func(s);
1728 }
1729
1730 uint32_t ide_data_readl(void *opaque, uint32_t addr)
1731 {
1732 IDEBus *bus = opaque;
1733 IDEState *s = idebus_active_if(bus);
1734 uint8_t *p;
1735 int ret;
1736
1737 /* PIO data access allowed only when DRQ bit is set. The result of a read
1738 * during PIO in is indeterminate, return 0 and don't move forward. */
1739 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
1740 return 0;
1741 }
1742
1743 p = s->data_ptr;
1744 ret = cpu_to_le32(*(uint32_t *)p);
1745 p += 4;
1746 s->data_ptr = p;
1747 if (p >= s->data_end)
1748 s->end_transfer_func(s);
1749 return ret;
1750 }
1751
1752 static void ide_dummy_transfer_stop(IDEState *s)
1753 {
1754 s->data_ptr = s->io_buffer;
1755 s->data_end = s->io_buffer;
1756 s->io_buffer[0] = 0xff;
1757 s->io_buffer[1] = 0xff;
1758 s->io_buffer[2] = 0xff;
1759 s->io_buffer[3] = 0xff;
1760 }
1761
1762 static void ide_reset(IDEState *s)
1763 {
1764 #ifdef DEBUG_IDE
1765 printf("ide: reset\n");
1766 #endif
1767 if (s->drive_kind == IDE_CFATA)
1768 s->mult_sectors = 0;
1769 else
1770 s->mult_sectors = MAX_MULT_SECTORS;
1771 /* ide regs */
1772 s->feature = 0;
1773 s->error = 0;
1774 s->nsector = 0;
1775 s->sector = 0;
1776 s->lcyl = 0;
1777 s->hcyl = 0;
1778
1779 /* lba48 */
1780 s->hob_feature = 0;
1781 s->hob_sector = 0;
1782 s->hob_nsector = 0;
1783 s->hob_lcyl = 0;
1784 s->hob_hcyl = 0;
1785
1786 s->select = 0xa0;
1787 s->status = READY_STAT | SEEK_STAT;
1788
1789 s->lba48 = 0;
1790
1791 /* ATAPI specific */
1792 s->sense_key = 0;
1793 s->asc = 0;
1794 s->cdrom_changed = 0;
1795 s->packet_transfer_size = 0;
1796 s->elementary_transfer_size = 0;
1797 s->io_buffer_index = 0;
1798 s->cd_sector_size = 0;
1799 s->atapi_dma = 0;
1800 /* ATA DMA state */
1801 s->io_buffer_size = 0;
1802 s->req_nb_sectors = 0;
1803
1804 ide_set_signature(s);
1805 /* init the transfer handler so that 0xffff is returned on data
1806 accesses */
1807 s->end_transfer_func = ide_dummy_transfer_stop;
1808 ide_dummy_transfer_stop(s);
1809 s->media_changed = 0;
1810 }
1811
1812 void ide_bus_reset(IDEBus *bus)
1813 {
1814 bus->unit = 0;
1815 bus->cmd = 0;
1816 ide_reset(&bus->ifs[0]);
1817 ide_reset(&bus->ifs[1]);
1818 ide_clear_hob(bus);
1819
1820 /* pending async DMA */
1821 if (bus->dma->aiocb) {
1822 #ifdef DEBUG_AIO
1823 printf("aio_cancel\n");
1824 #endif
1825 bdrv_aio_cancel(bus->dma->aiocb);
1826 bus->dma->aiocb = NULL;
1827 }
1828
1829 /* reset dma provider too */
1830 bus->dma->ops->reset(bus->dma);
1831 }
1832
1833 static bool ide_cd_is_tray_open(void *opaque)
1834 {
1835 return ((IDEState *)opaque)->tray_open;
1836 }
1837
1838 static bool ide_cd_is_medium_locked(void *opaque)
1839 {
1840 return ((IDEState *)opaque)->tray_locked;
1841 }
1842
1843 static const BlockDevOps ide_cd_block_ops = {
1844 .change_media_cb = ide_cd_change_cb,
1845 .eject_request_cb = ide_cd_eject_request_cb,
1846 .is_tray_open = ide_cd_is_tray_open,
1847 .is_medium_locked = ide_cd_is_medium_locked,
1848 };
1849
1850 int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
1851 const char *version, const char *serial, const char *model,
1852 uint64_t wwn)
1853 {
1854 int cylinders, heads, secs;
1855 uint64_t nb_sectors;
1856
1857 s->bs = bs;
1858 s->drive_kind = kind;
1859
1860 bdrv_get_geometry(bs, &nb_sectors);
1861 bdrv_guess_geometry(bs, &cylinders, &heads, &secs);
1862 if (cylinders < 1 || cylinders > 16383) {
1863 error_report("cyls must be between 1 and 16383");
1864 return -1;
1865 }
1866 if (heads < 1 || heads > 16) {
1867 error_report("heads must be between 1 and 16");
1868 return -1;
1869 }
1870 if (secs < 1 || secs > 63) {
1871 error_report("secs must be between 1 and 63");
1872 return -1;
1873 }
1874 s->cylinders = cylinders;
1875 s->heads = heads;
1876 s->sectors = secs;
1877 s->nb_sectors = nb_sectors;
1878 s->wwn = wwn;
1879 /* The SMART values should be preserved across power cycles
1880 but they aren't. */
1881 s->smart_enabled = 1;
1882 s->smart_autosave = 1;
1883 s->smart_errors = 0;
1884 s->smart_selftest_count = 0;
1885 if (kind == IDE_CD) {
1886 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
1887 bdrv_set_buffer_alignment(bs, 2048);
1888 } else {
1889 if (!bdrv_is_inserted(s->bs)) {
1890 error_report("Device needs media, but drive is empty");
1891 return -1;
1892 }
1893 if (bdrv_is_read_only(bs)) {
1894 error_report("Can't use a read-only drive");
1895 return -1;
1896 }
1897 }
1898 if (serial) {
1899 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
1900 } else {
1901 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
1902 "QM%05d", s->drive_serial);
1903 }
1904 if (model) {
1905 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
1906 } else {
1907 switch (kind) {
1908 case IDE_CD:
1909 strcpy(s->drive_model_str, "QEMU DVD-ROM");
1910 break;
1911 case IDE_CFATA:
1912 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
1913 break;
1914 default:
1915 strcpy(s->drive_model_str, "QEMU HARDDISK");
1916 break;
1917 }
1918 }
1919
1920 if (version) {
1921 pstrcpy(s->version, sizeof(s->version), version);
1922 } else {
1923 pstrcpy(s->version, sizeof(s->version), QEMU_VERSION);
1924 }
1925
1926 ide_reset(s);
1927 bdrv_iostatus_enable(bs);
1928 return 0;
1929 }
1930
1931 static void ide_init1(IDEBus *bus, int unit)
1932 {
1933 static int drive_serial = 1;
1934 IDEState *s = &bus->ifs[unit];
1935
1936 s->bus = bus;
1937 s->unit = unit;
1938 s->drive_serial = drive_serial++;
1939 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
1940 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
1941 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
1942 memset(s->io_buffer, 0, s->io_buffer_total_len);
1943
1944 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
1945 memset(s->smart_selftest_data, 0, 512);
1946
1947 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
1948 ide_sector_write_timer_cb, s);
1949 }
1950
1951 static void ide_nop_start(IDEDMA *dma, IDEState *s,
1952 BlockDriverCompletionFunc *cb)
1953 {
1954 }
1955
1956 static int ide_nop(IDEDMA *dma)
1957 {
1958 return 0;
1959 }
1960
1961 static int ide_nop_int(IDEDMA *dma, int x)
1962 {
1963 return 0;
1964 }
1965
1966 static void ide_nop_restart(void *opaque, int x, RunState y)
1967 {
1968 }
1969
1970 static const IDEDMAOps ide_dma_nop_ops = {
1971 .start_dma = ide_nop_start,
1972 .start_transfer = ide_nop,
1973 .prepare_buf = ide_nop_int,
1974 .rw_buf = ide_nop_int,
1975 .set_unit = ide_nop_int,
1976 .add_status = ide_nop_int,
1977 .set_inactive = ide_nop,
1978 .restart_cb = ide_nop_restart,
1979 .reset = ide_nop,
1980 };
1981
1982 static IDEDMA ide_dma_nop = {
1983 .ops = &ide_dma_nop_ops,
1984 .aiocb = NULL,
1985 };
1986
1987 void ide_init2(IDEBus *bus, qemu_irq irq)
1988 {
1989 int i;
1990
1991 for(i = 0; i < 2; i++) {
1992 ide_init1(bus, i);
1993 ide_reset(&bus->ifs[i]);
1994 }
1995 bus->irq = irq;
1996 bus->dma = &ide_dma_nop;
1997 }
1998
1999 /* TODO convert users to qdev and remove */
2000 void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
2001 DriveInfo *hd1, qemu_irq irq)
2002 {
2003 int i;
2004 DriveInfo *dinfo;
2005
2006 for(i = 0; i < 2; i++) {
2007 dinfo = i == 0 ? hd0 : hd1;
2008 ide_init1(bus, i);
2009 if (dinfo) {
2010 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
2011 dinfo->media_cd ? IDE_CD : IDE_HD, NULL,
2012 *dinfo->serial ? dinfo->serial : NULL,
2013 NULL, 0) < 0) {
2014 error_report("Can't set up IDE drive %s", dinfo->id);
2015 exit(1);
2016 }
2017 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
2018 } else {
2019 ide_reset(&bus->ifs[i]);
2020 }
2021 }
2022 bus->irq = irq;
2023 bus->dma = &ide_dma_nop;
2024 }
2025
2026 static const MemoryRegionPortio ide_portio_list[] = {
2027 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2028 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2029 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2030 PORTIO_END_OF_LIST(),
2031 };
2032
2033 static const MemoryRegionPortio ide_portio2_list[] = {
2034 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2035 PORTIO_END_OF_LIST(),
2036 };
2037
2038 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2039 {
2040 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2041 bridge has been setup properly to always register with ISA. */
2042 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2043
2044 if (iobase2) {
2045 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2046 }
2047 }
2048
2049 static bool is_identify_set(void *opaque, int version_id)
2050 {
2051 IDEState *s = opaque;
2052
2053 return s->identify_set != 0;
2054 }
2055
2056 static EndTransferFunc* transfer_end_table[] = {
2057 ide_sector_read,
2058 ide_sector_write,
2059 ide_transfer_stop,
2060 ide_atapi_cmd_reply_end,
2061 ide_atapi_cmd,
2062 ide_dummy_transfer_stop,
2063 };
2064
2065 static int transfer_end_table_idx(EndTransferFunc *fn)
2066 {
2067 int i;
2068
2069 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2070 if (transfer_end_table[i] == fn)
2071 return i;
2072
2073 return -1;
2074 }
2075
2076 static int ide_drive_post_load(void *opaque, int version_id)
2077 {
2078 IDEState *s = opaque;
2079
2080 if (version_id < 3) {
2081 if (s->sense_key == UNIT_ATTENTION &&
2082 s->asc == ASC_MEDIUM_MAY_HAVE_CHANGED) {
2083 s->cdrom_changed = 1;
2084 }
2085 }
2086 return 0;
2087 }
2088
2089 static int ide_drive_pio_post_load(void *opaque, int version_id)
2090 {
2091 IDEState *s = opaque;
2092
2093 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2094 return -EINVAL;
2095 }
2096 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2097 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2098 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2099
2100 return 0;
2101 }
2102
2103 static void ide_drive_pio_pre_save(void *opaque)
2104 {
2105 IDEState *s = opaque;
2106 int idx;
2107
2108 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2109 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2110
2111 idx = transfer_end_table_idx(s->end_transfer_func);
2112 if (idx == -1) {
2113 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2114 __func__);
2115 s->end_transfer_fn_idx = 2;
2116 } else {
2117 s->end_transfer_fn_idx = idx;
2118 }
2119 }
2120
2121 static bool ide_drive_pio_state_needed(void *opaque)
2122 {
2123 IDEState *s = opaque;
2124
2125 return ((s->status & DRQ_STAT) != 0)
2126 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
2127 }
2128
2129 static bool ide_tray_state_needed(void *opaque)
2130 {
2131 IDEState *s = opaque;
2132
2133 return s->tray_open || s->tray_locked;
2134 }
2135
2136 static bool ide_atapi_gesn_needed(void *opaque)
2137 {
2138 IDEState *s = opaque;
2139
2140 return s->events.new_media || s->events.eject_request;
2141 }
2142
2143 static bool ide_error_needed(void *opaque)
2144 {
2145 IDEBus *bus = opaque;
2146
2147 return (bus->error_status != 0);
2148 }
2149
2150 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2151 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2152 .name ="ide_drive/atapi/gesn_state",
2153 .version_id = 1,
2154 .minimum_version_id = 1,
2155 .minimum_version_id_old = 1,
2156 .fields = (VMStateField []) {
2157 VMSTATE_BOOL(events.new_media, IDEState),
2158 VMSTATE_BOOL(events.eject_request, IDEState),
2159 VMSTATE_END_OF_LIST()
2160 }
2161 };
2162
2163 static const VMStateDescription vmstate_ide_tray_state = {
2164 .name = "ide_drive/tray_state",
2165 .version_id = 1,
2166 .minimum_version_id = 1,
2167 .minimum_version_id_old = 1,
2168 .fields = (VMStateField[]) {
2169 VMSTATE_BOOL(tray_open, IDEState),
2170 VMSTATE_BOOL(tray_locked, IDEState),
2171 VMSTATE_END_OF_LIST()
2172 }
2173 };
2174
2175 static const VMStateDescription vmstate_ide_drive_pio_state = {
2176 .name = "ide_drive/pio_state",
2177 .version_id = 1,
2178 .minimum_version_id = 1,
2179 .minimum_version_id_old = 1,
2180 .pre_save = ide_drive_pio_pre_save,
2181 .post_load = ide_drive_pio_post_load,
2182 .fields = (VMStateField []) {
2183 VMSTATE_INT32(req_nb_sectors, IDEState),
2184 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2185 vmstate_info_uint8, uint8_t),
2186 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2187 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2188 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2189 VMSTATE_INT32(elementary_transfer_size, IDEState),
2190 VMSTATE_INT32(packet_transfer_size, IDEState),
2191 VMSTATE_END_OF_LIST()
2192 }
2193 };
2194
2195 const VMStateDescription vmstate_ide_drive = {
2196 .name = "ide_drive",
2197 .version_id = 3,
2198 .minimum_version_id = 0,
2199 .minimum_version_id_old = 0,
2200 .post_load = ide_drive_post_load,
2201 .fields = (VMStateField []) {
2202 VMSTATE_INT32(mult_sectors, IDEState),
2203 VMSTATE_INT32(identify_set, IDEState),
2204 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2205 VMSTATE_UINT8(feature, IDEState),
2206 VMSTATE_UINT8(error, IDEState),
2207 VMSTATE_UINT32(nsector, IDEState),
2208 VMSTATE_UINT8(sector, IDEState),
2209 VMSTATE_UINT8(lcyl, IDEState),
2210 VMSTATE_UINT8(hcyl, IDEState),
2211 VMSTATE_UINT8(hob_feature, IDEState),
2212 VMSTATE_UINT8(hob_sector, IDEState),
2213 VMSTATE_UINT8(hob_nsector, IDEState),
2214 VMSTATE_UINT8(hob_lcyl, IDEState),
2215 VMSTATE_UINT8(hob_hcyl, IDEState),
2216 VMSTATE_UINT8(select, IDEState),
2217 VMSTATE_UINT8(status, IDEState),
2218 VMSTATE_UINT8(lba48, IDEState),
2219 VMSTATE_UINT8(sense_key, IDEState),
2220 VMSTATE_UINT8(asc, IDEState),
2221 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2222 VMSTATE_END_OF_LIST()
2223 },
2224 .subsections = (VMStateSubsection []) {
2225 {
2226 .vmsd = &vmstate_ide_drive_pio_state,
2227 .needed = ide_drive_pio_state_needed,
2228 }, {
2229 .vmsd = &vmstate_ide_tray_state,
2230 .needed = ide_tray_state_needed,
2231 }, {
2232 .vmsd = &vmstate_ide_atapi_gesn_state,
2233 .needed = ide_atapi_gesn_needed,
2234 }, {
2235 /* empty */
2236 }
2237 }
2238 };
2239
2240 static const VMStateDescription vmstate_ide_error_status = {
2241 .name ="ide_bus/error",
2242 .version_id = 1,
2243 .minimum_version_id = 1,
2244 .minimum_version_id_old = 1,
2245 .fields = (VMStateField []) {
2246 VMSTATE_INT32(error_status, IDEBus),
2247 VMSTATE_END_OF_LIST()
2248 }
2249 };
2250
2251 const VMStateDescription vmstate_ide_bus = {
2252 .name = "ide_bus",
2253 .version_id = 1,
2254 .minimum_version_id = 1,
2255 .minimum_version_id_old = 1,
2256 .fields = (VMStateField []) {
2257 VMSTATE_UINT8(cmd, IDEBus),
2258 VMSTATE_UINT8(unit, IDEBus),
2259 VMSTATE_END_OF_LIST()
2260 },
2261 .subsections = (VMStateSubsection []) {
2262 {
2263 .vmsd = &vmstate_ide_error_status,
2264 .needed = ide_error_needed,
2265 }, {
2266 /* empty */
2267 }
2268 }
2269 };
2270
2271 void ide_drive_get(DriveInfo **hd, int max_bus)
2272 {
2273 int i;
2274
2275 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2276 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2277 exit(1);
2278 }
2279
2280 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2281 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2282 }
2283 }
Qemu copy for testing