2 * QEMU IDE Emulation: MacIO support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include <hw/ppc_mac.h>
27 #include <hw/mac_dbdma.h>
28 #include "block/block.h"
29 #include "sysemu/dma.h"
31 #include <hw/ide/internal.h>
33 /***********************************************************/
34 /* MacIO based PowerPC IDE */
36 typedef struct MACIOIDEState
{
39 BlockDriverAIOCB
*aiocb
;
42 #define MACIO_PAGE_SIZE 4096
44 static void pmac_ide_atapi_transfer_cb(void *opaque
, int ret
)
46 DBDMA_io
*io
= opaque
;
47 MACIOIDEState
*m
= io
->opaque
;
48 IDEState
*s
= idebus_active_if(&m
->bus
);
52 qemu_sglist_destroy(&s
->sg
);
53 ide_atapi_io_error(s
, ret
);
57 if (s
->io_buffer_size
> 0) {
59 qemu_sglist_destroy(&s
->sg
);
61 s
->packet_transfer_size
-= s
->io_buffer_size
;
63 s
->io_buffer_index
+= s
->io_buffer_size
;
64 s
->lba
+= s
->io_buffer_index
>> 11;
65 s
->io_buffer_index
&= 0x7ff;
68 if (s
->packet_transfer_size
<= 0)
75 /* launch next transfer */
77 s
->io_buffer_size
= io
->len
;
79 qemu_sglist_init(&s
->sg
, io
->len
/ MACIO_PAGE_SIZE
+ 1,
81 qemu_sglist_add(&s
->sg
, io
->addr
, io
->len
);
85 m
->aiocb
= dma_bdrv_read(s
->bs
, &s
->sg
,
86 (int64_t)(s
->lba
<< 2) + (s
->io_buffer_index
>> 9),
87 pmac_ide_atapi_transfer_cb
, io
);
91 bdrv_acct_done(s
->bs
, &s
->acct
);
95 static void pmac_ide_transfer_cb(void *opaque
, int ret
)
97 DBDMA_io
*io
= opaque
;
98 MACIOIDEState
*m
= io
->opaque
;
99 IDEState
*s
= idebus_active_if(&m
->bus
);
105 qemu_sglist_destroy(&s
->sg
);
110 sector_num
= ide_get_sector(s
);
111 if (s
->io_buffer_size
> 0) {
113 qemu_sglist_destroy(&s
->sg
);
114 n
= (s
->io_buffer_size
+ 0x1ff) >> 9;
116 ide_set_sector(s
, sector_num
);
120 /* end of transfer ? */
121 if (s
->nsector
== 0) {
122 s
->status
= READY_STAT
| SEEK_STAT
;
131 /* launch next transfer */
133 s
->io_buffer_index
= 0;
134 s
->io_buffer_size
= io
->len
;
136 qemu_sglist_init(&s
->sg
, io
->len
/ MACIO_PAGE_SIZE
+ 1,
137 &dma_context_memory
);
138 qemu_sglist_add(&s
->sg
, io
->addr
, io
->len
);
142 switch (s
->dma_cmd
) {
144 m
->aiocb
= dma_bdrv_read(s
->bs
, &s
->sg
, sector_num
,
145 pmac_ide_transfer_cb
, io
);
148 m
->aiocb
= dma_bdrv_write(s
->bs
, &s
->sg
, sector_num
,
149 pmac_ide_transfer_cb
, io
);
152 m
->aiocb
= dma_bdrv_io(s
->bs
, &s
->sg
, sector_num
,
153 ide_issue_trim
, pmac_ide_transfer_cb
, s
,
154 DMA_DIRECTION_TO_DEVICE
);
160 if (s
->dma_cmd
== IDE_DMA_READ
|| s
->dma_cmd
== IDE_DMA_WRITE
) {
161 bdrv_acct_done(s
->bs
, &s
->acct
);
166 static void pmac_ide_transfer(DBDMA_io
*io
)
168 MACIOIDEState
*m
= io
->opaque
;
169 IDEState
*s
= idebus_active_if(&m
->bus
);
171 s
->io_buffer_size
= 0;
172 if (s
->drive_kind
== IDE_CD
) {
173 bdrv_acct_start(s
->bs
, &s
->acct
, io
->len
, BDRV_ACCT_READ
);
174 pmac_ide_atapi_transfer_cb(io
, 0);
178 switch (s
->dma_cmd
) {
180 bdrv_acct_start(s
->bs
, &s
->acct
, io
->len
, BDRV_ACCT_READ
);
183 bdrv_acct_start(s
->bs
, &s
->acct
, io
->len
, BDRV_ACCT_WRITE
);
189 pmac_ide_transfer_cb(io
, 0);
192 static void pmac_ide_flush(DBDMA_io
*io
)
194 MACIOIDEState
*m
= io
->opaque
;
201 /* PowerMac IDE memory IO */
202 static void pmac_ide_writeb (void *opaque
,
203 hwaddr addr
, uint32_t val
)
205 MACIOIDEState
*d
= opaque
;
207 addr
= (addr
& 0xFFF) >> 4;
210 ide_ioport_write(&d
->bus
, addr
, val
);
214 ide_cmd_write(&d
->bus
, 0, val
);
221 static uint32_t pmac_ide_readb (void *opaque
,hwaddr addr
)
224 MACIOIDEState
*d
= opaque
;
226 addr
= (addr
& 0xFFF) >> 4;
229 retval
= ide_ioport_read(&d
->bus
, addr
);
233 retval
= ide_status_read(&d
->bus
, 0);
242 static void pmac_ide_writew (void *opaque
,
243 hwaddr addr
, uint32_t val
)
245 MACIOIDEState
*d
= opaque
;
247 addr
= (addr
& 0xFFF) >> 4;
250 ide_data_writew(&d
->bus
, 0, val
);
254 static uint32_t pmac_ide_readw (void *opaque
,hwaddr addr
)
257 MACIOIDEState
*d
= opaque
;
259 addr
= (addr
& 0xFFF) >> 4;
261 retval
= ide_data_readw(&d
->bus
, 0);
265 retval
= bswap16(retval
);
269 static void pmac_ide_writel (void *opaque
,
270 hwaddr addr
, uint32_t val
)
272 MACIOIDEState
*d
= opaque
;
274 addr
= (addr
& 0xFFF) >> 4;
277 ide_data_writel(&d
->bus
, 0, val
);
281 static uint32_t pmac_ide_readl (void *opaque
,hwaddr addr
)
284 MACIOIDEState
*d
= opaque
;
286 addr
= (addr
& 0xFFF) >> 4;
288 retval
= ide_data_readl(&d
->bus
, 0);
292 retval
= bswap32(retval
);
296 static const MemoryRegionOps pmac_ide_ops
= {
309 .endianness
= DEVICE_NATIVE_ENDIAN
,
312 static const VMStateDescription vmstate_pmac
= {
315 .minimum_version_id
= 0,
316 .minimum_version_id_old
= 0,
317 .fields
= (VMStateField
[]) {
318 VMSTATE_IDE_BUS(bus
, MACIOIDEState
),
319 VMSTATE_IDE_DRIVES(bus
.ifs
, MACIOIDEState
),
320 VMSTATE_END_OF_LIST()
324 static void pmac_ide_reset(void *opaque
)
326 MACIOIDEState
*d
= opaque
;
328 ide_bus_reset(&d
->bus
);
331 /* hd_table must contain 4 block drivers */
332 /* PowerMac uses memory mapped registers, not I/O. Return the memory
333 I/O index to access the ide. */
334 MemoryRegion
*pmac_ide_init (DriveInfo
**hd_table
, qemu_irq irq
,
335 void *dbdma
, int channel
, qemu_irq dma_irq
)
339 d
= g_malloc0(sizeof(MACIOIDEState
));
340 ide_init2_with_non_qdev_drives(&d
->bus
, hd_table
[0], hd_table
[1], irq
);
343 DBDMA_register_channel(dbdma
, channel
, dma_irq
, pmac_ide_transfer
, pmac_ide_flush
, d
);
345 memory_region_init_io(&d
->mem
, &pmac_ide_ops
, d
, "pmac-ide", 0x1000);
346 vmstate_register(NULL
, 0, &vmstate_pmac
, d
);
347 qemu_register_reset(pmac_ide_reset
, d
);