hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/ppc_mac.h>
  27 #include <hw/mac_dbdma.h>
  28 #include "block.h"
  29 #include "block_int.h"
  30 #include "dma.h"
  31
  32 #include <hw/ide/internal.h>
  33
  34 /***********************************************************/
  35 /* MacIO based PowerPC IDE */
  36
  37 typedef struct MACIOIDEState {
  38     MemoryRegion mem;
  39     IDEBus bus;
  40     BlockDriverAIOCB *aiocb;
  41 } MACIOIDEState;
  42
  43 #define MACIO_PAGE_SIZE 4096
  44
  45 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
  46 {
  47     DBDMA_io *io = opaque;
  48     MACIOIDEState *m = io->opaque;
  49     IDEState *s = idebus_active_if(&m->bus);
  50
  51     if (ret < 0) {
  52         m->aiocb = NULL;
  53         qemu_sglist_destroy(&s->sg);
  54         ide_atapi_io_error(s, ret);
  55         goto done;
  56     }
  57
  58     if (s->io_buffer_size > 0) {
  59         m->aiocb = NULL;
  60         qemu_sglist_destroy(&s->sg);
  61
  62         s->packet_transfer_size -= s->io_buffer_size;
  63
  64         s->io_buffer_index += s->io_buffer_size;
  65         s->lba += s->io_buffer_index >> 11;
  66         s->io_buffer_index &= 0x7ff;
  67     }
  68
  69     if (s->packet_transfer_size <= 0)
  70         ide_atapi_cmd_ok(s);
  71
  72     if (io->len == 0) {
  73         goto done;
  74     }
  75
  76     /* launch next transfer */
  77
  78     s->io_buffer_size = io->len;
  79
  80     qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
  81     qemu_sglist_add(&s->sg, io->addr, io->len);
  82     io->addr += io->len;
  83     io->len = 0;
  84
  85     m->aiocb = dma_bdrv_read(s->bs, &s->sg,
  86                              (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
  87                              pmac_ide_atapi_transfer_cb, io);
  88     if (!m->aiocb) {
  89         qemu_sglist_destroy(&s->sg);
  90         /* Note: media not present is the most likely case */
  91         ide_atapi_cmd_error(s, SENSE_NOT_READY,
  92                             ASC_MEDIUM_NOT_PRESENT);
  93         goto done;
  94     }
  95     return;
  96
  97 done:
  98     bdrv_acct_done(s->bs, &s->acct);
  99     io->dma_end(opaque);
 100     return;
 101 }
 102
 103 static void pmac_ide_transfer_cb(void *opaque, int ret)
 104 {
 105     DBDMA_io *io = opaque;
 106     MACIOIDEState *m = io->opaque;
 107     IDEState *s = idebus_active_if(&m->bus);
 108     int n;
 109     int64_t sector_num;
 110
 111     if (ret < 0) {
 112         m->aiocb = NULL;
 113         qemu_sglist_destroy(&s->sg);
 114         ide_dma_error(s);
 115         goto done;
 116     }
 117
 118     sector_num = ide_get_sector(s);
 119     if (s->io_buffer_size > 0) {
 120         m->aiocb = NULL;
 121         qemu_sglist_destroy(&s->sg);
 122         n = (s->io_buffer_size + 0x1ff) >> 9;
 123         sector_num += n;
 124         ide_set_sector(s, sector_num);
 125         s->nsector -= n;
 126     }
 127
 128     /* end of transfer ? */
 129     if (s->nsector == 0) {
 130         s->status = READY_STAT | SEEK_STAT;
 131         ide_set_irq(s->bus);
 132     }
 133
 134     /* end of DMA ? */
 135     if (io->len == 0) {
 136         goto done;
 137     }
 138
 139     /* launch next transfer */
 140
 141     s->io_buffer_index = 0;
 142     s->io_buffer_size = io->len;
 143
 144     qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
 145     qemu_sglist_add(&s->sg, io->addr, io->len);
 146     io->addr += io->len;
 147     io->len = 0;
 148
 149     switch (s->dma_cmd) {
 150     case IDE_DMA_READ:
 151         m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
 152                                  pmac_ide_transfer_cb, io);
 153         break;
 154     case IDE_DMA_WRITE:
 155         m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
 156                                   pmac_ide_transfer_cb, io);
 157         break;
 158     case IDE_DMA_TRIM:
 159         m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
 160                                ide_issue_trim, pmac_ide_transfer_cb, s, 1);
 161         break;
 162     }
 163
 164     if (!m->aiocb)
 165         pmac_ide_transfer_cb(io, -1);
 166     return;
 167 done:
 168     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 169         bdrv_acct_done(s->bs, &s->acct);
 170     }
 171     io->dma_end(io);
 172 }
 173
 174 static void pmac_ide_transfer(DBDMA_io *io)
 175 {
 176     MACIOIDEState *m = io->opaque;
 177     IDEState *s = idebus_active_if(&m->bus);
 178
 179     s->io_buffer_size = 0;
 180     if (s->drive_kind == IDE_CD) {
 181         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
 182         pmac_ide_atapi_transfer_cb(io, 0);
 183         return;
 184     }
 185
 186     switch (s->dma_cmd) {
 187     case IDE_DMA_READ:
 188         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
 189         break;
 190     case IDE_DMA_WRITE:
 191         bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE);
 192         break;
 193     default:
 194         break;
 195     }
 196
 197     pmac_ide_transfer_cb(io, 0);
 198 }
 199
 200 static void pmac_ide_flush(DBDMA_io *io)
 201 {
 202     MACIOIDEState *m = io->opaque;
 203
 204     if (m->aiocb)
 205         qemu_aio_flush();
 206 }
 207
 208 /* PowerMac IDE memory IO */
 209 static void pmac_ide_writeb (void *opaque,
 210                              target_phys_addr_t addr, uint32_t val)
 211 {
 212     MACIOIDEState *d = opaque;
 213
 214     addr = (addr & 0xFFF) >> 4;
 215     switch (addr) {
 216     case 1 ... 7:
 217         ide_ioport_write(&d->bus, addr, val);
 218         break;
 219     case 8:
 220     case 22:
 221         ide_cmd_write(&d->bus, 0, val);
 222         break;
 223     default:
 224         break;
 225     }
 226 }
 227
 228 static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
 229 {
 230     uint8_t retval;
 231     MACIOIDEState *d = opaque;
 232
 233     addr = (addr & 0xFFF) >> 4;
 234     switch (addr) {
 235     case 1 ... 7:
 236         retval = ide_ioport_read(&d->bus, addr);
 237         break;
 238     case 8:
 239     case 22:
 240         retval = ide_status_read(&d->bus, 0);
 241         break;
 242     default:
 243         retval = 0xFF;
 244         break;
 245     }
 246     return retval;
 247 }
 248
 249 static void pmac_ide_writew (void *opaque,
 250                              target_phys_addr_t addr, uint32_t val)
 251 {
 252     MACIOIDEState *d = opaque;
 253
 254     addr = (addr & 0xFFF) >> 4;
 255     val = bswap16(val);
 256     if (addr == 0) {
 257         ide_data_writew(&d->bus, 0, val);
 258     }
 259 }
 260
 261 static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
 262 {
 263     uint16_t retval;
 264     MACIOIDEState *d = opaque;
 265
 266     addr = (addr & 0xFFF) >> 4;
 267     if (addr == 0) {
 268         retval = ide_data_readw(&d->bus, 0);
 269     } else {
 270         retval = 0xFFFF;
 271     }
 272     retval = bswap16(retval);
 273     return retval;
 274 }
 275
 276 static void pmac_ide_writel (void *opaque,
 277                              target_phys_addr_t addr, uint32_t val)
 278 {
 279     MACIOIDEState *d = opaque;
 280
 281     addr = (addr & 0xFFF) >> 4;
 282     val = bswap32(val);
 283     if (addr == 0) {
 284         ide_data_writel(&d->bus, 0, val);
 285     }
 286 }
 287
 288 static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
 289 {
 290     uint32_t retval;
 291     MACIOIDEState *d = opaque;
 292
 293     addr = (addr & 0xFFF) >> 4;
 294     if (addr == 0) {
 295         retval = ide_data_readl(&d->bus, 0);
 296     } else {
 297         retval = 0xFFFFFFFF;
 298     }
 299     retval = bswap32(retval);
 300     return retval;
 301 }
 302
 303 static MemoryRegionOps pmac_ide_ops = {
 304     .old_mmio = {
 305         .write = {
 306             pmac_ide_writeb,
 307             pmac_ide_writew,
 308             pmac_ide_writel,
 309         },
 310         .read = {
 311             pmac_ide_readb,
 312             pmac_ide_readw,
 313             pmac_ide_readl,
 314         },
 315     },
 316     .endianness = DEVICE_NATIVE_ENDIAN,
 317 };
 318
 319 static const VMStateDescription vmstate_pmac = {
 320     .name = "ide",
 321     .version_id = 3,
 322     .minimum_version_id = 0,
 323     .minimum_version_id_old = 0,
 324     .fields      = (VMStateField []) {
 325         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 326         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 327         VMSTATE_END_OF_LIST()
 328     }
 329 };
 330
 331 static void pmac_ide_reset(void *opaque)
 332 {
 333     MACIOIDEState *d = opaque;
 334
 335     ide_bus_reset(&d->bus);
 336 }
 337
 338 /* hd_table must contain 4 block drivers */
 339 /* PowerMac uses memory mapped registers, not I/O. Return the memory
 340    I/O index to access the ide. */
 341 MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
 342                              void *dbdma, int channel, qemu_irq dma_irq)
 343 {
 344     MACIOIDEState *d;
 345
 346     d = g_malloc0(sizeof(MACIOIDEState));
 347     ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
 348
 349     if (dbdma)
 350         DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
 351
 352     memory_region_init_io(&d->mem, &pmac_ide_ops, d, "pmac-ide", 0x1000);
 353     vmstate_register(NULL, 0, &vmstate_pmac, d);
 354     qemu_register_reset(pmac_ide_reset, d);
 355
 356     return &d->mem;
 357 }