hw/ide/pci.c

   1 /*
   2  * QEMU IDE Emulation: PCI Bus support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/pc.h>
  27 #include <hw/pci.h>
  28 #include <hw/isa.h>
  29 #include "block.h"
  30 #include "block_int.h"
  31 #include "dma.h"
  32
  33 #include <hw/ide/pci.h>
  34
  35 #define BMDMA_PAGE_SIZE 4096
  36
  37 static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
  38                             BlockDriverCompletionFunc *dma_cb)
  39 {
  40     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  41
  42     bm->unit = s->unit;
  43     bm->dma_cb = dma_cb;
  44     bm->cur_prd_last = 0;
  45     bm->cur_prd_addr = 0;
  46     bm->cur_prd_len = 0;
  47     bm->sector_num = ide_get_sector(s);
  48     bm->nsector = s->nsector;
  49
  50     if (bm->status & BM_STATUS_DMAING) {
  51         bm->dma_cb(bmdma_active_if(bm), 0);
  52     }
  53 }
  54
  55 /* return 0 if buffer completed */
  56 static int bmdma_prepare_buf(IDEDMA *dma, int is_write)
  57 {
  58     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  59     IDEState *s = bmdma_active_if(bm);
  60     struct {
  61         uint32_t addr;
  62         uint32_t size;
  63     } prd;
  64     int l, len;
  65
  66     qemu_sglist_init(&s->sg, s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
  67     s->io_buffer_size = 0;
  68     for(;;) {
  69         if (bm->cur_prd_len == 0) {
  70             /* end of table (with a fail safe of one page) */
  71             if (bm->cur_prd_last ||
  72                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
  73                 return s->io_buffer_size != 0;
  74             cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
  75             bm->cur_addr += 8;
  76             prd.addr = le32_to_cpu(prd.addr);
  77             prd.size = le32_to_cpu(prd.size);
  78             len = prd.size & 0xfffe;
  79             if (len == 0)
  80                 len = 0x10000;
  81             bm->cur_prd_len = len;
  82             bm->cur_prd_addr = prd.addr;
  83             bm->cur_prd_last = (prd.size & 0x80000000);
  84         }
  85         l = bm->cur_prd_len;
  86         if (l > 0) {
  87             qemu_sglist_add(&s->sg, bm->cur_prd_addr, l);
  88             bm->cur_prd_addr += l;
  89             bm->cur_prd_len -= l;
  90             s->io_buffer_size += l;
  91         }
  92     }
  93     return 1;
  94 }
  95
  96 /* return 0 if buffer completed */
  97 static int bmdma_rw_buf(IDEDMA *dma, int is_write)
  98 {
  99     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 100     IDEState *s = bmdma_active_if(bm);
 101     struct {
 102         uint32_t addr;
 103         uint32_t size;
 104     } prd;
 105     int l, len;
 106
 107     for(;;) {
 108         l = s->io_buffer_size - s->io_buffer_index;
 109         if (l <= 0)
 110             break;
 111         if (bm->cur_prd_len == 0) {
 112             /* end of table (with a fail safe of one page) */
 113             if (bm->cur_prd_last ||
 114                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
 115                 return 0;
 116             cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
 117             bm->cur_addr += 8;
 118             prd.addr = le32_to_cpu(prd.addr);
 119             prd.size = le32_to_cpu(prd.size);
 120             len = prd.size & 0xfffe;
 121             if (len == 0)
 122                 len = 0x10000;
 123             bm->cur_prd_len = len;
 124             bm->cur_prd_addr = prd.addr;
 125             bm->cur_prd_last = (prd.size & 0x80000000);
 126         }
 127         if (l > bm->cur_prd_len)
 128             l = bm->cur_prd_len;
 129         if (l > 0) {
 130             if (is_write) {
 131                 cpu_physical_memory_write(bm->cur_prd_addr,
 132                                           s->io_buffer + s->io_buffer_index, l);
 133             } else {
 134                 cpu_physical_memory_read(bm->cur_prd_addr,
 135                                           s->io_buffer + s->io_buffer_index, l);
 136             }
 137             bm->cur_prd_addr += l;
 138             bm->cur_prd_len -= l;
 139             s->io_buffer_index += l;
 140         }
 141     }
 142     return 1;
 143 }
 144
 145 static int bmdma_set_unit(IDEDMA *dma, int unit)
 146 {
 147     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 148     bm->unit = unit;
 149
 150     return 0;
 151 }
 152
 153 static int bmdma_add_status(IDEDMA *dma, int status)
 154 {
 155     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 156     bm->status |= status;
 157
 158     return 0;
 159 }
 160
 161 static int bmdma_set_inactive(IDEDMA *dma)
 162 {
 163     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 164
 165     bm->status &= ~BM_STATUS_DMAING;
 166     bm->dma_cb = NULL;
 167     bm->unit = -1;
 168
 169     return 0;
 170 }
 171
 172 static void bmdma_restart_dma(BMDMAState *bm, enum ide_dma_cmd dma_cmd)
 173 {
 174     IDEState *s = bmdma_active_if(bm);
 175
 176     ide_set_sector(s, bm->sector_num);
 177     s->io_buffer_index = 0;
 178     s->io_buffer_size = 0;
 179     s->nsector = bm->nsector;
 180     s->dma_cmd = dma_cmd;
 181     bm->cur_addr = bm->addr;
 182     bm->dma_cb = ide_dma_cb;
 183     bmdma_start_dma(&bm->dma, s, bm->dma_cb);
 184 }
 185
 186 /* TODO This should be common IDE code */
 187 static void bmdma_restart_bh(void *opaque)
 188 {
 189     BMDMAState *bm = opaque;
 190     IDEBus *bus = bm->bus;
 191     int is_read;
 192     int error_status;
 193
 194     qemu_bh_delete(bm->bh);
 195     bm->bh = NULL;
 196
 197     if (bm->unit == (uint8_t) -1) {
 198         return;
 199     }
 200
 201     is_read = !!(bus->error_status & BM_STATUS_RETRY_READ);
 202
 203     /* The error status must be cleared before resubmitting the request: The
 204      * request may fail again, and this case can only be distinguished if the
 205      * called function can set a new error status. */
 206     error_status = bus->error_status;
 207     bus->error_status = 0;
 208
 209     if (error_status & BM_STATUS_DMA_RETRY) {
 210         if (error_status & BM_STATUS_RETRY_TRIM) {
 211             bmdma_restart_dma(bm, IDE_DMA_TRIM);
 212         } else {
 213             bmdma_restart_dma(bm, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
 214         }
 215     } else if (error_status & BM_STATUS_PIO_RETRY) {
 216         if (is_read) {
 217             ide_sector_read(bmdma_active_if(bm));
 218         } else {
 219             ide_sector_write(bmdma_active_if(bm));
 220         }
 221     } else if (error_status & BM_STATUS_RETRY_FLUSH) {
 222         ide_flush_cache(bmdma_active_if(bm));
 223     }
 224 }
 225
 226 static void bmdma_restart_cb(void *opaque, int running, int reason)
 227 {
 228     IDEDMA *dma = opaque;
 229     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 230
 231     if (!running)
 232         return;
 233
 234     if (!bm->bh) {
 235         bm->bh = qemu_bh_new(bmdma_restart_bh, &bm->dma);
 236         qemu_bh_schedule(bm->bh);
 237     }
 238 }
 239
 240 static void bmdma_cancel(BMDMAState *bm)
 241 {
 242     if (bm->status & BM_STATUS_DMAING) {
 243         /* cancel DMA request */
 244         bmdma_set_inactive(&bm->dma);
 245     }
 246 }
 247
 248 static int bmdma_reset(IDEDMA *dma)
 249 {
 250     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 251
 252 #ifdef DEBUG_IDE
 253     printf("ide: dma_reset\n");
 254 #endif
 255     bmdma_cancel(bm);
 256     bm->cmd = 0;
 257     bm->status = 0;
 258     bm->addr = 0;
 259     bm->cur_addr = 0;
 260     bm->cur_prd_last = 0;
 261     bm->cur_prd_addr = 0;
 262     bm->cur_prd_len = 0;
 263     bm->sector_num = 0;
 264     bm->nsector = 0;
 265
 266     return 0;
 267 }
 268
 269 static int bmdma_start_transfer(IDEDMA *dma)
 270 {
 271     return 0;
 272 }
 273
 274 static void bmdma_irq(void *opaque, int n, int level)
 275 {
 276     BMDMAState *bm = opaque;
 277
 278     if (!level) {
 279         /* pass through lower */
 280         qemu_set_irq(bm->irq, level);
 281         return;
 282     }
 283
 284     bm->status |= BM_STATUS_INT;
 285
 286     /* trigger the real irq */
 287     qemu_set_irq(bm->irq, level);
 288 }
 289
 290 void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
 291 {
 292     BMDMAState *bm = opaque;
 293 #ifdef DEBUG_IDE
 294     printf("%s: 0x%08x\n", __func__, val);
 295 #endif
 296
 297     /* Ignore writes to SSBM if it keeps the old value */
 298     if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
 299         if (!(val & BM_CMD_START)) {
 300             /*
 301              * We can't cancel Scatter Gather DMA in the middle of the
 302              * operation or a partial (not full) DMA transfer would reach
 303              * the storage so we wait for completion instead (we beahve
 304              * like if the DMA was completed by the time the guest trying
 305              * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
 306              * set).
 307              *
 308              * In the future we'll be able to safely cancel the I/O if the
 309              * whole DMA operation will be submitted to disk with a single
 310              * aio operation with preadv/pwritev.
 311              */
 312             if (bm->bus->dma->aiocb) {
 313                 qemu_aio_flush();
 314                 assert(bm->bus->dma->aiocb == NULL);
 315                 assert((bm->status & BM_STATUS_DMAING) == 0);
 316             }
 317         } else {
 318             bm->cur_addr = bm->addr;
 319             if (!(bm->status & BM_STATUS_DMAING)) {
 320                 bm->status |= BM_STATUS_DMAING;
 321                 /* start dma transfer if possible */
 322                 if (bm->dma_cb)
 323                     bm->dma_cb(bmdma_active_if(bm), 0);
 324             }
 325         }
 326     }
 327
 328     bm->cmd = val & 0x09;
 329 }
 330
 331 static void bmdma_addr_read(IORange *ioport, uint64_t addr,
 332                             unsigned width, uint64_t *data)
 333 {
 334     BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
 335     uint32_t mask = (1ULL << (width * 8)) - 1;
 336
 337     *data = (bm->addr >> (addr * 8)) & mask;
 338 #ifdef DEBUG_IDE
 339     printf("%s: 0x%08x\n", __func__, (unsigned)*data);
 340 #endif
 341 }
 342
 343 static void bmdma_addr_write(IORange *ioport, uint64_t addr,
 344                              unsigned width, uint64_t data)
 345 {
 346     BMDMAState *bm = container_of(ioport, BMDMAState, addr_ioport);
 347     int shift = addr * 8;
 348     uint32_t mask = (1ULL << (width * 8)) - 1;
 349
 350 #ifdef DEBUG_IDE
 351     printf("%s: 0x%08x\n", __func__, (unsigned)data);
 352 #endif
 353     bm->addr &= ~(mask << shift);
 354     bm->addr |= ((data & mask) << shift) & ~3;
 355 }
 356
 357 const IORangeOps bmdma_addr_ioport_ops = {
 358     .read = bmdma_addr_read,
 359     .write = bmdma_addr_write,
 360 };
 361
 362 static bool ide_bmdma_current_needed(void *opaque)
 363 {
 364     BMDMAState *bm = opaque;
 365
 366     return (bm->cur_prd_len != 0);
 367 }
 368
 369 static bool ide_bmdma_status_needed(void *opaque)
 370 {
 371     BMDMAState *bm = opaque;
 372
 373     /* Older versions abused some bits in the status register for internal
 374      * error state. If any of these bits are set, we must add a subsection to
 375      * transfer the real status register */
 376     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 377
 378     return ((bm->status & abused_bits) != 0);
 379 }
 380
 381 static void ide_bmdma_pre_save(void *opaque)
 382 {
 383     BMDMAState *bm = opaque;
 384     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 385
 386     bm->migration_compat_status =
 387         (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
 388 }
 389
 390 /* This function accesses bm->bus->error_status which is loaded only after
 391  * BMDMA itself. This is why the function is called from ide_pci_post_load
 392  * instead of being registered with VMState where it would run too early. */
 393 static int ide_bmdma_post_load(void *opaque, int version_id)
 394 {
 395     BMDMAState *bm = opaque;
 396     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 397
 398     if (bm->status == 0) {
 399         bm->status = bm->migration_compat_status & ~abused_bits;
 400         bm->bus->error_status |= bm->migration_compat_status & abused_bits;
 401     }
 402
 403     return 0;
 404 }
 405
 406 static const VMStateDescription vmstate_bmdma_current = {
 407     .name = "ide bmdma_current",
 408     .version_id = 1,
 409     .minimum_version_id = 1,
 410     .minimum_version_id_old = 1,
 411     .fields      = (VMStateField []) {
 412         VMSTATE_UINT32(cur_addr, BMDMAState),
 413         VMSTATE_UINT32(cur_prd_last, BMDMAState),
 414         VMSTATE_UINT32(cur_prd_addr, BMDMAState),
 415         VMSTATE_UINT32(cur_prd_len, BMDMAState),
 416         VMSTATE_END_OF_LIST()
 417     }
 418 };
 419
 420 const VMStateDescription vmstate_bmdma_status = {
 421     .name ="ide bmdma/status",
 422     .version_id = 1,
 423     .minimum_version_id = 1,
 424     .minimum_version_id_old = 1,
 425     .fields = (VMStateField []) {
 426         VMSTATE_UINT8(status, BMDMAState),
 427         VMSTATE_END_OF_LIST()
 428     }
 429 };
 430
 431 static const VMStateDescription vmstate_bmdma = {
 432     .name = "ide bmdma",
 433     .version_id = 3,
 434     .minimum_version_id = 0,
 435     .minimum_version_id_old = 0,
 436     .pre_save  = ide_bmdma_pre_save,
 437     .fields      = (VMStateField []) {
 438         VMSTATE_UINT8(cmd, BMDMAState),
 439         VMSTATE_UINT8(migration_compat_status, BMDMAState),
 440         VMSTATE_UINT32(addr, BMDMAState),
 441         VMSTATE_INT64(sector_num, BMDMAState),
 442         VMSTATE_UINT32(nsector, BMDMAState),
 443         VMSTATE_UINT8(unit, BMDMAState),
 444         VMSTATE_END_OF_LIST()
 445     },
 446     .subsections = (VMStateSubsection []) {
 447         {
 448             .vmsd = &vmstate_bmdma_current,
 449             .needed = ide_bmdma_current_needed,
 450         }, {
 451             .vmsd = &vmstate_bmdma_status,
 452             .needed = ide_bmdma_status_needed,
 453         }, {
 454             /* empty */
 455         }
 456     }
 457 };
 458
 459 static int ide_pci_post_load(void *opaque, int version_id)
 460 {
 461     PCIIDEState *d = opaque;
 462     int i;
 463
 464     for(i = 0; i < 2; i++) {
 465         /* current versions always store 0/1, but older version
 466            stored bigger values. We only need last bit */
 467         d->bmdma[i].unit &= 1;
 468         ide_bmdma_post_load(&d->bmdma[i], -1);
 469     }
 470
 471     return 0;
 472 }
 473
 474 const VMStateDescription vmstate_ide_pci = {
 475     .name = "ide",
 476     .version_id = 3,
 477     .minimum_version_id = 0,
 478     .minimum_version_id_old = 0,
 479     .post_load = ide_pci_post_load,
 480     .fields      = (VMStateField []) {
 481         VMSTATE_PCI_DEVICE(dev, PCIIDEState),
 482         VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
 483                              vmstate_bmdma, BMDMAState),
 484         VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
 485         VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
 486         VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
 487         VMSTATE_END_OF_LIST()
 488     }
 489 };
 490
 491 void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
 492 {
 493     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
 494     static const int bus[4]  = { 0, 0, 1, 1 };
 495     static const int unit[4] = { 0, 1, 0, 1 };
 496     int i;
 497
 498     for (i = 0; i < 4; i++) {
 499         if (hd_table[i] == NULL)
 500             continue;
 501         ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
 502     }
 503 }
 504
 505 static const struct IDEDMAOps bmdma_ops = {
 506     .start_dma = bmdma_start_dma,
 507     .start_transfer = bmdma_start_transfer,
 508     .prepare_buf = bmdma_prepare_buf,
 509     .rw_buf = bmdma_rw_buf,
 510     .set_unit = bmdma_set_unit,
 511     .add_status = bmdma_add_status,
 512     .set_inactive = bmdma_set_inactive,
 513     .restart_cb = bmdma_restart_cb,
 514     .reset = bmdma_reset,
 515 };
 516
 517 void bmdma_init(IDEBus *bus, BMDMAState *bm)
 518 {
 519     qemu_irq *irq;
 520
 521     if (bus->dma == &bm->dma) {
 522         return;
 523     }
 524
 525     bm->dma.ops = &bmdma_ops;
 526     bus->dma = &bm->dma;
 527     bm->irq = bus->irq;
 528     irq = qemu_allocate_irqs(bmdma_irq, bm, 1);
 529     bus->irq = *irq;
 530 }