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ide: create ide/pci.h for common ide pci definitions
[qemu.git] / hw / ide / pci.c
1 /*
2 * QEMU IDE Emulation: PCI Bus support.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/pc.h>
27 #include <hw/pci.h>
28 #include <hw/isa.h>
29 #include "block.h"
30 #include "block_int.h"
31 #include "sysemu.h"
32 #include "dma.h"
33
34 #include <hw/ide/pci.h>
35
36 /***********************************************************/
37 /* PCI IDE definitions */
38
39 /* CMD646 specific */
40 #define MRDMODE 0x71
41 #define MRDMODE_INTR_CH0 0x04
42 #define MRDMODE_INTR_CH1 0x08
43 #define MRDMODE_BLK_CH0 0x10
44 #define MRDMODE_BLK_CH1 0x20
45 #define UDIDETCR0 0x73
46 #define UDIDETCR1 0x7B
47
48 static void cmd646_update_irq(PCIIDEState *d);
49
50 static void ide_map(PCIDevice *pci_dev, int region_num,
51 uint32_t addr, uint32_t size, int type)
52 {
53 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
54 IDEBus *bus;
55
56 if (region_num <= 3) {
57 bus = &d->bus[(region_num >> 1)];
58 if (region_num & 1) {
59 register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
60 register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
61 } else {
62 register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
63 register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
64
65 /* data ports */
66 register_ioport_write(addr, 2, 2, ide_data_writew, bus);
67 register_ioport_read(addr, 2, 2, ide_data_readw, bus);
68 register_ioport_write(addr, 4, 4, ide_data_writel, bus);
69 register_ioport_read(addr, 4, 4, ide_data_readl, bus);
70 }
71 }
72 }
73
74 static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
75 {
76 BMDMAState *bm = opaque;
77 #ifdef DEBUG_IDE
78 printf("%s: 0x%08x\n", __func__, val);
79 #endif
80 if (!(val & BM_CMD_START)) {
81 /* XXX: do it better */
82 ide_dma_cancel(bm);
83 bm->cmd = val & 0x09;
84 } else {
85 if (!(bm->status & BM_STATUS_DMAING)) {
86 bm->status |= BM_STATUS_DMAING;
87 /* start dma transfer if possible */
88 if (bm->dma_cb)
89 bm->dma_cb(bm, 0);
90 }
91 bm->cmd = val & 0x09;
92 }
93 }
94
95 static uint32_t bmdma_readb(void *opaque, uint32_t addr)
96 {
97 BMDMAState *bm = opaque;
98 PCIIDEState *pci_dev;
99 uint32_t val;
100
101 switch(addr & 3) {
102 case 0:
103 val = bm->cmd;
104 break;
105 case 1:
106 pci_dev = bm->pci_dev;
107 if (pci_dev->type == IDE_TYPE_CMD646) {
108 val = pci_dev->dev.config[MRDMODE];
109 } else {
110 val = 0xff;
111 }
112 break;
113 case 2:
114 val = bm->status;
115 break;
116 case 3:
117 pci_dev = bm->pci_dev;
118 if (pci_dev->type == IDE_TYPE_CMD646) {
119 if (bm == &pci_dev->bmdma[0])
120 val = pci_dev->dev.config[UDIDETCR0];
121 else
122 val = pci_dev->dev.config[UDIDETCR1];
123 } else {
124 val = 0xff;
125 }
126 break;
127 default:
128 val = 0xff;
129 break;
130 }
131 #ifdef DEBUG_IDE
132 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
133 #endif
134 return val;
135 }
136
137 static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
138 {
139 BMDMAState *bm = opaque;
140 PCIIDEState *pci_dev;
141 #ifdef DEBUG_IDE
142 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
143 #endif
144 switch(addr & 3) {
145 case 1:
146 pci_dev = bm->pci_dev;
147 if (pci_dev->type == IDE_TYPE_CMD646) {
148 pci_dev->dev.config[MRDMODE] =
149 (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
150 cmd646_update_irq(pci_dev);
151 }
152 break;
153 case 2:
154 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
155 break;
156 case 3:
157 pci_dev = bm->pci_dev;
158 if (pci_dev->type == IDE_TYPE_CMD646) {
159 if (bm == &pci_dev->bmdma[0])
160 pci_dev->dev.config[UDIDETCR0] = val;
161 else
162 pci_dev->dev.config[UDIDETCR1] = val;
163 }
164 break;
165 }
166 }
167
168 static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
169 {
170 BMDMAState *bm = opaque;
171 uint32_t val;
172 val = (bm->addr >> ((addr & 3) * 8)) & 0xff;
173 #ifdef DEBUG_IDE
174 printf("%s: 0x%08x\n", __func__, val);
175 #endif
176 return val;
177 }
178
179 static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
180 {
181 BMDMAState *bm = opaque;
182 int shift = (addr & 3) * 8;
183 #ifdef DEBUG_IDE
184 printf("%s: 0x%08x\n", __func__, val);
185 #endif
186 bm->addr &= ~(0xFF << shift);
187 bm->addr |= ((val & 0xFF) << shift) & ~3;
188 bm->cur_addr = bm->addr;
189 }
190
191 static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
192 {
193 BMDMAState *bm = opaque;
194 uint32_t val;
195 val = (bm->addr >> ((addr & 3) * 8)) & 0xffff;
196 #ifdef DEBUG_IDE
197 printf("%s: 0x%08x\n", __func__, val);
198 #endif
199 return val;
200 }
201
202 static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
203 {
204 BMDMAState *bm = opaque;
205 int shift = (addr & 3) * 8;
206 #ifdef DEBUG_IDE
207 printf("%s: 0x%08x\n", __func__, val);
208 #endif
209 bm->addr &= ~(0xFFFF << shift);
210 bm->addr |= ((val & 0xFFFF) << shift) & ~3;
211 bm->cur_addr = bm->addr;
212 }
213
214 static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
215 {
216 BMDMAState *bm = opaque;
217 uint32_t val;
218 val = bm->addr;
219 #ifdef DEBUG_IDE
220 printf("%s: 0x%08x\n", __func__, val);
221 #endif
222 return val;
223 }
224
225 static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
226 {
227 BMDMAState *bm = opaque;
228 #ifdef DEBUG_IDE
229 printf("%s: 0x%08x\n", __func__, val);
230 #endif
231 bm->addr = val & ~3;
232 bm->cur_addr = bm->addr;
233 }
234
235 static void bmdma_map(PCIDevice *pci_dev, int region_num,
236 uint32_t addr, uint32_t size, int type)
237 {
238 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
239 int i;
240
241 for(i = 0;i < 2; i++) {
242 BMDMAState *bm = &d->bmdma[i];
243 d->bus[i].bmdma = bm;
244 bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
245 bm->bus = d->bus+i;
246 qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
247
248 register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
249
250 register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
251 register_ioport_read(addr, 4, 1, bmdma_readb, bm);
252
253 register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
254 register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
255 register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
256 register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
257 register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
258 register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
259 addr += 8;
260 }
261 }
262
263 static void pci_ide_save(QEMUFile* f, void *opaque)
264 {
265 PCIIDEState *d = opaque;
266 int i;
267
268 pci_device_save(&d->dev, f);
269
270 for(i = 0; i < 2; i++) {
271 BMDMAState *bm = &d->bmdma[i];
272 uint8_t ifidx;
273 qemu_put_8s(f, &bm->cmd);
274 qemu_put_8s(f, &bm->status);
275 qemu_put_be32s(f, &bm->addr);
276 qemu_put_sbe64s(f, &bm->sector_num);
277 qemu_put_be32s(f, &bm->nsector);
278 ifidx = bm->unit + 2*i;
279 qemu_put_8s(f, &ifidx);
280 /* XXX: if a transfer is pending, we do not save it yet */
281 }
282
283 /* per IDE interface data */
284 for(i = 0; i < 2; i++) {
285 idebus_save(f, d->bus+i);
286 }
287
288 /* per IDE drive data */
289 for(i = 0; i < 2; i++) {
290 ide_save(f, &d->bus[i].ifs[0]);
291 ide_save(f, &d->bus[i].ifs[1]);
292 }
293 }
294
295 static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
296 {
297 PCIIDEState *d = opaque;
298 int ret, i;
299
300 if (version_id != 2 && version_id != 3)
301 return -EINVAL;
302 ret = pci_device_load(&d->dev, f);
303 if (ret < 0)
304 return ret;
305
306 for(i = 0; i < 2; i++) {
307 BMDMAState *bm = &d->bmdma[i];
308 uint8_t ifidx;
309 qemu_get_8s(f, &bm->cmd);
310 qemu_get_8s(f, &bm->status);
311 qemu_get_be32s(f, &bm->addr);
312 qemu_get_sbe64s(f, &bm->sector_num);
313 qemu_get_be32s(f, &bm->nsector);
314 qemu_get_8s(f, &ifidx);
315 bm->unit = ifidx & 1;
316 /* XXX: if a transfer is pending, we do not save it yet */
317 }
318
319 /* per IDE interface data */
320 for(i = 0; i < 2; i++) {
321 idebus_load(f, d->bus+i, version_id);
322 }
323
324 /* per IDE drive data */
325 for(i = 0; i < 2; i++) {
326 ide_load(f, &d->bus[i].ifs[0], version_id);
327 ide_load(f, &d->bus[i].ifs[1], version_id);
328 }
329 return 0;
330 }
331
332 static void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
333 {
334 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
335 static const int bus[4] = { 0, 0, 1, 1 };
336 static const int unit[4] = { 0, 1, 0, 1 };
337 int i;
338
339 for (i = 0; i < 4; i++) {
340 if (hd_table[i] == NULL)
341 continue;
342 ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
343 }
344 }
345
346 /* XXX: call it also when the MRDMODE is changed from the PCI config
347 registers */
348 static void cmd646_update_irq(PCIIDEState *d)
349 {
350 int pci_level;
351 pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
352 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
353 ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
354 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
355 qemu_set_irq(d->dev.irq[0], pci_level);
356 }
357
358 /* the PCI irq level is the logical OR of the two channels */
359 static void cmd646_set_irq(void *opaque, int channel, int level)
360 {
361 PCIIDEState *d = opaque;
362 int irq_mask;
363
364 irq_mask = MRDMODE_INTR_CH0 << channel;
365 if (level)
366 d->dev.config[MRDMODE] |= irq_mask;
367 else
368 d->dev.config[MRDMODE] &= ~irq_mask;
369 cmd646_update_irq(d);
370 }
371
372 static void cmd646_reset(void *opaque)
373 {
374 PCIIDEState *d = opaque;
375 unsigned int i;
376
377 for (i = 0; i < 2; i++)
378 ide_dma_cancel(&d->bmdma[i]);
379 }
380
381 /* CMD646 PCI IDE controller */
382 static int pci_cmd646_ide_initfn(PCIDevice *dev)
383 {
384 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
385 uint8_t *pci_conf = d->dev.config;
386 qemu_irq *irq;
387
388 d->type = IDE_TYPE_CMD646;
389 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
390 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
391
392 pci_conf[0x08] = 0x07; // IDE controller revision
393 pci_conf[0x09] = 0x8f;
394
395 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
396 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
397
398 pci_conf[0x51] = 0x04; // enable IDE0
399 if (d->secondary) {
400 /* XXX: if not enabled, really disable the seconday IDE controller */
401 pci_conf[0x51] |= 0x08; /* enable IDE1 */
402 }
403
404 pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
405 pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
406 pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
407 pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
408 pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);
409
410 pci_conf[0x3d] = 0x01; // interrupt on pin 1
411
412 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
413 ide_bus_new(&d->bus[0], &d->dev.qdev);
414 ide_bus_new(&d->bus[1], &d->dev.qdev);
415 ide_init2(&d->bus[0], NULL, NULL, irq[0]);
416 ide_init2(&d->bus[1], NULL, NULL, irq[1]);
417
418 register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
419 qemu_register_reset(cmd646_reset, d);
420 cmd646_reset(d);
421 return 0;
422 }
423
424 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
425 int secondary_ide_enabled)
426 {
427 PCIDevice *dev;
428
429 dev = pci_create(bus, -1, "CMD646 IDE");
430 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
431 qdev_init_nofail(&dev->qdev);
432
433 pci_ide_create_devs(dev, hd_table);
434 }
435
436 static void piix3_reset(void *opaque)
437 {
438 PCIIDEState *d = opaque;
439 uint8_t *pci_conf = d->dev.config;
440 int i;
441
442 for (i = 0; i < 2; i++)
443 ide_dma_cancel(&d->bmdma[i]);
444
445 pci_conf[0x04] = 0x00;
446 pci_conf[0x05] = 0x00;
447 pci_conf[0x06] = 0x80; /* FBC */
448 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
449 pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
450 }
451
452 static int pci_piix_ide_initfn(PCIIDEState *d)
453 {
454 uint8_t *pci_conf = d->dev.config;
455
456 pci_conf[0x09] = 0x80; // legacy ATA mode
457 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
458 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
459
460 qemu_register_reset(piix3_reset, d);
461 piix3_reset(d);
462
463 pci_register_bar(&d->dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);
464
465 register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
466
467 ide_bus_new(&d->bus[0], &d->dev.qdev);
468 ide_bus_new(&d->bus[1], &d->dev.qdev);
469 ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
470 ide_init_ioport(&d->bus[1], 0x170, 0x376);
471
472 ide_init2(&d->bus[0], NULL, NULL, isa_reserve_irq(14));
473 ide_init2(&d->bus[1], NULL, NULL, isa_reserve_irq(15));
474 return 0;
475 }
476
477 static int pci_piix3_ide_initfn(PCIDevice *dev)
478 {
479 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
480
481 d->type = IDE_TYPE_PIIX3;
482 pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
483 pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1);
484 return pci_piix_ide_initfn(d);
485 }
486
487 static int pci_piix4_ide_initfn(PCIDevice *dev)
488 {
489 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
490
491 d->type = IDE_TYPE_PIIX4;
492 pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
493 pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB);
494 return pci_piix_ide_initfn(d);
495 }
496
497 /* hd_table must contain 4 block drivers */
498 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
499 void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
500 {
501 PCIDevice *dev;
502
503 dev = pci_create_simple(bus, devfn, "PIIX3 IDE");
504 pci_ide_create_devs(dev, hd_table);
505 }
506
507 /* hd_table must contain 4 block drivers */
508 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
509 void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
510 {
511 PCIDevice *dev;
512
513 dev = pci_create_simple(bus, devfn, "PIIX4 IDE");
514 pci_ide_create_devs(dev, hd_table);
515 }
516
517 static PCIDeviceInfo piix_ide_info[] = {
518 {
519 .qdev.name = "PIIX3 IDE",
520 .qdev.size = sizeof(PCIIDEState),
521 .init = pci_piix3_ide_initfn,
522 },{
523 .qdev.name = "PIIX4 IDE",
524 .qdev.size = sizeof(PCIIDEState),
525 .init = pci_piix4_ide_initfn,
526 },{
527 .qdev.name = "CMD646 IDE",
528 .qdev.size = sizeof(PCIIDEState),
529 .init = pci_cmd646_ide_initfn,
530 .qdev.props = (Property[]) {
531 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
532 DEFINE_PROP_END_OF_LIST(),
533 },
534 },{
535 /* end of list */
536 }
537 };
538
539 static void piix_ide_register(void)
540 {
541 pci_qdev_register_many(piix_ide_info);
542 }
543 device_init(piix_ide_register);
Qemu copy for testing