2 * QEMU IDE Emulation: PCI PIIX3/4 support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "block_int.h"
34 #include <hw/ide/pci.h>
36 static uint64_t bmdma_read(void *opaque
, target_phys_addr_t addr
, unsigned size
)
38 BMDMAState
*bm
= opaque
;
42 return ((uint64_t)1 << (size
* 8)) - 1;
57 printf("bmdma: readb 0x%02x : 0x%02x\n", addr
, val
);
62 static void bmdma_write(void *opaque
, target_phys_addr_t addr
,
63 uint64_t val
, unsigned size
)
65 BMDMAState
*bm
= opaque
;
72 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr
, val
);
76 return bmdma_cmd_writeb(bm
, val
);
78 bm
->status
= (val
& 0x60) | (bm
->status
& 1) | (bm
->status
& ~val
& 0x06);
83 static MemoryRegionOps piix_bmdma_ops
= {
88 static void bmdma_setup_bar(PCIIDEState
*d
)
92 memory_region_init(&d
->bmdma_bar
, "piix-bmdma-container", 16);
93 for(i
= 0;i
< 2; i
++) {
94 BMDMAState
*bm
= &d
->bmdma
[i
];
96 memory_region_init_io(&bm
->extra_io
, &piix_bmdma_ops
, bm
,
98 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8, &bm
->extra_io
);
99 memory_region_init_io(&bm
->addr_ioport
, &bmdma_addr_ioport_ops
, bm
,
101 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8 + 4, &bm
->addr_ioport
);
105 static void piix3_reset(void *opaque
)
107 PCIIDEState
*d
= opaque
;
108 uint8_t *pci_conf
= d
->dev
.config
;
111 for (i
= 0; i
< 2; i
++) {
112 ide_bus_reset(&d
->bus
[i
]);
115 /* TODO: this is the default. do not override. */
116 pci_conf
[PCI_COMMAND
] = 0x00;
117 /* TODO: this is the default. do not override. */
118 pci_conf
[PCI_COMMAND
+ 1] = 0x00;
119 /* TODO: use pci_set_word */
120 pci_conf
[PCI_STATUS
] = PCI_STATUS_FAST_BACK
;
121 pci_conf
[PCI_STATUS
+ 1] = PCI_STATUS_DEVSEL_MEDIUM
>> 8;
122 pci_conf
[0x20] = 0x01; /* BMIBA: 20-23h */
125 static void pci_piix_init_ports(PCIIDEState
*d
) {
136 for (i
= 0; i
< 2; i
++) {
137 ide_bus_new(&d
->bus
[i
], &d
->dev
.qdev
, i
);
138 ide_init_ioport(&d
->bus
[i
], port_info
[i
].iobase
, port_info
[i
].iobase2
);
139 ide_init2(&d
->bus
[i
], isa_get_irq(port_info
[i
].isairq
));
141 bmdma_init(&d
->bus
[i
], &d
->bmdma
[i
], d
);
142 d
->bmdma
[i
].bus
= &d
->bus
[i
];
143 qemu_add_vm_change_state_handler(d
->bus
[i
].dma
->ops
->restart_cb
,
148 static int pci_piix_ide_initfn(PCIDevice
*dev
)
150 PCIIDEState
*d
= DO_UPCAST(PCIIDEState
, dev
, dev
);
151 uint8_t *pci_conf
= d
->dev
.config
;
153 pci_conf
[PCI_CLASS_PROG
] = 0x80; // legacy ATA mode
155 qemu_register_reset(piix3_reset
, d
);
158 pci_register_bar_region(&d
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
,
161 vmstate_register(&d
->dev
.qdev
, 0, &vmstate_ide_pci
, d
);
163 pci_piix_init_ports(d
);
168 static int pci_piix3_xen_ide_unplug(DeviceState
*dev
)
171 PCIIDEState
*pci_ide
;
175 pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
176 pci_ide
= DO_UPCAST(PCIIDEState
, dev
, pci_dev
);
179 di
= drive_get_by_index(IF_IDE
, i
);
180 if (di
!= NULL
&& di
->bdrv
!= NULL
&& !di
->bdrv
->removable
) {
181 DeviceState
*ds
= bdrv_get_attached(di
->bdrv
);
183 bdrv_detach(di
->bdrv
, ds
);
185 bdrv_close(di
->bdrv
);
186 pci_ide
->bus
[di
->bus
].ifs
[di
->unit
].bs
= NULL
;
190 qdev_reset_all(&(pci_ide
->dev
.qdev
));
194 PCIDevice
*pci_piix3_xen_ide_init(PCIBus
*bus
, DriveInfo
**hd_table
, int devfn
)
198 dev
= pci_create_simple(bus
, devfn
, "piix3-ide-xen");
199 dev
->qdev
.info
->unplug
= pci_piix3_xen_ide_unplug
;
200 pci_ide_create_devs(dev
, hd_table
);
204 static int pci_piix_ide_exitfn(PCIDevice
*dev
)
206 PCIIDEState
*d
= DO_UPCAST(PCIIDEState
, dev
, dev
);
209 for (i
= 0; i
< 2; ++i
) {
210 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].extra_io
);
211 memory_region_destroy(&d
->bmdma
[i
].extra_io
);
212 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].addr_ioport
);
213 memory_region_destroy(&d
->bmdma
[i
].addr_ioport
);
215 memory_region_destroy(&d
->bmdma_bar
);
220 /* hd_table must contain 4 block drivers */
221 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
222 PCIDevice
*pci_piix3_ide_init(PCIBus
*bus
, DriveInfo
**hd_table
, int devfn
)
226 dev
= pci_create_simple(bus
, devfn
, "piix3-ide");
227 pci_ide_create_devs(dev
, hd_table
);
231 /* hd_table must contain 4 block drivers */
232 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
233 PCIDevice
*pci_piix4_ide_init(PCIBus
*bus
, DriveInfo
**hd_table
, int devfn
)
237 dev
= pci_create_simple(bus
, devfn
, "piix4-ide");
238 pci_ide_create_devs(dev
, hd_table
);
242 static PCIDeviceInfo piix_ide_info
[] = {
244 .qdev
.name
= "piix3-ide",
245 .qdev
.size
= sizeof(PCIIDEState
),
248 .init
= pci_piix_ide_initfn
,
249 .exit
= pci_piix_ide_exitfn
,
250 .vendor_id
= PCI_VENDOR_ID_INTEL
,
251 .device_id
= PCI_DEVICE_ID_INTEL_82371SB_1
,
252 .class_id
= PCI_CLASS_STORAGE_IDE
,
254 .qdev
.name
= "piix3-ide-xen",
255 .qdev
.size
= sizeof(PCIIDEState
),
257 .init
= pci_piix_ide_initfn
,
258 .vendor_id
= PCI_VENDOR_ID_INTEL
,
259 .device_id
= PCI_DEVICE_ID_INTEL_82371SB_1
,
260 .class_id
= PCI_CLASS_STORAGE_IDE
,
262 .qdev
.name
= "piix4-ide",
263 .qdev
.size
= sizeof(PCIIDEState
),
266 .init
= pci_piix_ide_initfn
,
267 .exit
= pci_piix_ide_exitfn
,
268 .vendor_id
= PCI_VENDOR_ID_INTEL
,
269 .device_id
= PCI_DEVICE_ID_INTEL_82371AB
,
270 .class_id
= PCI_CLASS_STORAGE_IDE
,
276 static void piix_ide_register(void)
278 pci_qdev_register_many(piix_ide_info
);
280 device_init(piix_ide_register
);