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Spelling fixes, by Stefan Weil.
[qemu.git] / hw / ide.c
1 /*
2 * QEMU IDE disk and CD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "vl.h"
26
27 /* debug IDE devices */
28 //#define DEBUG_IDE
29 //#define DEBUG_IDE_ATAPI
30 //#define DEBUG_AIO
31 #define USE_DMA_CDROM
32
33 /* Bits of HD_STATUS */
34 #define ERR_STAT 0x01
35 #define INDEX_STAT 0x02
36 #define ECC_STAT 0x04 /* Corrected error */
37 #define DRQ_STAT 0x08
38 #define SEEK_STAT 0x10
39 #define SRV_STAT 0x10
40 #define WRERR_STAT 0x20
41 #define READY_STAT 0x40
42 #define BUSY_STAT 0x80
43
44 /* Bits for HD_ERROR */
45 #define MARK_ERR 0x01 /* Bad address mark */
46 #define TRK0_ERR 0x02 /* couldn't find track 0 */
47 #define ABRT_ERR 0x04 /* Command aborted */
48 #define MCR_ERR 0x08 /* media change request */
49 #define ID_ERR 0x10 /* ID field not found */
50 #define MC_ERR 0x20 /* media changed */
51 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
52 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
53 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
54
55 /* Bits of HD_NSECTOR */
56 #define CD 0x01
57 #define IO 0x02
58 #define REL 0x04
59 #define TAG_MASK 0xf8
60
61 #define IDE_CMD_RESET 0x04
62 #define IDE_CMD_DISABLE_IRQ 0x02
63
64 /* ATA/ATAPI Commands pre T13 Spec */
65 #define WIN_NOP 0x00
66 /*
67 * 0x01->0x02 Reserved
68 */
69 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
70 /*
71 * 0x04->0x07 Reserved
72 */
73 #define WIN_SRST 0x08 /* ATAPI soft reset command */
74 #define WIN_DEVICE_RESET 0x08
75 /*
76 * 0x09->0x0F Reserved
77 */
78 #define WIN_RECAL 0x10
79 #define WIN_RESTORE WIN_RECAL
80 /*
81 * 0x10->0x1F Reserved
82 */
83 #define WIN_READ 0x20 /* 28-Bit */
84 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
85 #define WIN_READ_LONG 0x22 /* 28-Bit */
86 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
87 #define WIN_READ_EXT 0x24 /* 48-Bit */
88 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
89 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
90 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
91 /*
92 * 0x28
93 */
94 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
95 /*
96 * 0x2A->0x2F Reserved
97 */
98 #define WIN_WRITE 0x30 /* 28-Bit */
99 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
100 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
101 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
102 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
103 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
104 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
105 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
106 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
107 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
108 /*
109 * 0x3A->0x3B Reserved
110 */
111 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
112 /*
113 * 0x3D->0x3F Reserved
114 */
115 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
116 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
117 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
118 /*
119 * 0x43->0x4F Reserved
120 */
121 #define WIN_FORMAT 0x50
122 /*
123 * 0x51->0x5F Reserved
124 */
125 #define WIN_INIT 0x60
126 /*
127 * 0x61->0x5F Reserved
128 */
129 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
130 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
131 #define WIN_DIAGNOSE 0x90
132 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
133 #define WIN_DOWNLOAD_MICROCODE 0x92
134 #define WIN_STANDBYNOW2 0x94
135 #define CFA_IDLEIMMEDIATE 0x95 /* force drive to become "ready" */
136 #define WIN_STANDBY2 0x96
137 #define WIN_SETIDLE2 0x97
138 #define WIN_CHECKPOWERMODE2 0x98
139 #define WIN_SLEEPNOW2 0x99
140 /*
141 * 0x9A VENDOR
142 */
143 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
144 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
145 #define WIN_QUEUED_SERVICE 0xA2
146 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
147 #define CFA_ACCESS_METADATA_STORAGE 0xB8
148 #define CFA_ERASE_SECTORS 0xC0 /* microdrives implement as NOP */
149 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
150 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
151 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
152 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
153 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
154 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
155 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
156 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
157 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
158 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
159 #define WIN_GETMEDIASTATUS 0xDA
160 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
161 #define WIN_POSTBOOT 0xDC
162 #define WIN_PREBOOT 0xDD
163 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
164 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
165 #define WIN_STANDBYNOW1 0xE0
166 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
167 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
168 #define WIN_SETIDLE1 0xE3
169 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
170 #define WIN_CHECKPOWERMODE1 0xE5
171 #define WIN_SLEEPNOW1 0xE6
172 #define WIN_FLUSH_CACHE 0xE7
173 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
174 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
175 /* SET_FEATURES 0x22 or 0xDD */
176 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
177 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
178 #define WIN_MEDIAEJECT 0xED
179 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
180 #define WIN_SETFEATURES 0xEF /* set special drive features */
181 #define EXABYTE_ENABLE_NEST 0xF0
182 #define IBM_SENSE_CONDITION 0xF0 /* measure disk temperature */
183 #define WIN_SECURITY_SET_PASS 0xF1
184 #define WIN_SECURITY_UNLOCK 0xF2
185 #define WIN_SECURITY_ERASE_PREPARE 0xF3
186 #define WIN_SECURITY_ERASE_UNIT 0xF4
187 #define WIN_SECURITY_FREEZE_LOCK 0xF5
188 #define CFA_WEAR_LEVEL 0xF5 /* microdrives implement as NOP */
189 #define WIN_SECURITY_DISABLE 0xF6
190 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
191 #define WIN_SET_MAX 0xF9
192 #define DISABLE_SEAGATE 0xFB
193
194 /* set to 1 set disable mult support */
195 #define MAX_MULT_SECTORS 16
196
197 /* ATAPI defines */
198
199 #define ATAPI_PACKET_SIZE 12
200
201 /* The generic packet command opcodes for CD/DVD Logical Units,
202 * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
203 #define GPCMD_BLANK 0xa1
204 #define GPCMD_CLOSE_TRACK 0x5b
205 #define GPCMD_FLUSH_CACHE 0x35
206 #define GPCMD_FORMAT_UNIT 0x04
207 #define GPCMD_GET_CONFIGURATION 0x46
208 #define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
209 #define GPCMD_GET_PERFORMANCE 0xac
210 #define GPCMD_INQUIRY 0x12
211 #define GPCMD_LOAD_UNLOAD 0xa6
212 #define GPCMD_MECHANISM_STATUS 0xbd
213 #define GPCMD_MODE_SELECT_10 0x55
214 #define GPCMD_MODE_SENSE_10 0x5a
215 #define GPCMD_PAUSE_RESUME 0x4b
216 #define GPCMD_PLAY_AUDIO_10 0x45
217 #define GPCMD_PLAY_AUDIO_MSF 0x47
218 #define GPCMD_PLAY_AUDIO_TI 0x48
219 #define GPCMD_PLAY_CD 0xbc
220 #define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e
221 #define GPCMD_READ_10 0x28
222 #define GPCMD_READ_12 0xa8
223 #define GPCMD_READ_CDVD_CAPACITY 0x25
224 #define GPCMD_READ_CD 0xbe
225 #define GPCMD_READ_CD_MSF 0xb9
226 #define GPCMD_READ_DISC_INFO 0x51
227 #define GPCMD_READ_DVD_STRUCTURE 0xad
228 #define GPCMD_READ_FORMAT_CAPACITIES 0x23
229 #define GPCMD_READ_HEADER 0x44
230 #define GPCMD_READ_TRACK_RZONE_INFO 0x52
231 #define GPCMD_READ_SUBCHANNEL 0x42
232 #define GPCMD_READ_TOC_PMA_ATIP 0x43
233 #define GPCMD_REPAIR_RZONE_TRACK 0x58
234 #define GPCMD_REPORT_KEY 0xa4
235 #define GPCMD_REQUEST_SENSE 0x03
236 #define GPCMD_RESERVE_RZONE_TRACK 0x53
237 #define GPCMD_SCAN 0xba
238 #define GPCMD_SEEK 0x2b
239 #define GPCMD_SEND_DVD_STRUCTURE 0xad
240 #define GPCMD_SEND_EVENT 0xa2
241 #define GPCMD_SEND_KEY 0xa3
242 #define GPCMD_SEND_OPC 0x54
243 #define GPCMD_SET_READ_AHEAD 0xa7
244 #define GPCMD_SET_STREAMING 0xb6
245 #define GPCMD_START_STOP_UNIT 0x1b
246 #define GPCMD_STOP_PLAY_SCAN 0x4e
247 #define GPCMD_TEST_UNIT_READY 0x00
248 #define GPCMD_VERIFY_10 0x2f
249 #define GPCMD_WRITE_10 0x2a
250 #define GPCMD_WRITE_AND_VERIFY_10 0x2e
251 /* This is listed as optional in ATAPI 2.6, but is (curiously)
252 * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
253 * Table 377 as an MMC command for SCSi devices though... Most ATAPI
254 * drives support it. */
255 #define GPCMD_SET_SPEED 0xbb
256 /* This seems to be a SCSI specific CD-ROM opcode
257 * to play data at track/index */
258 #define GPCMD_PLAYAUDIO_TI 0x48
259 /*
260 * From MS Media Status Notification Support Specification. For
261 * older drives only.
262 */
263 #define GPCMD_GET_MEDIA_STATUS 0xda
264
265 /* Mode page codes for mode sense/set */
266 #define GPMODE_R_W_ERROR_PAGE 0x01
267 #define GPMODE_WRITE_PARMS_PAGE 0x05
268 #define GPMODE_AUDIO_CTL_PAGE 0x0e
269 #define GPMODE_POWER_PAGE 0x1a
270 #define GPMODE_FAULT_FAIL_PAGE 0x1c
271 #define GPMODE_TO_PROTECT_PAGE 0x1d
272 #define GPMODE_CAPABILITIES_PAGE 0x2a
273 #define GPMODE_ALL_PAGES 0x3f
274 /* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
275 * of MODE_SENSE_POWER_PAGE */
276 #define GPMODE_CDROM_PAGE 0x0d
277
278 #define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */
279 #define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */
280 #define ATAPI_INT_REASON_REL 0x04
281 #define ATAPI_INT_REASON_TAG 0xf8
282
283 /* same constants as bochs */
284 #define ASC_ILLEGAL_OPCODE 0x20
285 #define ASC_LOGICAL_BLOCK_OOR 0x21
286 #define ASC_INV_FIELD_IN_CMD_PACKET 0x24
287 #define ASC_MEDIUM_NOT_PRESENT 0x3a
288 #define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
289
290 #define CFA_NO_ERROR 0x00
291 #define CFA_MISC_ERROR 0x09
292 #define CFA_INVALID_COMMAND 0x20
293 #define CFA_INVALID_ADDRESS 0x21
294 #define CFA_ADDRESS_OVERFLOW 0x2f
295
296 #define SENSE_NONE 0
297 #define SENSE_NOT_READY 2
298 #define SENSE_ILLEGAL_REQUEST 5
299 #define SENSE_UNIT_ATTENTION 6
300
301 struct IDEState;
302
303 typedef void EndTransferFunc(struct IDEState *);
304
305 /* NOTE: IDEState represents in fact one drive */
306 typedef struct IDEState {
307 /* ide config */
308 int is_cdrom;
309 int is_cf;
310 int cylinders, heads, sectors;
311 int64_t nb_sectors;
312 int mult_sectors;
313 int identify_set;
314 uint16_t identify_data[256];
315 qemu_irq irq;
316 PCIDevice *pci_dev;
317 struct BMDMAState *bmdma;
318 int drive_serial;
319 /* ide regs */
320 uint8_t feature;
321 uint8_t error;
322 uint32_t nsector;
323 uint8_t sector;
324 uint8_t lcyl;
325 uint8_t hcyl;
326 /* other part of tf for lba48 support */
327 uint8_t hob_feature;
328 uint8_t hob_nsector;
329 uint8_t hob_sector;
330 uint8_t hob_lcyl;
331 uint8_t hob_hcyl;
332
333 uint8_t select;
334 uint8_t status;
335
336 /* 0x3f6 command, only meaningful for drive 0 */
337 uint8_t cmd;
338 /* set for lba48 access */
339 uint8_t lba48;
340 /* depends on bit 4 in select, only meaningful for drive 0 */
341 struct IDEState *cur_drive;
342 BlockDriverState *bs;
343 /* ATAPI specific */
344 uint8_t sense_key;
345 uint8_t asc;
346 int packet_transfer_size;
347 int elementary_transfer_size;
348 int io_buffer_index;
349 int lba;
350 int cd_sector_size;
351 int atapi_dma; /* true if dma is requested for the packet cmd */
352 /* ATA DMA state */
353 int io_buffer_size;
354 /* PIO transfer handling */
355 int req_nb_sectors; /* number of sectors per interrupt */
356 EndTransferFunc *end_transfer_func;
357 uint8_t *data_ptr;
358 uint8_t *data_end;
359 uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
360 QEMUTimer *sector_write_timer; /* only used for win2k instal hack */
361 uint32_t irq_count; /* counts IRQs when using win2k install hack */
362 /* CF-ATA extended error */
363 uint8_t ext_error;
364 /* CF-ATA metadata storage */
365 uint32_t mdata_size;
366 uint8_t *mdata_storage;
367 int media_changed;
368 } IDEState;
369
370 #define BM_STATUS_DMAING 0x01
371 #define BM_STATUS_ERROR 0x02
372 #define BM_STATUS_INT 0x04
373
374 #define BM_CMD_START 0x01
375 #define BM_CMD_READ 0x08
376
377 #define IDE_TYPE_PIIX3 0
378 #define IDE_TYPE_CMD646 1
379 #define IDE_TYPE_PIIX4 2
380
381 /* CMD646 specific */
382 #define MRDMODE 0x71
383 #define MRDMODE_INTR_CH0 0x04
384 #define MRDMODE_INTR_CH1 0x08
385 #define MRDMODE_BLK_CH0 0x10
386 #define MRDMODE_BLK_CH1 0x20
387 #define UDIDETCR0 0x73
388 #define UDIDETCR1 0x7B
389
390 typedef struct BMDMAState {
391 uint8_t cmd;
392 uint8_t status;
393 uint32_t addr;
394
395 struct PCIIDEState *pci_dev;
396 /* current transfer state */
397 uint32_t cur_addr;
398 uint32_t cur_prd_last;
399 uint32_t cur_prd_addr;
400 uint32_t cur_prd_len;
401 IDEState *ide_if;
402 BlockDriverCompletionFunc *dma_cb;
403 BlockDriverAIOCB *aiocb;
404 } BMDMAState;
405
406 typedef struct PCIIDEState {
407 PCIDevice dev;
408 IDEState ide_if[4];
409 BMDMAState bmdma[2];
410 int type; /* see IDE_TYPE_xxx */
411 } PCIIDEState;
412
413 static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
414 static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);
415
416 static void padstr(char *str, const char *src, int len)
417 {
418 int i, v;
419 for(i = 0; i < len; i++) {
420 if (*src)
421 v = *src++;
422 else
423 v = ' ';
424 *(char *)((long)str ^ 1) = v;
425 str++;
426 }
427 }
428
429 static void padstr8(uint8_t *buf, int buf_size, const char *src)
430 {
431 int i;
432 for(i = 0; i < buf_size; i++) {
433 if (*src)
434 buf[i] = *src++;
435 else
436 buf[i] = ' ';
437 }
438 }
439
440 static void put_le16(uint16_t *p, unsigned int v)
441 {
442 *p = cpu_to_le16(v);
443 }
444
445 static void ide_identify(IDEState *s)
446 {
447 uint16_t *p;
448 unsigned int oldsize;
449 char buf[20];
450
451 if (s->identify_set) {
452 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
453 return;
454 }
455
456 memset(s->io_buffer, 0, 512);
457 p = (uint16_t *)s->io_buffer;
458 put_le16(p + 0, 0x0040);
459 put_le16(p + 1, s->cylinders);
460 put_le16(p + 3, s->heads);
461 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
462 put_le16(p + 5, 512); /* XXX: retired, remove ? */
463 put_le16(p + 6, s->sectors);
464 snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
465 padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
466 put_le16(p + 20, 3); /* XXX: retired, remove ? */
467 put_le16(p + 21, 512); /* cache size in sectors */
468 put_le16(p + 22, 4); /* ecc bytes */
469 padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
470 padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); /* model */
471 #if MAX_MULT_SECTORS > 1
472 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
473 #endif
474 put_le16(p + 48, 1); /* dword I/O */
475 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
476 put_le16(p + 51, 0x200); /* PIO transfer cycle */
477 put_le16(p + 52, 0x200); /* DMA transfer cycle */
478 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
479 put_le16(p + 54, s->cylinders);
480 put_le16(p + 55, s->heads);
481 put_le16(p + 56, s->sectors);
482 oldsize = s->cylinders * s->heads * s->sectors;
483 put_le16(p + 57, oldsize);
484 put_le16(p + 58, oldsize >> 16);
485 if (s->mult_sectors)
486 put_le16(p + 59, 0x100 | s->mult_sectors);
487 put_le16(p + 60, s->nb_sectors);
488 put_le16(p + 61, s->nb_sectors >> 16);
489 put_le16(p + 63, 0x07); /* mdma0-2 supported */
490 put_le16(p + 65, 120);
491 put_le16(p + 66, 120);
492 put_le16(p + 67, 120);
493 put_le16(p + 68, 120);
494 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
495 put_le16(p + 81, 0x16); /* conforms to ata5 */
496 put_le16(p + 82, (1 << 14));
497 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
498 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
499 put_le16(p + 84, (1 << 14));
500 put_le16(p + 85, (1 << 14));
501 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
502 put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
503 put_le16(p + 87, (1 << 14));
504 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
505 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
506 put_le16(p + 100, s->nb_sectors);
507 put_le16(p + 101, s->nb_sectors >> 16);
508 put_le16(p + 102, s->nb_sectors >> 32);
509 put_le16(p + 103, s->nb_sectors >> 48);
510
511 memcpy(s->identify_data, p, sizeof(s->identify_data));
512 s->identify_set = 1;
513 }
514
515 static void ide_atapi_identify(IDEState *s)
516 {
517 uint16_t *p;
518 char buf[20];
519
520 if (s->identify_set) {
521 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
522 return;
523 }
524
525 memset(s->io_buffer, 0, 512);
526 p = (uint16_t *)s->io_buffer;
527 /* Removable CDROM, 50us response, 12 byte packets */
528 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
529 snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
530 padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
531 put_le16(p + 20, 3); /* buffer type */
532 put_le16(p + 21, 512); /* cache size in sectors */
533 put_le16(p + 22, 4); /* ecc bytes */
534 padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
535 padstr((uint8_t *)(p + 27), "QEMU CD-ROM", 40); /* model */
536 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
537 #ifdef USE_DMA_CDROM
538 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
539 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
540 put_le16(p + 63, 7); /* mdma0-2 supported */
541 put_le16(p + 64, 0x3f); /* PIO modes supported */
542 #else
543 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
544 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
545 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
546 put_le16(p + 64, 1); /* PIO modes */
547 #endif
548 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
549 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
550 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
551 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
552
553 put_le16(p + 71, 30); /* in ns */
554 put_le16(p + 72, 30); /* in ns */
555
556 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
557 #ifdef USE_DMA_CDROM
558 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
559 #endif
560 memcpy(s->identify_data, p, sizeof(s->identify_data));
561 s->identify_set = 1;
562 }
563
564 static void ide_cfata_identify(IDEState *s)
565 {
566 uint16_t *p;
567 uint32_t cur_sec;
568 char buf[20];
569
570 p = (uint16_t *) s->identify_data;
571 if (s->identify_set)
572 goto fill_buffer;
573
574 memset(p, 0, sizeof(s->identify_data));
575
576 cur_sec = s->cylinders * s->heads * s->sectors;
577
578 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
579 put_le16(p + 1, s->cylinders); /* Default cylinders */
580 put_le16(p + 3, s->heads); /* Default heads */
581 put_le16(p + 6, s->sectors); /* Default sectors per track */
582 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
583 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
584 snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
585 padstr((uint8_t *)(p + 10), buf, 20); /* Serial number in ASCII */
586 put_le16(p + 22, 0x0004); /* ECC bytes */
587 padstr((uint8_t *) (p + 23), QEMU_VERSION, 8); /* Firmware Revision */
588 padstr((uint8_t *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
589 #if MAX_MULT_SECTORS > 1
590 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
591 #else
592 put_le16(p + 47, 0x0000);
593 #endif
594 put_le16(p + 49, 0x0f00); /* Capabilities */
595 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
596 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
597 put_le16(p + 53, 0x0003); /* Translation params valid */
598 put_le16(p + 54, s->cylinders); /* Current cylinders */
599 put_le16(p + 55, s->heads); /* Current heads */
600 put_le16(p + 56, s->sectors); /* Current sectors */
601 put_le16(p + 57, cur_sec); /* Current capacity */
602 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
603 if (s->mult_sectors) /* Multiple sector setting */
604 put_le16(p + 59, 0x100 | s->mult_sectors);
605 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
606 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
607 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
608 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
609 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
610 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
611 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
612 put_le16(p + 82, 0x400c); /* Command Set supported */
613 put_le16(p + 83, 0x7068); /* Command Set supported */
614 put_le16(p + 84, 0x4000); /* Features supported */
615 put_le16(p + 85, 0x000c); /* Command Set enabled */
616 put_le16(p + 86, 0x7044); /* Command Set enabled */
617 put_le16(p + 87, 0x4000); /* Features enabled */
618 put_le16(p + 91, 0x4060); /* Current APM level */
619 put_le16(p + 129, 0x0002); /* Current features option */
620 put_le16(p + 130, 0x0005); /* Reassigned sectors */
621 put_le16(p + 131, 0x0001); /* Initial power mode */
622 put_le16(p + 132, 0x0000); /* User signature */
623 put_le16(p + 160, 0x8100); /* Power requirement */
624 put_le16(p + 161, 0x8001); /* CF command set */
625
626 s->identify_set = 1;
627
628 fill_buffer:
629 memcpy(s->io_buffer, p, sizeof(s->identify_data));
630 }
631
632 static void ide_set_signature(IDEState *s)
633 {
634 s->select &= 0xf0; /* clear head */
635 /* put signature */
636 s->nsector = 1;
637 s->sector = 1;
638 if (s->is_cdrom) {
639 s->lcyl = 0x14;
640 s->hcyl = 0xeb;
641 } else if (s->bs) {
642 s->lcyl = 0;
643 s->hcyl = 0;
644 } else {
645 s->lcyl = 0xff;
646 s->hcyl = 0xff;
647 }
648 }
649
650 static inline void ide_abort_command(IDEState *s)
651 {
652 s->status = READY_STAT | ERR_STAT;
653 s->error = ABRT_ERR;
654 }
655
656 static inline void ide_set_irq(IDEState *s)
657 {
658 BMDMAState *bm = s->bmdma;
659 if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
660 if (bm) {
661 bm->status |= BM_STATUS_INT;
662 }
663 qemu_irq_raise(s->irq);
664 }
665 }
666
667 /* prepare data transfer and tell what to do after */
668 static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
669 EndTransferFunc *end_transfer_func)
670 {
671 s->end_transfer_func = end_transfer_func;
672 s->data_ptr = buf;
673 s->data_end = buf + size;
674 s->status |= DRQ_STAT;
675 }
676
677 static void ide_transfer_stop(IDEState *s)
678 {
679 s->end_transfer_func = ide_transfer_stop;
680 s->data_ptr = s->io_buffer;
681 s->data_end = s->io_buffer;
682 s->status &= ~DRQ_STAT;
683 }
684
685 static int64_t ide_get_sector(IDEState *s)
686 {
687 int64_t sector_num;
688 if (s->select & 0x40) {
689 /* lba */
690 if (!s->lba48) {
691 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
692 (s->lcyl << 8) | s->sector;
693 } else {
694 sector_num = ((int64_t)s->hob_hcyl << 40) |
695 ((int64_t) s->hob_lcyl << 32) |
696 ((int64_t) s->hob_sector << 24) |
697 ((int64_t) s->hcyl << 16) |
698 ((int64_t) s->lcyl << 8) | s->sector;
699 }
700 } else {
701 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
702 (s->select & 0x0f) * s->sectors + (s->sector - 1);
703 }
704 return sector_num;
705 }
706
707 static void ide_set_sector(IDEState *s, int64_t sector_num)
708 {
709 unsigned int cyl, r;
710 if (s->select & 0x40) {
711 if (!s->lba48) {
712 s->select = (s->select & 0xf0) | (sector_num >> 24);
713 s->hcyl = (sector_num >> 16);
714 s->lcyl = (sector_num >> 8);
715 s->sector = (sector_num);
716 } else {
717 s->sector = sector_num;
718 s->lcyl = sector_num >> 8;
719 s->hcyl = sector_num >> 16;
720 s->hob_sector = sector_num >> 24;
721 s->hob_lcyl = sector_num >> 32;
722 s->hob_hcyl = sector_num >> 40;
723 }
724 } else {
725 cyl = sector_num / (s->heads * s->sectors);
726 r = sector_num % (s->heads * s->sectors);
727 s->hcyl = cyl >> 8;
728 s->lcyl = cyl;
729 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
730 s->sector = (r % s->sectors) + 1;
731 }
732 }
733
734 static void ide_sector_read(IDEState *s)
735 {
736 int64_t sector_num;
737 int ret, n;
738
739 s->status = READY_STAT | SEEK_STAT;
740 s->error = 0; /* not needed by IDE spec, but needed by Windows */
741 sector_num = ide_get_sector(s);
742 n = s->nsector;
743 if (n == 0) {
744 /* no more sector to read from disk */
745 ide_transfer_stop(s);
746 } else {
747 #if defined(DEBUG_IDE)
748 printf("read sector=%Ld\n", sector_num);
749 #endif
750 if (n > s->req_nb_sectors)
751 n = s->req_nb_sectors;
752 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
753 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
754 ide_set_irq(s);
755 ide_set_sector(s, sector_num + n);
756 s->nsector -= n;
757 }
758 }
759
760 /* return 0 if buffer completed */
761 static int dma_buf_rw(BMDMAState *bm, int is_write)
762 {
763 IDEState *s = bm->ide_if;
764 struct {
765 uint32_t addr;
766 uint32_t size;
767 } prd;
768 int l, len;
769
770 for(;;) {
771 l = s->io_buffer_size - s->io_buffer_index;
772 if (l <= 0)
773 break;
774 if (bm->cur_prd_len == 0) {
775 /* end of table (with a fail safe of one page) */
776 if (bm->cur_prd_last ||
777 (bm->cur_addr - bm->addr) >= 4096)
778 return 0;
779 cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
780 bm->cur_addr += 8;
781 prd.addr = le32_to_cpu(prd.addr);
782 prd.size = le32_to_cpu(prd.size);
783 len = prd.size & 0xfffe;
784 if (len == 0)
785 len = 0x10000;
786 bm->cur_prd_len = len;
787 bm->cur_prd_addr = prd.addr;
788 bm->cur_prd_last = (prd.size & 0x80000000);
789 }
790 if (l > bm->cur_prd_len)
791 l = bm->cur_prd_len;
792 if (l > 0) {
793 if (is_write) {
794 cpu_physical_memory_write(bm->cur_prd_addr,
795 s->io_buffer + s->io_buffer_index, l);
796 } else {
797 cpu_physical_memory_read(bm->cur_prd_addr,
798 s->io_buffer + s->io_buffer_index, l);
799 }
800 bm->cur_prd_addr += l;
801 bm->cur_prd_len -= l;
802 s->io_buffer_index += l;
803 }
804 }
805 return 1;
806 }
807
808 /* XXX: handle errors */
809 static void ide_read_dma_cb(void *opaque, int ret)
810 {
811 BMDMAState *bm = opaque;
812 IDEState *s = bm->ide_if;
813 int n;
814 int64_t sector_num;
815
816 n = s->io_buffer_size >> 9;
817 sector_num = ide_get_sector(s);
818 if (n > 0) {
819 sector_num += n;
820 ide_set_sector(s, sector_num);
821 s->nsector -= n;
822 if (dma_buf_rw(bm, 1) == 0)
823 goto eot;
824 }
825
826 /* end of transfer ? */
827 if (s->nsector == 0) {
828 s->status = READY_STAT | SEEK_STAT;
829 ide_set_irq(s);
830 eot:
831 bm->status &= ~BM_STATUS_DMAING;
832 bm->status |= BM_STATUS_INT;
833 bm->dma_cb = NULL;
834 bm->ide_if = NULL;
835 bm->aiocb = NULL;
836 return;
837 }
838
839 /* launch next transfer */
840 n = s->nsector;
841 if (n > MAX_MULT_SECTORS)
842 n = MAX_MULT_SECTORS;
843 s->io_buffer_index = 0;
844 s->io_buffer_size = n * 512;
845 #ifdef DEBUG_AIO
846 printf("aio_read: sector_num=%lld n=%d\n", sector_num, n);
847 #endif
848 bm->aiocb = bdrv_aio_read(s->bs, sector_num, s->io_buffer, n,
849 ide_read_dma_cb, bm);
850 }
851
852 static void ide_sector_read_dma(IDEState *s)
853 {
854 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
855 s->io_buffer_index = 0;
856 s->io_buffer_size = 0;
857 ide_dma_start(s, ide_read_dma_cb);
858 }
859
860 static void ide_sector_write_timer_cb(void *opaque)
861 {
862 IDEState *s = opaque;
863 ide_set_irq(s);
864 }
865
866 static void ide_sector_write(IDEState *s)
867 {
868 int64_t sector_num;
869 int ret, n, n1;
870
871 s->status = READY_STAT | SEEK_STAT;
872 sector_num = ide_get_sector(s);
873 #if defined(DEBUG_IDE)
874 printf("write sector=%Ld\n", sector_num);
875 #endif
876 n = s->nsector;
877 if (n > s->req_nb_sectors)
878 n = s->req_nb_sectors;
879 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
880 s->nsector -= n;
881 if (s->nsector == 0) {
882 /* no more sectors to write */
883 ide_transfer_stop(s);
884 } else {
885 n1 = s->nsector;
886 if (n1 > s->req_nb_sectors)
887 n1 = s->req_nb_sectors;
888 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
889 }
890 ide_set_sector(s, sector_num + n);
891
892 #ifdef TARGET_I386
893 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
894 /* It seems there is a bug in the Windows 2000 installer HDD
895 IDE driver which fills the disk with empty logs when the
896 IDE write IRQ comes too early. This hack tries to correct
897 that at the expense of slower write performances. Use this
898 option _only_ to install Windows 2000. You must disable it
899 for normal use. */
900 qemu_mod_timer(s->sector_write_timer,
901 qemu_get_clock(vm_clock) + (ticks_per_sec / 1000));
902 } else
903 #endif
904 {
905 ide_set_irq(s);
906 }
907 }
908
909 /* XXX: handle errors */
910 static void ide_write_dma_cb(void *opaque, int ret)
911 {
912 BMDMAState *bm = opaque;
913 IDEState *s = bm->ide_if;
914 int n;
915 int64_t sector_num;
916
917 n = s->io_buffer_size >> 9;
918 sector_num = ide_get_sector(s);
919 if (n > 0) {
920 sector_num += n;
921 ide_set_sector(s, sector_num);
922 s->nsector -= n;
923 }
924
925 /* end of transfer ? */
926 if (s->nsector == 0) {
927 s->status = READY_STAT | SEEK_STAT;
928 ide_set_irq(s);
929 eot:
930 bm->status &= ~BM_STATUS_DMAING;
931 bm->status |= BM_STATUS_INT;
932 bm->dma_cb = NULL;
933 bm->ide_if = NULL;
934 bm->aiocb = NULL;
935 return;
936 }
937
938 /* launch next transfer */
939 n = s->nsector;
940 if (n > MAX_MULT_SECTORS)
941 n = MAX_MULT_SECTORS;
942 s->io_buffer_index = 0;
943 s->io_buffer_size = n * 512;
944
945 if (dma_buf_rw(bm, 0) == 0)
946 goto eot;
947 #ifdef DEBUG_AIO
948 printf("aio_write: sector_num=%lld n=%d\n", sector_num, n);
949 #endif
950 bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n,
951 ide_write_dma_cb, bm);
952 }
953
954 static void ide_sector_write_dma(IDEState *s)
955 {
956 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
957 s->io_buffer_index = 0;
958 s->io_buffer_size = 0;
959 ide_dma_start(s, ide_write_dma_cb);
960 }
961
962 static void ide_atapi_cmd_ok(IDEState *s)
963 {
964 s->error = 0;
965 s->status = READY_STAT;
966 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
967 ide_set_irq(s);
968 }
969
970 static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
971 {
972 #ifdef DEBUG_IDE_ATAPI
973 printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
974 #endif
975 s->error = sense_key << 4;
976 s->status = READY_STAT | ERR_STAT;
977 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
978 s->sense_key = sense_key;
979 s->asc = asc;
980 ide_set_irq(s);
981 }
982
983 static inline void cpu_to_ube16(uint8_t *buf, int val)
984 {
985 buf[0] = val >> 8;
986 buf[1] = val;
987 }
988
989 static inline void cpu_to_ube32(uint8_t *buf, unsigned int val)
990 {
991 buf[0] = val >> 24;
992 buf[1] = val >> 16;
993 buf[2] = val >> 8;
994 buf[3] = val;
995 }
996
997 static inline int ube16_to_cpu(const uint8_t *buf)
998 {
999 return (buf[0] << 8) | buf[1];
1000 }
1001
1002 static inline int ube32_to_cpu(const uint8_t *buf)
1003 {
1004 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
1005 }
1006
1007 static void lba_to_msf(uint8_t *buf, int lba)
1008 {
1009 lba += 150;
1010 buf[0] = (lba / 75) / 60;
1011 buf[1] = (lba / 75) % 60;
1012 buf[2] = lba % 75;
1013 }
1014
1015 static void cd_data_to_raw(uint8_t *buf, int lba)
1016 {
1017 /* sync bytes */
1018 buf[0] = 0x00;
1019 memset(buf + 1, 0xff, 10);
1020 buf[11] = 0x00;
1021 buf += 12;
1022 /* MSF */
1023 lba_to_msf(buf, lba);
1024 buf[3] = 0x01; /* mode 1 data */
1025 buf += 4;
1026 /* data */
1027 buf += 2048;
1028 /* XXX: ECC not computed */
1029 memset(buf, 0, 288);
1030 }
1031
1032 static int cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
1033 int sector_size)
1034 {
1035 int ret;
1036
1037 switch(sector_size) {
1038 case 2048:
1039 ret = bdrv_read(bs, (int64_t)lba << 2, buf, 4);
1040 break;
1041 case 2352:
1042 ret = bdrv_read(bs, (int64_t)lba << 2, buf + 16, 4);
1043 if (ret < 0)
1044 return ret;
1045 cd_data_to_raw(buf, lba);
1046 break;
1047 default:
1048 ret = -EIO;
1049 break;
1050 }
1051 return ret;
1052 }
1053
1054 static void ide_atapi_io_error(IDEState *s, int ret)
1055 {
1056 /* XXX: handle more errors */
1057 if (ret == -ENOMEDIUM) {
1058 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1059 ASC_MEDIUM_NOT_PRESENT);
1060 } else {
1061 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1062 ASC_LOGICAL_BLOCK_OOR);
1063 }
1064 }
1065
1066 /* The whole ATAPI transfer logic is handled in this function */
1067 static void ide_atapi_cmd_reply_end(IDEState *s)
1068 {
1069 int byte_count_limit, size, ret;
1070 #ifdef DEBUG_IDE_ATAPI
1071 printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
1072 s->packet_transfer_size,
1073 s->elementary_transfer_size,
1074 s->io_buffer_index);
1075 #endif
1076 if (s->packet_transfer_size <= 0) {
1077 /* end of transfer */
1078 ide_transfer_stop(s);
1079 s->status = READY_STAT;
1080 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1081 ide_set_irq(s);
1082 #ifdef DEBUG_IDE_ATAPI
1083 printf("status=0x%x\n", s->status);
1084 #endif
1085 } else {
1086 /* see if a new sector must be read */
1087 if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) {
1088 ret = cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
1089 if (ret < 0) {
1090 ide_transfer_stop(s);
1091 ide_atapi_io_error(s, ret);
1092 return;
1093 }
1094 s->lba++;
1095 s->io_buffer_index = 0;
1096 }
1097 if (s->elementary_transfer_size > 0) {
1098 /* there are some data left to transmit in this elementary
1099 transfer */
1100 size = s->cd_sector_size - s->io_buffer_index;
1101 if (size > s->elementary_transfer_size)
1102 size = s->elementary_transfer_size;
1103 ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
1104 size, ide_atapi_cmd_reply_end);
1105 s->packet_transfer_size -= size;
1106 s->elementary_transfer_size -= size;
1107 s->io_buffer_index += size;
1108 } else {
1109 /* a new transfer is needed */
1110 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
1111 byte_count_limit = s->lcyl | (s->hcyl << 8);
1112 #ifdef DEBUG_IDE_ATAPI
1113 printf("byte_count_limit=%d\n", byte_count_limit);
1114 #endif
1115 if (byte_count_limit == 0xffff)
1116 byte_count_limit--;
1117 size = s->packet_transfer_size;
1118 if (size > byte_count_limit) {
1119 /* byte count limit must be even if this case */
1120 if (byte_count_limit & 1)
1121 byte_count_limit--;
1122 size = byte_count_limit;
1123 }
1124 s->lcyl = size;
1125 s->hcyl = size >> 8;
1126 s->elementary_transfer_size = size;
1127 /* we cannot transmit more than one sector at a time */
1128 if (s->lba != -1) {
1129 if (size > (s->cd_sector_size - s->io_buffer_index))
1130 size = (s->cd_sector_size - s->io_buffer_index);
1131 }
1132 ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
1133 size, ide_atapi_cmd_reply_end);
1134 s->packet_transfer_size -= size;
1135 s->elementary_transfer_size -= size;
1136 s->io_buffer_index += size;
1137 ide_set_irq(s);
1138 #ifdef DEBUG_IDE_ATAPI
1139 printf("status=0x%x\n", s->status);
1140 #endif
1141 }
1142 }
1143 }
1144
1145 /* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
1146 static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size)
1147 {
1148 if (size > max_size)
1149 size = max_size;
1150 s->lba = -1; /* no sector read */
1151 s->packet_transfer_size = size;
1152 s->io_buffer_size = size; /* dma: send the reply data as one chunk */
1153 s->elementary_transfer_size = 0;
1154 s->io_buffer_index = 0;
1155
1156 if (s->atapi_dma) {
1157 s->status = READY_STAT | DRQ_STAT;
1158 ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
1159 } else {
1160 s->status = READY_STAT;
1161 ide_atapi_cmd_reply_end(s);
1162 }
1163 }
1164
1165 /* start a CD-CDROM read command */
1166 static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
1167 int sector_size)
1168 {
1169 s->lba = lba;
1170 s->packet_transfer_size = nb_sectors * sector_size;
1171 s->elementary_transfer_size = 0;
1172 s->io_buffer_index = sector_size;
1173 s->cd_sector_size = sector_size;
1174
1175 s->status = READY_STAT;
1176 ide_atapi_cmd_reply_end(s);
1177 }
1178
1179 /* ATAPI DMA support */
1180
1181 /* XXX: handle read errors */
1182 static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
1183 {
1184 BMDMAState *bm = opaque;
1185 IDEState *s = bm->ide_if;
1186 int data_offset, n;
1187
1188 if (ret < 0) {
1189 ide_atapi_io_error(s, ret);
1190 goto eot;
1191 }
1192
1193 if (s->io_buffer_size > 0) {
1194 /*
1195 * For a cdrom read sector command (s->lba != -1),
1196 * adjust the lba for the next s->io_buffer_size chunk
1197 * and dma the current chunk.
1198 * For a command != read (s->lba == -1), just transfer
1199 * the reply data.
1200 */
1201 if (s->lba != -1) {
1202 if (s->cd_sector_size == 2352) {
1203 n = 1;
1204 cd_data_to_raw(s->io_buffer, s->lba);
1205 } else {
1206 n = s->io_buffer_size >> 11;
1207 }
1208 s->lba += n;
1209 }
1210 s->packet_transfer_size -= s->io_buffer_size;
1211 if (dma_buf_rw(bm, 1) == 0)
1212 goto eot;
1213 }
1214
1215 if (s->packet_transfer_size <= 0) {
1216 s->status = READY_STAT;
1217 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1218 ide_set_irq(s);
1219 eot:
1220 bm->status &= ~BM_STATUS_DMAING;
1221 bm->status |= BM_STATUS_INT;
1222 bm->dma_cb = NULL;
1223 bm->ide_if = NULL;
1224 bm->aiocb = NULL;
1225 return;
1226 }
1227
1228 s->io_buffer_index = 0;
1229 if (s->cd_sector_size == 2352) {
1230 n = 1;
1231 s->io_buffer_size = s->cd_sector_size;
1232 data_offset = 16;
1233 } else {
1234 n = s->packet_transfer_size >> 11;
1235 if (n > (MAX_MULT_SECTORS / 4))
1236 n = (MAX_MULT_SECTORS / 4);
1237 s->io_buffer_size = n * 2048;
1238 data_offset = 0;
1239 }
1240 #ifdef DEBUG_AIO
1241 printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
1242 #endif
1243 bm->aiocb = bdrv_aio_read(s->bs, (int64_t)s->lba << 2,
1244 s->io_buffer + data_offset, n * 4,
1245 ide_atapi_cmd_read_dma_cb, bm);
1246 if (!bm->aiocb) {
1247 /* Note: media not present is the most likely case */
1248 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1249 ASC_MEDIUM_NOT_PRESENT);
1250 goto eot;
1251 }
1252 }
1253
1254 /* start a CD-CDROM read command with DMA */
1255 /* XXX: test if DMA is available */
1256 static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors,
1257 int sector_size)
1258 {
1259 s->lba = lba;
1260 s->packet_transfer_size = nb_sectors * sector_size;
1261 s->io_buffer_index = 0;
1262 s->io_buffer_size = 0;
1263 s->cd_sector_size = sector_size;
1264
1265 /* XXX: check if BUSY_STAT should be set */
1266 s->status = READY_STAT | DRQ_STAT | BUSY_STAT;
1267 ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
1268 }
1269
1270 static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors,
1271 int sector_size)
1272 {
1273 #ifdef DEBUG_IDE_ATAPI
1274 printf("read %s: LBA=%d nb_sectors=%d\n", s->atapi_dma ? "dma" : "pio",
1275 lba, nb_sectors);
1276 #endif
1277 if (s->atapi_dma) {
1278 ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size);
1279 } else {
1280 ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size);
1281 }
1282 }
1283
1284 static void ide_atapi_cmd(IDEState *s)
1285 {
1286 const uint8_t *packet;
1287 uint8_t *buf;
1288 int max_len;
1289
1290 packet = s->io_buffer;
1291 buf = s->io_buffer;
1292 #ifdef DEBUG_IDE_ATAPI
1293 {
1294 int i;
1295 printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8));
1296 for(i = 0; i < ATAPI_PACKET_SIZE; i++) {
1297 printf(" %02x", packet[i]);
1298 }
1299 printf("\n");
1300 }
1301 #endif
1302 switch(s->io_buffer[0]) {
1303 case GPCMD_TEST_UNIT_READY:
1304 if (bdrv_is_inserted(s->bs)) {
1305 ide_atapi_cmd_ok(s);
1306 } else {
1307 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1308 ASC_MEDIUM_NOT_PRESENT);
1309 }
1310 break;
1311 case GPCMD_MODE_SENSE_10:
1312 {
1313 int action, code;
1314 max_len = ube16_to_cpu(packet + 7);
1315 action = packet[2] >> 6;
1316 code = packet[2] & 0x3f;
1317 switch(action) {
1318 case 0: /* current values */
1319 switch(code) {
1320 case 0x01: /* error recovery */
1321 cpu_to_ube16(&buf[0], 16 + 6);
1322 buf[2] = 0x70;
1323 buf[3] = 0;
1324 buf[4] = 0;
1325 buf[5] = 0;
1326 buf[6] = 0;
1327 buf[7] = 0;
1328
1329 buf[8] = 0x01;
1330 buf[9] = 0x06;
1331 buf[10] = 0x00;
1332 buf[11] = 0x05;
1333 buf[12] = 0x00;
1334 buf[13] = 0x00;
1335 buf[14] = 0x00;
1336 buf[15] = 0x00;
1337 ide_atapi_cmd_reply(s, 16, max_len);
1338 break;
1339 case 0x2a:
1340 cpu_to_ube16(&buf[0], 28 + 6);
1341 buf[2] = 0x70;
1342 buf[3] = 0;
1343 buf[4] = 0;
1344 buf[5] = 0;
1345 buf[6] = 0;
1346 buf[7] = 0;
1347
1348 buf[8] = 0x2a;
1349 buf[9] = 0x12;
1350 buf[10] = 0x00;
1351 buf[11] = 0x00;
1352
1353 buf[12] = 0x70;
1354 buf[13] = 3 << 5;
1355 buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
1356 if (bdrv_is_locked(s->bs))
1357 buf[6] |= 1 << 1;
1358 buf[15] = 0x00;
1359 cpu_to_ube16(&buf[16], 706);
1360 buf[18] = 0;
1361 buf[19] = 2;
1362 cpu_to_ube16(&buf[20], 512);
1363 cpu_to_ube16(&buf[22], 706);
1364 buf[24] = 0;
1365 buf[25] = 0;
1366 buf[26] = 0;
1367 buf[27] = 0;
1368 ide_atapi_cmd_reply(s, 28, max_len);
1369 break;
1370 default:
1371 goto error_cmd;
1372 }
1373 break;
1374 case 1: /* changeable values */
1375 goto error_cmd;
1376 case 2: /* default values */
1377 goto error_cmd;
1378 default:
1379 case 3: /* saved values */
1380 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1381 ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
1382 break;
1383 }
1384 }
1385 break;
1386 case GPCMD_REQUEST_SENSE:
1387 max_len = packet[4];
1388 memset(buf, 0, 18);
1389 buf[0] = 0x70 | (1 << 7);
1390 buf[2] = s->sense_key;
1391 buf[7] = 10;
1392 buf[12] = s->asc;
1393 ide_atapi_cmd_reply(s, 18, max_len);
1394 break;
1395 case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
1396 if (bdrv_is_inserted(s->bs)) {
1397 bdrv_set_locked(s->bs, packet[4] & 1);
1398 ide_atapi_cmd_ok(s);
1399 } else {
1400 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1401 ASC_MEDIUM_NOT_PRESENT);
1402 }
1403 break;
1404 case GPCMD_READ_10:
1405 case GPCMD_READ_12:
1406 {
1407 int nb_sectors, lba;
1408
1409 if (packet[0] == GPCMD_READ_10)
1410 nb_sectors = ube16_to_cpu(packet + 7);
1411 else
1412 nb_sectors = ube32_to_cpu(packet + 6);
1413 lba = ube32_to_cpu(packet + 2);
1414 if (nb_sectors == 0) {
1415 ide_atapi_cmd_ok(s);
1416 break;
1417 }
1418 ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1419 }
1420 break;
1421 case GPCMD_READ_CD:
1422 {
1423 int nb_sectors, lba, transfer_request;
1424
1425 nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8];
1426 lba = ube32_to_cpu(packet + 2);
1427 if (nb_sectors == 0) {
1428 ide_atapi_cmd_ok(s);
1429 break;
1430 }
1431 transfer_request = packet[9];
1432 switch(transfer_request & 0xf8) {
1433 case 0x00:
1434 /* nothing */
1435 ide_atapi_cmd_ok(s);
1436 break;
1437 case 0x10:
1438 /* normal read */
1439 ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1440 break;
1441 case 0xf8:
1442 /* read all data */
1443 ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
1444 break;
1445 default:
1446 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1447 ASC_INV_FIELD_IN_CMD_PACKET);
1448 break;
1449 }
1450 }
1451 break;
1452 case GPCMD_SEEK:
1453 {
1454 int lba;
1455 int64_t total_sectors;
1456
1457 bdrv_get_geometry(s->bs, &total_sectors);
1458 total_sectors >>= 2;
1459 if (total_sectors <= 0) {
1460 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1461 ASC_MEDIUM_NOT_PRESENT);
1462 break;
1463 }
1464 lba = ube32_to_cpu(packet + 2);
1465 if (lba >= total_sectors) {
1466 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1467 ASC_LOGICAL_BLOCK_OOR);
1468 break;
1469 }
1470 ide_atapi_cmd_ok(s);
1471 }
1472 break;
1473 case GPCMD_START_STOP_UNIT:
1474 {
1475 int start, eject;
1476 start = packet[4] & 1;
1477 eject = (packet[4] >> 1) & 1;
1478
1479 if (eject && !start) {
1480 /* eject the disk */
1481 bdrv_eject(s->bs, 1);
1482 } else if (eject && start) {
1483 /* close the tray */
1484 bdrv_eject(s->bs, 0);
1485 }
1486 ide_atapi_cmd_ok(s);
1487 }
1488 break;
1489 case GPCMD_MECHANISM_STATUS:
1490 {
1491 max_len = ube16_to_cpu(packet + 8);
1492 cpu_to_ube16(buf, 0);
1493 /* no current LBA */
1494 buf[2] = 0;
1495 buf[3] = 0;
1496 buf[4] = 0;
1497 buf[5] = 1;
1498 cpu_to_ube16(buf + 6, 0);
1499 ide_atapi_cmd_reply(s, 8, max_len);
1500 }
1501 break;
1502 case GPCMD_READ_TOC_PMA_ATIP:
1503 {
1504 int format, msf, start_track, len;
1505 int64_t total_sectors;
1506
1507 bdrv_get_geometry(s->bs, &total_sectors);
1508 total_sectors >>= 2;
1509 if (total_sectors <= 0) {
1510 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1511 ASC_MEDIUM_NOT_PRESENT);
1512 break;
1513 }
1514 max_len = ube16_to_cpu(packet + 7);
1515 format = packet[9] >> 6;
1516 msf = (packet[1] >> 1) & 1;
1517 start_track = packet[6];
1518 switch(format) {
1519 case 0:
1520 len = cdrom_read_toc(total_sectors, buf, msf, start_track);
1521 if (len < 0)
1522 goto error_cmd;
1523 ide_atapi_cmd_reply(s, len, max_len);
1524 break;
1525 case 1:
1526 /* multi session : only a single session defined */
1527 memset(buf, 0, 12);
1528 buf[1] = 0x0a;
1529 buf[2] = 0x01;
1530 buf[3] = 0x01;
1531 ide_atapi_cmd_reply(s, 12, max_len);
1532 break;
1533 case 2:
1534 len = cdrom_read_toc_raw(total_sectors, buf, msf, start_track);
1535 if (len < 0)
1536 goto error_cmd;
1537 ide_atapi_cmd_reply(s, len, max_len);
1538 break;
1539 default:
1540 error_cmd:
1541 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1542 ASC_INV_FIELD_IN_CMD_PACKET);
1543 break;
1544 }
1545 }
1546 break;
1547 case GPCMD_READ_CDVD_CAPACITY:
1548 {
1549 int64_t total_sectors;
1550
1551 bdrv_get_geometry(s->bs, &total_sectors);
1552 total_sectors >>= 2;
1553 if (total_sectors <= 0) {
1554 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1555 ASC_MEDIUM_NOT_PRESENT);
1556 break;
1557 }
1558 /* NOTE: it is really the number of sectors minus 1 */
1559 cpu_to_ube32(buf, total_sectors - 1);
1560 cpu_to_ube32(buf + 4, 2048);
1561 ide_atapi_cmd_reply(s, 8, 8);
1562 }
1563 break;
1564 case GPCMD_INQUIRY:
1565 max_len = packet[4];
1566 buf[0] = 0x05; /* CD-ROM */
1567 buf[1] = 0x80; /* removable */
1568 buf[2] = 0x00; /* ISO */
1569 buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
1570 buf[4] = 31; /* additional length */
1571 buf[5] = 0; /* reserved */
1572 buf[6] = 0; /* reserved */
1573 buf[7] = 0; /* reserved */
1574 padstr8(buf + 8, 8, "QEMU");
1575 padstr8(buf + 16, 16, "QEMU CD-ROM");
1576 padstr8(buf + 32, 4, QEMU_VERSION);
1577 ide_atapi_cmd_reply(s, 36, max_len);
1578 break;
1579 default:
1580 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1581 ASC_ILLEGAL_OPCODE);
1582 break;
1583 }
1584 }
1585
1586 static void ide_cfata_metadata_inquiry(IDEState *s)
1587 {
1588 uint16_t *p;
1589 uint32_t spd;
1590
1591 p = (uint16_t *) s->io_buffer;
1592 memset(p, 0, 0x200);
1593 spd = ((s->mdata_size - 1) >> 9) + 1;
1594
1595 put_le16(p + 0, 0x0001); /* Data format revision */
1596 put_le16(p + 1, 0x0000); /* Media property: silicon */
1597 put_le16(p + 2, s->media_changed); /* Media status */
1598 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1599 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1600 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1601 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1602 }
1603
1604 static void ide_cfata_metadata_read(IDEState *s)
1605 {
1606 uint16_t *p;
1607
1608 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1609 s->status = ERR_STAT;
1610 s->error = ABRT_ERR;
1611 return;
1612 }
1613
1614 p = (uint16_t *) s->io_buffer;
1615 memset(p, 0, 0x200);
1616
1617 put_le16(p + 0, s->media_changed); /* Media status */
1618 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1619 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1620 s->nsector << 9), 0x200 - 2));
1621 }
1622
1623 static void ide_cfata_metadata_write(IDEState *s)
1624 {
1625 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1626 s->status = ERR_STAT;
1627 s->error = ABRT_ERR;
1628 return;
1629 }
1630
1631 s->media_changed = 0;
1632
1633 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1634 s->io_buffer + 2,
1635 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1636 s->nsector << 9), 0x200 - 2));
1637 }
1638
1639 /* called when the inserted state of the media has changed */
1640 static void cdrom_change_cb(void *opaque)
1641 {
1642 IDEState *s = opaque;
1643 int64_t nb_sectors;
1644
1645 /* XXX: send interrupt too */
1646 bdrv_get_geometry(s->bs, &nb_sectors);
1647 s->nb_sectors = nb_sectors;
1648 }
1649
1650 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1651 {
1652 s->lba48 = lba48;
1653
1654 /* handle the 'magic' 0 nsector count conversion here. to avoid
1655 * fiddling with the rest of the read logic, we just store the
1656 * full sector count in ->nsector and ignore ->hob_nsector from now
1657 */
1658 if (!s->lba48) {
1659 if (!s->nsector)
1660 s->nsector = 256;
1661 } else {
1662 if (!s->nsector && !s->hob_nsector)
1663 s->nsector = 65536;
1664 else {
1665 int lo = s->nsector;
1666 int hi = s->hob_nsector;
1667
1668 s->nsector = (hi << 8) | lo;
1669 }
1670 }
1671 }
1672
1673 static void ide_clear_hob(IDEState *ide_if)
1674 {
1675 /* any write clears HOB high bit of device control register */
1676 ide_if[0].select &= ~(1 << 7);
1677 ide_if[1].select &= ~(1 << 7);
1678 }
1679
1680 static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1681 {
1682 IDEState *ide_if = opaque;
1683 IDEState *s;
1684 int unit, n;
1685 int lba48 = 0;
1686
1687 #ifdef DEBUG_IDE
1688 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1689 #endif
1690
1691 addr &= 7;
1692 switch(addr) {
1693 case 0:
1694 break;
1695 case 1:
1696 ide_clear_hob(ide_if);
1697 /* NOTE: data is written to the two drives */
1698 ide_if[0].hob_feature = ide_if[0].feature;
1699 ide_if[1].hob_feature = ide_if[1].feature;
1700 ide_if[0].feature = val;
1701 ide_if[1].feature = val;
1702 break;
1703 case 2:
1704 ide_clear_hob(ide_if);
1705 ide_if[0].hob_nsector = ide_if[0].nsector;
1706 ide_if[1].hob_nsector = ide_if[1].nsector;
1707 ide_if[0].nsector = val;
1708 ide_if[1].nsector = val;
1709 break;
1710 case 3:
1711 ide_clear_hob(ide_if);
1712 ide_if[0].hob_sector = ide_if[0].sector;
1713 ide_if[1].hob_sector = ide_if[1].sector;
1714 ide_if[0].sector = val;
1715 ide_if[1].sector = val;
1716 break;
1717 case 4:
1718 ide_clear_hob(ide_if);
1719 ide_if[0].hob_lcyl = ide_if[0].lcyl;
1720 ide_if[1].hob_lcyl = ide_if[1].lcyl;
1721 ide_if[0].lcyl = val;
1722 ide_if[1].lcyl = val;
1723 break;
1724 case 5:
1725 ide_clear_hob(ide_if);
1726 ide_if[0].hob_hcyl = ide_if[0].hcyl;
1727 ide_if[1].hob_hcyl = ide_if[1].hcyl;
1728 ide_if[0].hcyl = val;
1729 ide_if[1].hcyl = val;
1730 break;
1731 case 6:
1732 /* FIXME: HOB readback uses bit 7 */
1733 ide_if[0].select = (val & ~0x10) | 0xa0;
1734 ide_if[1].select = (val | 0x10) | 0xa0;
1735 /* select drive */
1736 unit = (val >> 4) & 1;
1737 s = ide_if + unit;
1738 ide_if->cur_drive = s;
1739 break;
1740 default:
1741 case 7:
1742 /* command */
1743 #if defined(DEBUG_IDE)
1744 printf("ide: CMD=%02x\n", val);
1745 #endif
1746 s = ide_if->cur_drive;
1747 /* ignore commands to non existant slave */
1748 if (s != ide_if && !s->bs)
1749 break;
1750
1751 switch(val) {
1752 case WIN_IDENTIFY:
1753 if (s->bs && !s->is_cdrom) {
1754 if (!s->is_cf)
1755 ide_identify(s);
1756 else
1757 ide_cfata_identify(s);
1758 s->status = READY_STAT | SEEK_STAT;
1759 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1760 } else {
1761 if (s->is_cdrom) {
1762 ide_set_signature(s);
1763 }
1764 ide_abort_command(s);
1765 }
1766 ide_set_irq(s);
1767 break;
1768 case WIN_SPECIFY:
1769 case WIN_RECAL:
1770 s->error = 0;
1771 s->status = READY_STAT | SEEK_STAT;
1772 ide_set_irq(s);
1773 break;
1774 case WIN_SETMULT:
1775 if (s->is_cf && s->nsector == 0) {
1776 /* Disable Read and Write Multiple */
1777 s->mult_sectors = 0;
1778 s->status = READY_STAT;
1779 } else if ((s->nsector & 0xff) != 0 &&
1780 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1781 (s->nsector & (s->nsector - 1)) != 0)) {
1782 ide_abort_command(s);
1783 } else {
1784 s->mult_sectors = s->nsector & 0xff;
1785 s->status = READY_STAT;
1786 }
1787 ide_set_irq(s);
1788 break;
1789 case WIN_VERIFY_EXT:
1790 lba48 = 1;
1791 case WIN_VERIFY:
1792 case WIN_VERIFY_ONCE:
1793 /* do sector number check ? */
1794 ide_cmd_lba48_transform(s, lba48);
1795 s->status = READY_STAT;
1796 ide_set_irq(s);
1797 break;
1798 case WIN_READ_EXT:
1799 lba48 = 1;
1800 case WIN_READ:
1801 case WIN_READ_ONCE:
1802 if (!s->bs)
1803 goto abort_cmd;
1804 ide_cmd_lba48_transform(s, lba48);
1805 s->req_nb_sectors = 1;
1806 ide_sector_read(s);
1807 break;
1808 case WIN_WRITE_EXT:
1809 lba48 = 1;
1810 case WIN_WRITE:
1811 case WIN_WRITE_ONCE:
1812 case CFA_WRITE_SECT_WO_ERASE:
1813 case WIN_WRITE_VERIFY:
1814 ide_cmd_lba48_transform(s, lba48);
1815 s->error = 0;
1816 s->status = SEEK_STAT | READY_STAT;
1817 s->req_nb_sectors = 1;
1818 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1819 s->media_changed = 1;
1820 break;
1821 case WIN_MULTREAD_EXT:
1822 lba48 = 1;
1823 case WIN_MULTREAD:
1824 if (!s->mult_sectors)
1825 goto abort_cmd;
1826 ide_cmd_lba48_transform(s, lba48);
1827 s->req_nb_sectors = s->mult_sectors;
1828 ide_sector_read(s);
1829 break;
1830 case WIN_MULTWRITE_EXT:
1831 lba48 = 1;
1832 case WIN_MULTWRITE:
1833 case CFA_WRITE_MULTI_WO_ERASE:
1834 if (!s->mult_sectors)
1835 goto abort_cmd;
1836 ide_cmd_lba48_transform(s, lba48);
1837 s->error = 0;
1838 s->status = SEEK_STAT | READY_STAT;
1839 s->req_nb_sectors = s->mult_sectors;
1840 n = s->nsector;
1841 if (n > s->req_nb_sectors)
1842 n = s->req_nb_sectors;
1843 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1844 s->media_changed = 1;
1845 break;
1846 case WIN_READDMA_EXT:
1847 lba48 = 1;
1848 case WIN_READDMA:
1849 case WIN_READDMA_ONCE:
1850 if (!s->bs)
1851 goto abort_cmd;
1852 ide_cmd_lba48_transform(s, lba48);
1853 ide_sector_read_dma(s);
1854 break;
1855 case WIN_WRITEDMA_EXT:
1856 lba48 = 1;
1857 case WIN_WRITEDMA:
1858 case WIN_WRITEDMA_ONCE:
1859 if (!s->bs)
1860 goto abort_cmd;
1861 ide_cmd_lba48_transform(s, lba48);
1862 ide_sector_write_dma(s);
1863 s->media_changed = 1;
1864 break;
1865 case WIN_READ_NATIVE_MAX_EXT:
1866 lba48 = 1;
1867 case WIN_READ_NATIVE_MAX:
1868 ide_cmd_lba48_transform(s, lba48);
1869 ide_set_sector(s, s->nb_sectors - 1);
1870 s->status = READY_STAT;
1871 ide_set_irq(s);
1872 break;
1873 case WIN_CHECKPOWERMODE1:
1874 case WIN_CHECKPOWERMODE2:
1875 s->nsector = 0xff; /* device active or idle */
1876 s->status = READY_STAT;
1877 ide_set_irq(s);
1878 break;
1879 case WIN_SETFEATURES:
1880 if (!s->bs)
1881 goto abort_cmd;
1882 /* XXX: valid for CDROM ? */
1883 switch(s->feature) {
1884 case 0xcc: /* reverting to power-on defaults enable */
1885 case 0x66: /* reverting to power-on defaults disable */
1886 case 0x02: /* write cache enable */
1887 case 0x82: /* write cache disable */
1888 case 0xaa: /* read look-ahead enable */
1889 case 0x55: /* read look-ahead disable */
1890 case 0x05: /* set advanced power management mode */
1891 case 0x85: /* disable advanced power management mode */
1892 case 0x69: /* NOP */
1893 case 0x67: /* NOP */
1894 case 0x96: /* NOP */
1895 case 0x9a: /* NOP */
1896 s->status = READY_STAT | SEEK_STAT;
1897 ide_set_irq(s);
1898 break;
1899 case 0x03: { /* set transfer mode */
1900 uint8_t val = s->nsector & 0x07;
1901
1902 switch (s->nsector >> 3) {
1903 case 0x00: /* pio default */
1904 case 0x01: /* pio mode */
1905 put_le16(s->identify_data + 63,0x07);
1906 put_le16(s->identify_data + 88,0x3f);
1907 break;
1908 case 0x04: /* mdma mode */
1909 put_le16(s->identify_data + 63,0x07 | (1 << (val + 8)));
1910 put_le16(s->identify_data + 88,0x3f);
1911 break;
1912 case 0x08: /* udma mode */
1913 put_le16(s->identify_data + 63,0x07);
1914 put_le16(s->identify_data + 88,0x3f | (1 << (val + 8)));
1915 break;
1916 default:
1917 goto abort_cmd;
1918 }
1919 s->status = READY_STAT | SEEK_STAT;
1920 ide_set_irq(s);
1921 break;
1922 }
1923 default:
1924 goto abort_cmd;
1925 }
1926 break;
1927 case WIN_FLUSH_CACHE:
1928 case WIN_FLUSH_CACHE_EXT:
1929 if (s->bs)
1930 bdrv_flush(s->bs);
1931 s->status = READY_STAT;
1932 ide_set_irq(s);
1933 break;
1934 case WIN_STANDBYNOW1:
1935 case WIN_STANDBYNOW2:
1936 case WIN_IDLEIMMEDIATE:
1937 case CFA_IDLEIMMEDIATE:
1938 case WIN_SETIDLE1:
1939 case WIN_SETIDLE2:
1940 s->status = READY_STAT;
1941 ide_set_irq(s);
1942 break;
1943 /* ATAPI commands */
1944 case WIN_PIDENTIFY:
1945 if (s->is_cdrom) {
1946 ide_atapi_identify(s);
1947 s->status = READY_STAT | SEEK_STAT;
1948 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1949 } else {
1950 ide_abort_command(s);
1951 }
1952 ide_set_irq(s);
1953 break;
1954 case WIN_DIAGNOSE:
1955 ide_set_signature(s);
1956 s->status = 0x00; /* NOTE: READY is _not_ set */
1957 s->error = 0x01;
1958 break;
1959 case WIN_SRST:
1960 if (!s->is_cdrom)
1961 goto abort_cmd;
1962 ide_set_signature(s);
1963 s->status = 0x00; /* NOTE: READY is _not_ set */
1964 s->error = 0x01;
1965 break;
1966 case WIN_PACKETCMD:
1967 if (!s->is_cdrom)
1968 goto abort_cmd;
1969 /* overlapping commands not supported */
1970 if (s->feature & 0x02)
1971 goto abort_cmd;
1972 s->atapi_dma = s->feature & 1;
1973 s->nsector = 1;
1974 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1975 ide_atapi_cmd);
1976 break;
1977 /* CF-ATA commands */
1978 case CFA_REQ_EXT_ERROR_CODE:
1979 if (!s->is_cf)
1980 goto abort_cmd;
1981 s->error = 0x09; /* miscellaneous error */
1982 s->status = READY_STAT;
1983 ide_set_irq(s);
1984 break;
1985 case CFA_ERASE_SECTORS:
1986 case CFA_WEAR_LEVEL:
1987 if (!s->is_cf)
1988 goto abort_cmd;
1989 if (val == CFA_WEAR_LEVEL)
1990 s->nsector = 0;
1991 if (val == CFA_ERASE_SECTORS)
1992 s->media_changed = 1;
1993 s->error = 0x00;
1994 s->status = READY_STAT;
1995 ide_set_irq(s);
1996 break;
1997 case CFA_TRANSLATE_SECTOR:
1998 if (!s->is_cf)
1999 goto abort_cmd;
2000 s->error = 0x00;
2001 s->status = READY_STAT;
2002 memset(s->io_buffer, 0, 0x200);
2003 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
2004 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
2005 s->io_buffer[0x02] = s->select; /* Head */
2006 s->io_buffer[0x03] = s->sector; /* Sector */
2007 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
2008 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
2009 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
2010 s->io_buffer[0x13] = 0x00; /* Erase flag */
2011 s->io_buffer[0x18] = 0x00; /* Hot count */
2012 s->io_buffer[0x19] = 0x00; /* Hot count */
2013 s->io_buffer[0x1a] = 0x01; /* Hot count */
2014 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
2015 ide_set_irq(s);
2016 break;
2017 case CFA_ACCESS_METADATA_STORAGE:
2018 if (!s->is_cf)
2019 goto abort_cmd;
2020 switch (s->feature) {
2021 case 0x02: /* Inquiry Metadata Storage */
2022 ide_cfata_metadata_inquiry(s);
2023 break;
2024 case 0x03: /* Read Metadata Storage */
2025 ide_cfata_metadata_read(s);
2026 break;
2027 case 0x04: /* Write Metadata Storage */
2028 ide_cfata_metadata_write(s);
2029 break;
2030 default:
2031 goto abort_cmd;
2032 }
2033 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
2034 s->status = 0x00; /* NOTE: READY is _not_ set */
2035 ide_set_irq(s);
2036 break;
2037 case IBM_SENSE_CONDITION:
2038 if (!s->is_cf)
2039 goto abort_cmd;
2040 switch (s->feature) {
2041 case 0x01: /* sense temperature in device */
2042 s->nsector = 0x50; /* +20 C */
2043 break;
2044 default:
2045 goto abort_cmd;
2046 }
2047 s->status = READY_STAT;
2048 ide_set_irq(s);
2049 break;
2050 default:
2051 abort_cmd:
2052 ide_abort_command(s);
2053 ide_set_irq(s);
2054 break;
2055 }
2056 }
2057 }
2058
2059 static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
2060 {
2061 IDEState *ide_if = opaque;
2062 IDEState *s = ide_if->cur_drive;
2063 uint32_t addr;
2064 int ret, hob;
2065
2066 addr = addr1 & 7;
2067 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2068 //hob = s->select & (1 << 7);
2069 hob = 0;
2070 switch(addr) {
2071 case 0:
2072 ret = 0xff;
2073 break;
2074 case 1:
2075 if (!ide_if[0].bs && !ide_if[1].bs)
2076 ret = 0;
2077 else if (!hob)
2078 ret = s->error;
2079 else
2080 ret = s->hob_feature;
2081 break;
2082 case 2:
2083 if (!ide_if[0].bs && !ide_if[1].bs)
2084 ret = 0;
2085 else if (!hob)
2086 ret = s->nsector & 0xff;
2087 else
2088 ret = s->hob_nsector;
2089 break;
2090 case 3:
2091 if (!ide_if[0].bs && !ide_if[1].bs)
2092 ret = 0;
2093 else if (!hob)
2094 ret = s->sector;
2095 else
2096 ret = s->hob_sector;
2097 break;
2098 case 4:
2099 if (!ide_if[0].bs && !ide_if[1].bs)
2100 ret = 0;
2101 else if (!hob)
2102 ret = s->lcyl;
2103 else
2104 ret = s->hob_lcyl;
2105 break;
2106 case 5:
2107 if (!ide_if[0].bs && !ide_if[1].bs)
2108 ret = 0;
2109 else if (!hob)
2110 ret = s->hcyl;
2111 else
2112 ret = s->hob_hcyl;
2113 break;
2114 case 6:
2115 if (!ide_if[0].bs && !ide_if[1].bs)
2116 ret = 0;
2117 else
2118 ret = s->select;
2119 break;
2120 default:
2121 case 7:
2122 if ((!ide_if[0].bs && !ide_if[1].bs) ||
2123 (s != ide_if && !s->bs))
2124 ret = 0;
2125 else
2126 ret = s->status;
2127 qemu_irq_lower(s->irq);
2128 break;
2129 }
2130 #ifdef DEBUG_IDE
2131 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
2132 #endif
2133 return ret;
2134 }
2135
2136 static uint32_t ide_status_read(void *opaque, uint32_t addr)
2137 {
2138 IDEState *ide_if = opaque;
2139 IDEState *s = ide_if->cur_drive;
2140 int ret;
2141
2142 if ((!ide_if[0].bs && !ide_if[1].bs) ||
2143 (s != ide_if && !s->bs))
2144 ret = 0;
2145 else
2146 ret = s->status;
2147 #ifdef DEBUG_IDE
2148 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
2149 #endif
2150 return ret;
2151 }
2152
2153 static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
2154 {
2155 IDEState *ide_if = opaque;
2156 IDEState *s;
2157 int i;
2158
2159 #ifdef DEBUG_IDE
2160 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
2161 #endif
2162 /* common for both drives */
2163 if (!(ide_if[0].cmd & IDE_CMD_RESET) &&
2164 (val & IDE_CMD_RESET)) {
2165 /* reset low to high */
2166 for(i = 0;i < 2; i++) {
2167 s = &ide_if[i];
2168 s->status = BUSY_STAT | SEEK_STAT;
2169 s->error = 0x01;
2170 }
2171 } else if ((ide_if[0].cmd & IDE_CMD_RESET) &&
2172 !(val & IDE_CMD_RESET)) {
2173 /* high to low */
2174 for(i = 0;i < 2; i++) {
2175 s = &ide_if[i];
2176 if (s->is_cdrom)
2177 s->status = 0x00; /* NOTE: READY is _not_ set */
2178 else
2179 s->status = READY_STAT | SEEK_STAT;
2180 ide_set_signature(s);
2181 }
2182 }
2183
2184 ide_if[0].cmd = val;
2185 ide_if[1].cmd = val;
2186 }
2187
2188 static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2189 {
2190 IDEState *s = ((IDEState *)opaque)->cur_drive;
2191 uint8_t *p;
2192
2193 p = s->data_ptr;
2194 *(uint16_t *)p = le16_to_cpu(val);
2195 p += 2;
2196 s->data_ptr = p;
2197 if (p >= s->data_end)
2198 s->end_transfer_func(s);
2199 }
2200
2201 static uint32_t ide_data_readw(void *opaque, uint32_t addr)
2202 {
2203 IDEState *s = ((IDEState *)opaque)->cur_drive;
2204 uint8_t *p;
2205 int ret;
2206 p = s->data_ptr;
2207 ret = cpu_to_le16(*(uint16_t *)p);
2208 p += 2;
2209 s->data_ptr = p;
2210 if (p >= s->data_end)
2211 s->end_transfer_func(s);
2212 return ret;
2213 }
2214
2215 static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2216 {
2217 IDEState *s = ((IDEState *)opaque)->cur_drive;
2218 uint8_t *p;
2219
2220 p = s->data_ptr;
2221 *(uint32_t *)p = le32_to_cpu(val);
2222 p += 4;
2223 s->data_ptr = p;
2224 if (p >= s->data_end)
2225 s->end_transfer_func(s);
2226 }
2227
2228 static uint32_t ide_data_readl(void *opaque, uint32_t addr)
2229 {
2230 IDEState *s = ((IDEState *)opaque)->cur_drive;
2231 uint8_t *p;
2232 int ret;
2233
2234 p = s->data_ptr;
2235 ret = cpu_to_le32(*(uint32_t *)p);
2236 p += 4;
2237 s->data_ptr = p;
2238 if (p >= s->data_end)
2239 s->end_transfer_func(s);
2240 return ret;
2241 }
2242
2243 static void ide_dummy_transfer_stop(IDEState *s)
2244 {
2245 s->data_ptr = s->io_buffer;
2246 s->data_end = s->io_buffer;
2247 s->io_buffer[0] = 0xff;
2248 s->io_buffer[1] = 0xff;
2249 s->io_buffer[2] = 0xff;
2250 s->io_buffer[3] = 0xff;
2251 }
2252
2253 static void ide_reset(IDEState *s)
2254 {
2255 if (s->is_cf)
2256 s->mult_sectors = 0;
2257 else
2258 s->mult_sectors = MAX_MULT_SECTORS;
2259 s->cur_drive = s;
2260 s->select = 0xa0;
2261 s->status = READY_STAT;
2262 ide_set_signature(s);
2263 /* init the transfer handler so that 0xffff is returned on data
2264 accesses */
2265 s->end_transfer_func = ide_dummy_transfer_stop;
2266 ide_dummy_transfer_stop(s);
2267 s->media_changed = 0;
2268 }
2269
2270 struct partition {
2271 uint8_t boot_ind; /* 0x80 - active */
2272 uint8_t head; /* starting head */
2273 uint8_t sector; /* starting sector */
2274 uint8_t cyl; /* starting cylinder */
2275 uint8_t sys_ind; /* What partition type */
2276 uint8_t end_head; /* end head */
2277 uint8_t end_sector; /* end sector */
2278 uint8_t end_cyl; /* end cylinder */
2279 uint32_t start_sect; /* starting sector counting from 0 */
2280 uint32_t nr_sects; /* nr of sectors in partition */
2281 } __attribute__((packed));
2282
2283 /* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
2284 static int guess_disk_lchs(IDEState *s,
2285 int *pcylinders, int *pheads, int *psectors)
2286 {
2287 uint8_t buf[512];
2288 int ret, i, heads, sectors, cylinders;
2289 struct partition *p;
2290 uint32_t nr_sects;
2291
2292 ret = bdrv_read(s->bs, 0, buf, 1);
2293 if (ret < 0)
2294 return -1;
2295 /* test msdos magic */
2296 if (buf[510] != 0x55 || buf[511] != 0xaa)
2297 return -1;
2298 for(i = 0; i < 4; i++) {
2299 p = ((struct partition *)(buf + 0x1be)) + i;
2300 nr_sects = le32_to_cpu(p->nr_sects);
2301 if (nr_sects && p->end_head) {
2302 /* We make the assumption that the partition terminates on
2303 a cylinder boundary */
2304 heads = p->end_head + 1;
2305 sectors = p->end_sector & 63;
2306 if (sectors == 0)
2307 continue;
2308 cylinders = s->nb_sectors / (heads * sectors);
2309 if (cylinders < 1 || cylinders > 16383)
2310 continue;
2311 *pheads = heads;
2312 *psectors = sectors;
2313 *pcylinders = cylinders;
2314 #if 0
2315 printf("guessed geometry: LCHS=%d %d %d\n",
2316 cylinders, heads, sectors);
2317 #endif
2318 return 0;
2319 }
2320 }
2321 return -1;
2322 }
2323
2324 static void ide_init2(IDEState *ide_state,
2325 BlockDriverState *hd0, BlockDriverState *hd1,
2326 qemu_irq irq)
2327 {
2328 IDEState *s;
2329 static int drive_serial = 1;
2330 int i, cylinders, heads, secs, translation, lba_detected = 0;
2331 int64_t nb_sectors;
2332
2333 for(i = 0; i < 2; i++) {
2334 s = ide_state + i;
2335 if (i == 0)
2336 s->bs = hd0;
2337 else
2338 s->bs = hd1;
2339 if (s->bs) {
2340 bdrv_get_geometry(s->bs, &nb_sectors);
2341 s->nb_sectors = nb_sectors;
2342 /* if a geometry hint is available, use it */
2343 bdrv_get_geometry_hint(s->bs, &cylinders, &heads, &secs);
2344 translation = bdrv_get_translation_hint(s->bs);
2345 if (cylinders != 0) {
2346 s->cylinders = cylinders;
2347 s->heads = heads;
2348 s->sectors = secs;
2349 } else {
2350 if (guess_disk_lchs(s, &cylinders, &heads, &secs) == 0) {
2351 if (heads > 16) {
2352 /* if heads > 16, it means that a BIOS LBA
2353 translation was active, so the default
2354 hardware geometry is OK */
2355 lba_detected = 1;
2356 goto default_geometry;
2357 } else {
2358 s->cylinders = cylinders;
2359 s->heads = heads;
2360 s->sectors = secs;
2361 /* disable any translation to be in sync with
2362 the logical geometry */
2363 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
2364 bdrv_set_translation_hint(s->bs,
2365 BIOS_ATA_TRANSLATION_NONE);
2366 }
2367 }
2368 } else {
2369 default_geometry:
2370 /* if no geometry, use a standard physical disk geometry */
2371 cylinders = nb_sectors / (16 * 63);
2372 if (cylinders > 16383)
2373 cylinders = 16383;
2374 else if (cylinders < 2)
2375 cylinders = 2;
2376 s->cylinders = cylinders;
2377 s->heads = 16;
2378 s->sectors = 63;
2379 if ((lba_detected == 1) && (translation == BIOS_ATA_TRANSLATION_AUTO)) {
2380 if ((s->cylinders * s->heads) <= 131072) {
2381 bdrv_set_translation_hint(s->bs,
2382 BIOS_ATA_TRANSLATION_LARGE);
2383 } else {
2384 bdrv_set_translation_hint(s->bs,
2385 BIOS_ATA_TRANSLATION_LBA);
2386 }
2387 }
2388 }
2389 bdrv_set_geometry_hint(s->bs, s->cylinders, s->heads, s->sectors);
2390 }
2391 if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
2392 s->is_cdrom = 1;
2393 bdrv_set_change_cb(s->bs, cdrom_change_cb, s);
2394 }
2395 }
2396 s->drive_serial = drive_serial++;
2397 s->irq = irq;
2398 s->sector_write_timer = qemu_new_timer(vm_clock,
2399 ide_sector_write_timer_cb, s);
2400 ide_reset(s);
2401 }
2402 }
2403
2404 static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
2405 {
2406 register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
2407 register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
2408 if (iobase2) {
2409 register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
2410 register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
2411 }
2412
2413 /* data ports */
2414 register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
2415 register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
2416 register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
2417 register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
2418 }
2419
2420 /* save per IDE drive data */
2421 static void ide_save(QEMUFile* f, IDEState *s)
2422 {
2423 qemu_put_be32s(f, &s->mult_sectors);
2424 qemu_put_be32s(f, &s->identify_set);
2425 if (s->identify_set) {
2426 qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512);
2427 }
2428 qemu_put_8s(f, &s->feature);
2429 qemu_put_8s(f, &s->error);
2430 qemu_put_be32s(f, &s->nsector);
2431 qemu_put_8s(f, &s->sector);
2432 qemu_put_8s(f, &s->lcyl);
2433 qemu_put_8s(f, &s->hcyl);
2434 qemu_put_8s(f, &s->hob_feature);
2435 qemu_put_8s(f, &s->hob_nsector);
2436 qemu_put_8s(f, &s->hob_sector);
2437 qemu_put_8s(f, &s->hob_lcyl);
2438 qemu_put_8s(f, &s->hob_hcyl);
2439 qemu_put_8s(f, &s->select);
2440 qemu_put_8s(f, &s->status);
2441 qemu_put_8s(f, &s->lba48);
2442
2443 qemu_put_8s(f, &s->sense_key);
2444 qemu_put_8s(f, &s->asc);
2445 /* XXX: if a transfer is pending, we do not save it yet */
2446 }
2447
2448 /* load per IDE drive data */
2449 static void ide_load(QEMUFile* f, IDEState *s)
2450 {
2451 qemu_get_be32s(f, &s->mult_sectors);
2452 qemu_get_be32s(f, &s->identify_set);
2453 if (s->identify_set) {
2454 qemu_get_buffer(f, (uint8_t *)s->identify_data, 512);
2455 }
2456 qemu_get_8s(f, &s->feature);
2457 qemu_get_8s(f, &s->error);
2458 qemu_get_be32s(f, &s->nsector);
2459 qemu_get_8s(f, &s->sector);
2460 qemu_get_8s(f, &s->lcyl);
2461 qemu_get_8s(f, &s->hcyl);
2462 qemu_get_8s(f, &s->hob_feature);
2463 qemu_get_8s(f, &s->hob_nsector);
2464 qemu_get_8s(f, &s->hob_sector);
2465 qemu_get_8s(f, &s->hob_lcyl);
2466 qemu_get_8s(f, &s->hob_hcyl);
2467 qemu_get_8s(f, &s->select);
2468 qemu_get_8s(f, &s->status);
2469 qemu_get_8s(f, &s->lba48);
2470
2471 qemu_get_8s(f, &s->sense_key);
2472 qemu_get_8s(f, &s->asc);
2473 /* XXX: if a transfer is pending, we do not save it yet */
2474 }
2475
2476 /***********************************************************/
2477 /* ISA IDE definitions */
2478
2479 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
2480 BlockDriverState *hd0, BlockDriverState *hd1)
2481 {
2482 IDEState *ide_state;
2483
2484 ide_state = qemu_mallocz(sizeof(IDEState) * 2);
2485 if (!ide_state)
2486 return;
2487
2488 ide_init2(ide_state, hd0, hd1, irq);
2489 ide_init_ioport(ide_state, iobase, iobase2);
2490 }
2491
2492 /***********************************************************/
2493 /* PCI IDE definitions */
2494
2495 static void cmd646_update_irq(PCIIDEState *d);
2496
2497 static void ide_map(PCIDevice *pci_dev, int region_num,
2498 uint32_t addr, uint32_t size, int type)
2499 {
2500 PCIIDEState *d = (PCIIDEState *)pci_dev;
2501 IDEState *ide_state;
2502
2503 if (region_num <= 3) {
2504 ide_state = &d->ide_if[(region_num >> 1) * 2];
2505 if (region_num & 1) {
2506 register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state);
2507 register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state);
2508 } else {
2509 register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state);
2510 register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state);
2511
2512 /* data ports */
2513 register_ioport_write(addr, 2, 2, ide_data_writew, ide_state);
2514 register_ioport_read(addr, 2, 2, ide_data_readw, ide_state);
2515 register_ioport_write(addr, 4, 4, ide_data_writel, ide_state);
2516 register_ioport_read(addr, 4, 4, ide_data_readl, ide_state);
2517 }
2518 }
2519 }
2520
2521 static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
2522 {
2523 BMDMAState *bm = s->bmdma;
2524 if(!bm)
2525 return;
2526 bm->ide_if = s;
2527 bm->dma_cb = dma_cb;
2528 bm->cur_prd_last = 0;
2529 bm->cur_prd_addr = 0;
2530 bm->cur_prd_len = 0;
2531 if (bm->status & BM_STATUS_DMAING) {
2532 bm->dma_cb(bm, 0);
2533 }
2534 }
2535
2536 static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
2537 {
2538 BMDMAState *bm = opaque;
2539 #ifdef DEBUG_IDE
2540 printf("%s: 0x%08x\n", __func__, val);
2541 #endif
2542 if (!(val & BM_CMD_START)) {
2543 /* XXX: do it better */
2544 if (bm->status & BM_STATUS_DMAING) {
2545 bm->status &= ~BM_STATUS_DMAING;
2546 /* cancel DMA request */
2547 bm->ide_if = NULL;
2548 bm->dma_cb = NULL;
2549 if (bm->aiocb) {
2550 #ifdef DEBUG_AIO
2551 printf("aio_cancel\n");
2552 #endif
2553 bdrv_aio_cancel(bm->aiocb);
2554 bm->aiocb = NULL;
2555 }
2556 }
2557 bm->cmd = val & 0x09;
2558 } else {
2559 if (!(bm->status & BM_STATUS_DMAING)) {
2560 bm->status |= BM_STATUS_DMAING;
2561 /* start dma transfer if possible */
2562 if (bm->dma_cb)
2563 bm->dma_cb(bm, 0);
2564 }
2565 bm->cmd = val & 0x09;
2566 }
2567 }
2568
2569 static uint32_t bmdma_readb(void *opaque, uint32_t addr)
2570 {
2571 BMDMAState *bm = opaque;
2572 PCIIDEState *pci_dev;
2573 uint32_t val;
2574
2575 switch(addr & 3) {
2576 case 0:
2577 val = bm->cmd;
2578 break;
2579 case 1:
2580 pci_dev = bm->pci_dev;
2581 if (pci_dev->type == IDE_TYPE_CMD646) {
2582 val = pci_dev->dev.config[MRDMODE];
2583 } else {
2584 val = 0xff;
2585 }
2586 break;
2587 case 2:
2588 val = bm->status;
2589 break;
2590 case 3:
2591 pci_dev = bm->pci_dev;
2592 if (pci_dev->type == IDE_TYPE_CMD646) {
2593 if (bm == &pci_dev->bmdma[0])
2594 val = pci_dev->dev.config[UDIDETCR0];
2595 else
2596 val = pci_dev->dev.config[UDIDETCR1];
2597 } else {
2598 val = 0xff;
2599 }
2600 break;
2601 default:
2602 val = 0xff;
2603 break;
2604 }
2605 #ifdef DEBUG_IDE
2606 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
2607 #endif
2608 return val;
2609 }
2610
2611 static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
2612 {
2613 BMDMAState *bm = opaque;
2614 PCIIDEState *pci_dev;
2615 #ifdef DEBUG_IDE
2616 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
2617 #endif
2618 switch(addr & 3) {
2619 case 1:
2620 pci_dev = bm->pci_dev;
2621 if (pci_dev->type == IDE_TYPE_CMD646) {
2622 pci_dev->dev.config[MRDMODE] =
2623 (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
2624 cmd646_update_irq(pci_dev);
2625 }
2626 break;
2627 case 2:
2628 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
2629 break;
2630 case 3:
2631 pci_dev = bm->pci_dev;
2632 if (pci_dev->type == IDE_TYPE_CMD646) {
2633 if (bm == &pci_dev->bmdma[0])
2634 pci_dev->dev.config[UDIDETCR0] = val;
2635 else
2636 pci_dev->dev.config[UDIDETCR1] = val;
2637 }
2638 break;
2639 }
2640 }
2641
2642 static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
2643 {
2644 BMDMAState *bm = opaque;
2645 uint32_t val;
2646 val = bm->addr;
2647 #ifdef DEBUG_IDE
2648 printf("%s: 0x%08x\n", __func__, val);
2649 #endif
2650 return val;
2651 }
2652
2653 static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
2654 {
2655 BMDMAState *bm = opaque;
2656 #ifdef DEBUG_IDE
2657 printf("%s: 0x%08x\n", __func__, val);
2658 #endif
2659 bm->addr = val & ~3;
2660 bm->cur_addr = bm->addr;
2661 }
2662
2663 static void bmdma_map(PCIDevice *pci_dev, int region_num,
2664 uint32_t addr, uint32_t size, int type)
2665 {
2666 PCIIDEState *d = (PCIIDEState *)pci_dev;
2667 int i;
2668
2669 for(i = 0;i < 2; i++) {
2670 BMDMAState *bm = &d->bmdma[i];
2671 d->ide_if[2 * i].bmdma = bm;
2672 d->ide_if[2 * i + 1].bmdma = bm;
2673 bm->pci_dev = (PCIIDEState *)pci_dev;
2674
2675 register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
2676
2677 register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
2678 register_ioport_read(addr, 4, 1, bmdma_readb, bm);
2679
2680 register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
2681 register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
2682 addr += 8;
2683 }
2684 }
2685
2686 /* XXX: call it also when the MRDMODE is changed from the PCI config
2687 registers */
2688 static void cmd646_update_irq(PCIIDEState *d)
2689 {
2690 int pci_level;
2691 pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
2692 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
2693 ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
2694 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
2695 qemu_set_irq(d->dev.irq[0], pci_level);
2696 }
2697
2698 /* the PCI irq level is the logical OR of the two channels */
2699 static void cmd646_set_irq(void *opaque, int channel, int level)
2700 {
2701 PCIIDEState *d = opaque;
2702 int irq_mask;
2703
2704 irq_mask = MRDMODE_INTR_CH0 << channel;
2705 if (level)
2706 d->dev.config[MRDMODE] |= irq_mask;
2707 else
2708 d->dev.config[MRDMODE] &= ~irq_mask;
2709 cmd646_update_irq(d);
2710 }
2711
2712 /* CMD646 PCI IDE controller */
2713 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
2714 int secondary_ide_enabled)
2715 {
2716 PCIIDEState *d;
2717 uint8_t *pci_conf;
2718 int i;
2719 qemu_irq *irq;
2720
2721 d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
2722 sizeof(PCIIDEState),
2723 -1,
2724 NULL, NULL);
2725 d->type = IDE_TYPE_CMD646;
2726 pci_conf = d->dev.config;
2727 pci_conf[0x00] = 0x95; // CMD646
2728 pci_conf[0x01] = 0x10;
2729 pci_conf[0x02] = 0x46;
2730 pci_conf[0x03] = 0x06;
2731
2732 pci_conf[0x08] = 0x07; // IDE controller revision
2733 pci_conf[0x09] = 0x8f;
2734
2735 pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2736 pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2737 pci_conf[0x0e] = 0x00; // header_type
2738
2739 if (secondary_ide_enabled) {
2740 /* XXX: if not enabled, really disable the seconday IDE controller */
2741 pci_conf[0x51] = 0x80; /* enable IDE1 */
2742 }
2743
2744 pci_register_io_region((PCIDevice *)d, 0, 0x8,
2745 PCI_ADDRESS_SPACE_IO, ide_map);
2746 pci_register_io_region((PCIDevice *)d, 1, 0x4,
2747 PCI_ADDRESS_SPACE_IO, ide_map);
2748 pci_register_io_region((PCIDevice *)d, 2, 0x8,
2749 PCI_ADDRESS_SPACE_IO, ide_map);
2750 pci_register_io_region((PCIDevice *)d, 3, 0x4,
2751 PCI_ADDRESS_SPACE_IO, ide_map);
2752 pci_register_io_region((PCIDevice *)d, 4, 0x10,
2753 PCI_ADDRESS_SPACE_IO, bmdma_map);
2754
2755 pci_conf[0x3d] = 0x01; // interrupt on pin 1
2756
2757 for(i = 0; i < 4; i++)
2758 d->ide_if[i].pci_dev = (PCIDevice *)d;
2759
2760 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
2761 ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]);
2762 ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
2763 }
2764
2765 static void pci_ide_save(QEMUFile* f, void *opaque)
2766 {
2767 PCIIDEState *d = opaque;
2768 int i;
2769
2770 pci_device_save(&d->dev, f);
2771
2772 for(i = 0; i < 2; i++) {
2773 BMDMAState *bm = &d->bmdma[i];
2774 qemu_put_8s(f, &bm->cmd);
2775 qemu_put_8s(f, &bm->status);
2776 qemu_put_be32s(f, &bm->addr);
2777 /* XXX: if a transfer is pending, we do not save it yet */
2778 }
2779
2780 /* per IDE interface data */
2781 for(i = 0; i < 2; i++) {
2782 IDEState *s = &d->ide_if[i * 2];
2783 uint8_t drive1_selected;
2784 qemu_put_8s(f, &s->cmd);
2785 drive1_selected = (s->cur_drive != s);
2786 qemu_put_8s(f, &drive1_selected);
2787 }
2788
2789 /* per IDE drive data */
2790 for(i = 0; i < 4; i++) {
2791 ide_save(f, &d->ide_if[i]);
2792 }
2793 }
2794
2795 static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
2796 {
2797 PCIIDEState *d = opaque;
2798 int ret, i;
2799
2800 if (version_id != 1)
2801 return -EINVAL;
2802 ret = pci_device_load(&d->dev, f);
2803 if (ret < 0)
2804 return ret;
2805
2806 for(i = 0; i < 2; i++) {
2807 BMDMAState *bm = &d->bmdma[i];
2808 qemu_get_8s(f, &bm->cmd);
2809 qemu_get_8s(f, &bm->status);
2810 qemu_get_be32s(f, &bm->addr);
2811 /* XXX: if a transfer is pending, we do not save it yet */
2812 }
2813
2814 /* per IDE interface data */
2815 for(i = 0; i < 2; i++) {
2816 IDEState *s = &d->ide_if[i * 2];
2817 uint8_t drive1_selected;
2818 qemu_get_8s(f, &s->cmd);
2819 qemu_get_8s(f, &drive1_selected);
2820 s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)];
2821 }
2822
2823 /* per IDE drive data */
2824 for(i = 0; i < 4; i++) {
2825 ide_load(f, &d->ide_if[i]);
2826 }
2827 return 0;
2828 }
2829
2830 static void piix3_reset(PCIIDEState *d)
2831 {
2832 uint8_t *pci_conf = d->dev.config;
2833
2834 pci_conf[0x04] = 0x00;
2835 pci_conf[0x05] = 0x00;
2836 pci_conf[0x06] = 0x80; /* FBC */
2837 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
2838 pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
2839 }
2840
2841 /* hd_table must contain 4 block drivers */
2842 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2843 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
2844 qemu_irq *pic)
2845 {
2846 PCIIDEState *d;
2847 uint8_t *pci_conf;
2848
2849 /* register a function 1 of PIIX3 */
2850 d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
2851 sizeof(PCIIDEState),
2852 devfn,
2853 NULL, NULL);
2854 d->type = IDE_TYPE_PIIX3;
2855
2856 pci_conf = d->dev.config;
2857 pci_conf[0x00] = 0x86; // Intel
2858 pci_conf[0x01] = 0x80;
2859 pci_conf[0x02] = 0x10;
2860 pci_conf[0x03] = 0x70;
2861 pci_conf[0x09] = 0x80; // legacy ATA mode
2862 pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2863 pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2864 pci_conf[0x0e] = 0x00; // header_type
2865
2866 piix3_reset(d);
2867
2868 pci_register_io_region((PCIDevice *)d, 4, 0x10,
2869 PCI_ADDRESS_SPACE_IO, bmdma_map);
2870
2871 ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
2872 ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
2873 ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2874 ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2875
2876 register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
2877 }
2878
2879 /* hd_table must contain 4 block drivers */
2880 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
2881 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
2882 qemu_irq *pic)
2883 {
2884 PCIIDEState *d;
2885 uint8_t *pci_conf;
2886
2887 /* register a function 1 of PIIX4 */
2888 d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
2889 sizeof(PCIIDEState),
2890 devfn,
2891 NULL, NULL);
2892 d->type = IDE_TYPE_PIIX4;
2893
2894 pci_conf = d->dev.config;
2895 pci_conf[0x00] = 0x86; // Intel
2896 pci_conf[0x01] = 0x80;
2897 pci_conf[0x02] = 0x11;
2898 pci_conf[0x03] = 0x71;
2899 pci_conf[0x09] = 0x80; // legacy ATA mode
2900 pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2901 pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2902 pci_conf[0x0e] = 0x00; // header_type
2903
2904 piix3_reset(d);
2905
2906 pci_register_io_region((PCIDevice *)d, 4, 0x10,
2907 PCI_ADDRESS_SPACE_IO, bmdma_map);
2908
2909 ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
2910 ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
2911 ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2912 ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2913
2914 register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
2915 }
2916
2917 /***********************************************************/
2918 /* MacIO based PowerPC IDE */
2919
2920 /* PowerMac IDE memory IO */
2921 static void pmac_ide_writeb (void *opaque,
2922 target_phys_addr_t addr, uint32_t val)
2923 {
2924 addr = (addr & 0xFFF) >> 4;
2925 switch (addr) {
2926 case 1 ... 7:
2927 ide_ioport_write(opaque, addr, val);
2928 break;
2929 case 8:
2930 case 22:
2931 ide_cmd_write(opaque, 0, val);
2932 break;
2933 default:
2934 break;
2935 }
2936 }
2937
2938 static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
2939 {
2940 uint8_t retval;
2941
2942 addr = (addr & 0xFFF) >> 4;
2943 switch (addr) {
2944 case 1 ... 7:
2945 retval = ide_ioport_read(opaque, addr);
2946 break;
2947 case 8:
2948 case 22:
2949 retval = ide_status_read(opaque, 0);
2950 break;
2951 default:
2952 retval = 0xFF;
2953 break;
2954 }
2955 return retval;
2956 }
2957
2958 static void pmac_ide_writew (void *opaque,
2959 target_phys_addr_t addr, uint32_t val)
2960 {
2961 addr = (addr & 0xFFF) >> 4;
2962 #ifdef TARGET_WORDS_BIGENDIAN
2963 val = bswap16(val);
2964 #endif
2965 if (addr == 0) {
2966 ide_data_writew(opaque, 0, val);
2967 }
2968 }
2969
2970 static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
2971 {
2972 uint16_t retval;
2973
2974 addr = (addr & 0xFFF) >> 4;
2975 if (addr == 0) {
2976 retval = ide_data_readw(opaque, 0);
2977 } else {
2978 retval = 0xFFFF;
2979 }
2980 #ifdef TARGET_WORDS_BIGENDIAN
2981 retval = bswap16(retval);
2982 #endif
2983 return retval;
2984 }
2985
2986 static void pmac_ide_writel (void *opaque,
2987 target_phys_addr_t addr, uint32_t val)
2988 {
2989 addr = (addr & 0xFFF) >> 4;
2990 #ifdef TARGET_WORDS_BIGENDIAN
2991 val = bswap32(val);
2992 #endif
2993 if (addr == 0) {
2994 ide_data_writel(opaque, 0, val);
2995 }
2996 }
2997
2998 static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
2999 {
3000 uint32_t retval;
3001
3002 addr = (addr & 0xFFF) >> 4;
3003 if (addr == 0) {
3004 retval = ide_data_readl(opaque, 0);
3005 } else {
3006 retval = 0xFFFFFFFF;
3007 }
3008 #ifdef TARGET_WORDS_BIGENDIAN
3009 retval = bswap32(retval);
3010 #endif
3011 return retval;
3012 }
3013
3014 static CPUWriteMemoryFunc *pmac_ide_write[] = {
3015 pmac_ide_writeb,
3016 pmac_ide_writew,
3017 pmac_ide_writel,
3018 };
3019
3020 static CPUReadMemoryFunc *pmac_ide_read[] = {
3021 pmac_ide_readb,
3022 pmac_ide_readw,
3023 pmac_ide_readl,
3024 };
3025
3026 /* hd_table must contain 4 block drivers */
3027 /* PowerMac uses memory mapped registers, not I/O. Return the memory
3028 I/O index to access the ide. */
3029 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
3030 {
3031 IDEState *ide_if;
3032 int pmac_ide_memory;
3033
3034 ide_if = qemu_mallocz(sizeof(IDEState) * 2);
3035 ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq);
3036
3037 pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
3038 pmac_ide_write, &ide_if[0]);
3039 return pmac_ide_memory;
3040 }
3041
3042 /***********************************************************/
3043 /* CF-ATA Microdrive */
3044
3045 #define METADATA_SIZE 0x20
3046
3047 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
3048 struct md_s {
3049 IDEState ide[2];
3050 struct pcmcia_card_s card;
3051 uint32_t attr_base;
3052 uint32_t io_base;
3053
3054 /* Card state */
3055 uint8_t opt;
3056 uint8_t stat;
3057 uint8_t pins;
3058
3059 uint8_t ctrl;
3060 uint16_t io;
3061 int cycle;
3062 };
3063
3064 /* Register bitfields */
3065 enum md_opt {
3066 OPT_MODE_MMAP = 0,
3067 OPT_MODE_IOMAP16 = 1,
3068 OPT_MODE_IOMAP1 = 2,
3069 OPT_MODE_IOMAP2 = 3,
3070 OPT_MODE = 0x3f,
3071 OPT_LEVIREQ = 0x40,
3072 OPT_SRESET = 0x80,
3073 };
3074 enum md_cstat {
3075 STAT_INT = 0x02,
3076 STAT_PWRDWN = 0x04,
3077 STAT_XE = 0x10,
3078 STAT_IOIS8 = 0x20,
3079 STAT_SIGCHG = 0x40,
3080 STAT_CHANGED = 0x80,
3081 };
3082 enum md_pins {
3083 PINS_MRDY = 0x02,
3084 PINS_CRDY = 0x20,
3085 };
3086 enum md_ctrl {
3087 CTRL_IEN = 0x02,
3088 CTRL_SRST = 0x04,
3089 };
3090
3091 static inline void md_interrupt_update(struct md_s *s)
3092 {
3093 if (!s->card.slot)
3094 return;
3095
3096 qemu_set_irq(s->card.slot->irq,
3097 !(s->stat & STAT_INT) && /* Inverted */
3098 !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
3099 !(s->opt & OPT_SRESET));
3100 }
3101
3102 static void md_set_irq(void *opaque, int irq, int level)
3103 {
3104 struct md_s *s = (struct md_s *) opaque;
3105 if (level)
3106 s->stat |= STAT_INT;
3107 else
3108 s->stat &= ~STAT_INT;
3109
3110 md_interrupt_update(s);
3111 }
3112
3113 static void md_reset(struct md_s *s)
3114 {
3115 s->opt = OPT_MODE_MMAP;
3116 s->stat = 0;
3117 s->pins = 0;
3118 s->cycle = 0;
3119 s->ctrl = 0;
3120 ide_reset(s->ide);
3121 }
3122
3123 static uint8_t md_attr_read(void *opaque, uint32_t at)
3124 {
3125 struct md_s *s = (struct md_s *) opaque;
3126 if (at < s->attr_base) {
3127 if (at < s->card.cis_len)
3128 return s->card.cis[at];
3129 else
3130 return 0x00;
3131 }
3132
3133 at -= s->attr_base;
3134
3135 switch (at) {
3136 case 0x00: /* Configuration Option Register */
3137 return s->opt;
3138 case 0x02: /* Card Configuration Status Register */
3139 if (s->ctrl & CTRL_IEN)
3140 return s->stat & ~STAT_INT;
3141 else
3142 return s->stat;
3143 case 0x04: /* Pin Replacement Register */
3144 return (s->pins & PINS_CRDY) | 0x0c;
3145 case 0x06: /* Socket and Copy Register */
3146 return 0x00;
3147 #ifdef VERBOSE
3148 default:
3149 printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
3150 #endif
3151 }
3152
3153 return 0;
3154 }
3155
3156 static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
3157 {
3158 struct md_s *s = (struct md_s *) opaque;
3159 at -= s->attr_base;
3160
3161 switch (at) {
3162 case 0x00: /* Configuration Option Register */
3163 s->opt = value & 0xcf;
3164 if (value & OPT_SRESET)
3165 md_reset(s);
3166 md_interrupt_update(s);
3167 break;
3168 case 0x02: /* Card Configuration Status Register */
3169 if ((s->stat ^ value) & STAT_PWRDWN)
3170 s->pins |= PINS_CRDY;
3171 s->stat &= 0x82;
3172 s->stat |= value & 0x74;
3173 md_interrupt_update(s);
3174 /* Word 170 in Identify Device must be equal to STAT_XE */
3175 break;
3176 case 0x04: /* Pin Replacement Register */
3177 s->pins &= PINS_CRDY;
3178 s->pins |= value & PINS_MRDY;
3179 break;
3180 case 0x06: /* Socket and Copy Register */
3181 break;
3182 default:
3183 printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
3184 }
3185 }
3186
3187 static uint16_t md_common_read(void *opaque, uint32_t at)
3188 {
3189 struct md_s *s = (struct md_s *) opaque;
3190 uint16_t ret;
3191 at -= s->io_base;
3192
3193 switch (s->opt & OPT_MODE) {
3194 case OPT_MODE_MMAP:
3195 if ((at & ~0x3ff) == 0x400)
3196 at = 0;
3197 break;
3198 case OPT_MODE_IOMAP16:
3199 at &= 0xf;
3200 break;
3201 case OPT_MODE_IOMAP1:
3202 if ((at & ~0xf) == 0x3f0)
3203 at -= 0x3e8;
3204 else if ((at & ~0xf) == 0x1f0)
3205 at -= 0x1f0;
3206 break;
3207 case OPT_MODE_IOMAP2:
3208 if ((at & ~0xf) == 0x370)
3209 at -= 0x368;
3210 else if ((at & ~0xf) == 0x170)
3211 at -= 0x170;
3212 }
3213
3214 switch (at) {
3215 case 0x0: /* Even RD Data */
3216 case 0x8:
3217 return ide_data_readw(s->ide, 0);
3218
3219 /* TODO: 8-bit accesses */
3220 if (s->cycle)
3221 ret = s->io >> 8;
3222 else {
3223 s->io = ide_data_readw(s->ide, 0);
3224 ret = s->io & 0xff;
3225 }
3226 s->cycle = !s->cycle;
3227 return ret;
3228 case 0x9: /* Odd RD Data */
3229 return s->io >> 8;
3230 case 0xd: /* Error */
3231 return ide_ioport_read(s->ide, 0x1);
3232 case 0xe: /* Alternate Status */
3233 if (s->ide->cur_drive->bs)
3234 return s->ide->cur_drive->status;
3235 else
3236 return 0;
3237 case 0xf: /* Device Address */
3238 return 0xc2 | ((~s->ide->select << 2) & 0x3c);
3239 default:
3240 return ide_ioport_read(s->ide, at);
3241 }
3242
3243 return 0;
3244 }
3245
3246 static void md_common_write(void *opaque, uint32_t at, uint16_t value)
3247 {
3248 struct md_s *s = (struct md_s *) opaque;
3249 at -= s->io_base;
3250
3251 switch (s->opt & OPT_MODE) {
3252 case OPT_MODE_MMAP:
3253 if ((at & ~0x3ff) == 0x400)
3254 at = 0;
3255 break;
3256 case OPT_MODE_IOMAP16:
3257 at &= 0xf;
3258 break;
3259 case OPT_MODE_IOMAP1:
3260 if ((at & ~0xf) == 0x3f0)
3261 at -= 0x3e8;
3262 else if ((at & ~0xf) == 0x1f0)
3263 at -= 0x1f0;
3264 break;
3265 case OPT_MODE_IOMAP2:
3266 if ((at & ~0xf) == 0x370)
3267 at -= 0x368;
3268 else if ((at & ~0xf) == 0x170)
3269 at -= 0x170;
3270 }
3271
3272 switch (at) {
3273 case 0x0: /* Even WR Data */
3274 case 0x8:
3275 ide_data_writew(s->ide, 0, value);
3276 break;
3277
3278 /* TODO: 8-bit accesses */
3279 if (s->cycle)
3280 ide_data_writew(s->ide, 0, s->io | (value << 8));
3281 else
3282 s->io = value & 0xff;
3283 s->cycle = !s->cycle;
3284 break;
3285 case 0x9:
3286 s->io = value & 0xff;
3287 s->cycle = !s->cycle;
3288 break;
3289 case 0xd: /* Features */
3290 ide_ioport_write(s->ide, 0x1, value);
3291 break;
3292 case 0xe: /* Device Control */
3293 s->ctrl = value;
3294 if (value & CTRL_SRST)
3295 md_reset(s);
3296 md_interrupt_update(s);
3297 break;
3298 default:
3299 if (s->stat & STAT_PWRDWN) {
3300 s->pins |= PINS_CRDY;
3301 s->stat &= ~STAT_PWRDWN;
3302 }
3303 ide_ioport_write(s->ide, at, value);
3304 }
3305 }
3306
3307 static void md_save(QEMUFile *f, void *opaque)
3308 {
3309 struct md_s *s = (struct md_s *) opaque;
3310 int i;
3311 uint8_t drive1_selected;
3312
3313 qemu_put_8s(f, &s->opt);
3314 qemu_put_8s(f, &s->stat);
3315 qemu_put_8s(f, &s->pins);
3316
3317 qemu_put_8s(f, &s->ctrl);
3318 qemu_put_be16s(f, &s->io);
3319 qemu_put_byte(f, s->cycle);
3320
3321 drive1_selected = (s->ide->cur_drive != s->ide);
3322 qemu_put_8s(f, &s->ide->cmd);
3323 qemu_put_8s(f, &drive1_selected);
3324
3325 for (i = 0; i < 2; i ++)
3326 ide_save(f, &s->ide[i]);
3327 }
3328
3329 static int md_load(QEMUFile *f, void *opaque, int version_id)
3330 {
3331 struct md_s *s = (struct md_s *) opaque;
3332 int i;
3333 uint8_t drive1_selected;
3334
3335 qemu_get_8s(f, &s->opt);
3336 qemu_get_8s(f, &s->stat);
3337 qemu_get_8s(f, &s->pins);
3338
3339 qemu_get_8s(f, &s->ctrl);
3340 qemu_get_be16s(f, &s->io);
3341 s->cycle = qemu_get_byte(f);
3342
3343 qemu_get_8s(f, &s->ide->cmd);
3344 qemu_get_8s(f, &drive1_selected);
3345 s->ide->cur_drive = &s->ide[(drive1_selected != 0)];
3346
3347 for (i = 0; i < 2; i ++)
3348 ide_load(f, &s->ide[i]);
3349
3350 return 0;
3351 }
3352
3353 static int md_iid = 0;
3354
3355 static const uint8_t dscm1xxxx_cis[0x14a] = {
3356 [0x000] = CISTPL_DEVICE, /* 5V Device Information */
3357 [0x002] = 0x03, /* Tuple length = 4 bytes */
3358 [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3359 [0x006] = 0x01, /* Size = 2K bytes */
3360 [0x008] = CISTPL_ENDMARK,
3361
3362 [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
3363 [0x00c] = 0x04, /* Tuple length = 4 byest */
3364 [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
3365 [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3366 [0x012] = 0x01, /* Size = 2K bytes */
3367 [0x014] = CISTPL_ENDMARK,
3368
3369 [0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
3370 [0x018] = 0x02, /* Tuple length = 2 bytes */
3371 [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
3372 [0x01c] = 0x01,
3373
3374 [0x01e] = CISTPL_MANFID, /* Manufacture ID */
3375 [0x020] = 0x04, /* Tuple length = 4 bytes */
3376 [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
3377 [0x024] = 0x00,
3378 [0x026] = 0x00, /* PLMID_CARD = 0000 */
3379 [0x028] = 0x00,
3380
3381 [0x02a] = CISTPL_VERS_1, /* Level 1 Version */
3382 [0x02c] = 0x12, /* Tuple length = 23 bytes */
3383 [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
3384 [0x030] = 0x01, /* Minor Version = 1 */
3385 [0x032] = 'I',
3386 [0x034] = 'B',
3387 [0x036] = 'M',
3388 [0x038] = 0x00,
3389 [0x03a] = 'm',
3390 [0x03c] = 'i',
3391 [0x03e] = 'c',
3392 [0x040] = 'r',
3393 [0x042] = 'o',
3394 [0x044] = 'd',
3395 [0x046] = 'r',
3396 [0x048] = 'i',
3397 [0x04a] = 'v',
3398 [0x04c] = 'e',
3399 [0x04e] = 0x00,
3400 [0x050] = CISTPL_ENDMARK,
3401
3402 [0x052] = CISTPL_FUNCID, /* Function ID */
3403 [0x054] = 0x02, /* Tuple length = 2 bytes */
3404 [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
3405 [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
3406
3407 [0x05a] = CISTPL_FUNCE, /* Function Extension */
3408 [0x05c] = 0x02, /* Tuple length = 2 bytes */
3409 [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
3410 [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
3411
3412 [0x062] = CISTPL_FUNCE, /* Function Extension */
3413 [0x064] = 0x03, /* Tuple length = 3 bytes */
3414 [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
3415 [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
3416 [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
3417
3418 [0x06c] = CISTPL_CONFIG, /* Configuration */
3419 [0x06e] = 0x05, /* Tuple length = 5 bytes */
3420 [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
3421 [0x072] = 0x07, /* TPCC_LAST = 7 */
3422 [0x074] = 0x00, /* TPCC_RADR = 0200 */
3423 [0x076] = 0x02,
3424 [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
3425
3426 [0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3427 [0x07c] = 0x0b, /* Tuple length = 11 bytes */
3428 [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
3429 [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
3430 [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
3431 [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3432 [0x086] = 0x55, /* NomV: 5.0 V */
3433 [0x088] = 0x4d, /* MinV: 4.5 V */
3434 [0x08a] = 0x5d, /* MaxV: 5.5 V */
3435 [0x08c] = 0x4e, /* Peakl: 450 mA */
3436 [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
3437 [0x090] = 0x00, /* Window descriptor: Window length = 0 */
3438 [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
3439
3440 [0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3441 [0x096] = 0x06, /* Tuple length = 6 bytes */
3442 [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
3443 [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3444 [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3445 [0x09e] = 0xb5, /* NomV: 3.3 V */
3446 [0x0a0] = 0x1e,
3447 [0x0a2] = 0x3e, /* Peakl: 350 mA */
3448
3449 [0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3450 [0x0a6] = 0x0d, /* Tuple length = 13 bytes */
3451 [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
3452 [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3453 [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3454 [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3455 [0x0b0] = 0x55, /* NomV: 5.0 V */
3456 [0x0b2] = 0x4d, /* MinV: 4.5 V */
3457 [0x0b4] = 0x5d, /* MaxV: 5.5 V */
3458 [0x0b6] = 0x4e, /* Peakl: 450 mA */
3459 [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
3460 [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
3461 [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
3462 [0x0be] = 0xff, /* IRQ8..IRQ15 supported */
3463 [0x0c0] = 0x20, /* TPCE_MI = support power down mode */
3464
3465 [0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3466 [0x0c4] = 0x06, /* Tuple length = 6 bytes */
3467 [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
3468 [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3469 [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3470 [0x0cc] = 0xb5, /* NomV: 3.3 V */
3471 [0x0ce] = 0x1e,
3472 [0x0d0] = 0x3e, /* Peakl: 350 mA */
3473
3474 [0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3475 [0x0d4] = 0x12, /* Tuple length = 18 bytes */
3476 [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
3477 [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3478 [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3479 [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3480 [0x0de] = 0x55, /* NomV: 5.0 V */
3481 [0x0e0] = 0x4d, /* MinV: 4.5 V */
3482 [0x0e2] = 0x5d, /* MaxV: 5.5 V */
3483 [0x0e4] = 0x4e, /* Peakl: 450 mA */
3484 [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
3485 [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
3486 [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
3487 [0x0ec] = 0x01,
3488 [0x0ee] = 0x07, /* Address block length = 8 */
3489 [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
3490 [0x0f2] = 0x03,
3491 [0x0f4] = 0x01, /* Address block length = 2 */
3492 [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
3493 [0x0f8] = 0x20, /* TPCE_MI = support power down mode */
3494
3495 [0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3496 [0x0fc] = 0x06, /* Tuple length = 6 bytes */
3497 [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
3498 [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3499 [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3500 [0x104] = 0xb5, /* NomV: 3.3 V */
3501 [0x106] = 0x1e,
3502 [0x108] = 0x3e, /* Peakl: 350 mA */
3503
3504 [0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3505 [0x10c] = 0x12, /* Tuple length = 18 bytes */
3506 [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
3507 [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3508 [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3509 [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3510 [0x116] = 0x55, /* NomV: 5.0 V */
3511 [0x118] = 0x4d, /* MinV: 4.5 V */
3512 [0x11a] = 0x5d, /* MaxV: 5.5 V */
3513 [0x11c] = 0x4e, /* Peakl: 450 mA */
3514 [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
3515 [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
3516 [0x122] = 0x70, /* Field 1 address = 0x0170 */
3517 [0x124] = 0x01,
3518 [0x126] = 0x07, /* Address block length = 8 */
3519 [0x128] = 0x76, /* Field 2 address = 0x0376 */
3520 [0x12a] = 0x03,
3521 [0x12c] = 0x01, /* Address block length = 2 */
3522 [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
3523 [0x130] = 0x20, /* TPCE_MI = support power down mode */
3524
3525 [0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
3526 [0x134] = 0x06, /* Tuple length = 6 bytes */
3527 [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
3528 [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3529 [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3530 [0x13c] = 0xb5, /* NomV: 3.3 V */
3531 [0x13e] = 0x1e,
3532 [0x140] = 0x3e, /* Peakl: 350 mA */
3533
3534 [0x142] = CISTPL_NO_LINK, /* No Link */
3535 [0x144] = 0x00, /* Tuple length = 0 bytes */
3536
3537 [0x146] = CISTPL_END, /* Tuple End */
3538 };
3539
3540 static int dscm1xxxx_attach(void *opaque)
3541 {
3542 struct md_s *md = (struct md_s *) opaque;
3543 md->card.attr_read = md_attr_read;
3544 md->card.attr_write = md_attr_write;
3545 md->card.common_read = md_common_read;
3546 md->card.common_write = md_common_write;
3547 md->card.io_read = md_common_read;
3548 md->card.io_write = md_common_write;
3549
3550 md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
3551 md->io_base = 0x0;
3552
3553 md_reset(md);
3554 md_interrupt_update(md);
3555
3556 md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
3557 return 0;
3558 }
3559
3560 static int dscm1xxxx_detach(void *opaque)
3561 {
3562 struct md_s *md = (struct md_s *) opaque;
3563 md_reset(md);
3564 return 0;
3565 }
3566
3567 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv)
3568 {
3569 struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s));
3570 md->card.state = md;
3571 md->card.attach = dscm1xxxx_attach;
3572 md->card.detach = dscm1xxxx_detach;
3573 md->card.cis = dscm1xxxx_cis;
3574 md->card.cis_len = sizeof(dscm1xxxx_cis);
3575
3576 ide_init2(md->ide, bdrv, 0, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
3577 md->ide->is_cf = 1;
3578 md->ide->mdata_size = METADATA_SIZE;
3579 md->ide->mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
3580
3581 register_savevm("microdrive", md_iid ++, 0, md_save, md_load, md);
3582
3583 return &md->card;
3584 }
Qemu copy for testing