hw/intc/xilinx_intc.c

   1 /*
   2  * QEMU Xilinx OPB Interrupt Controller.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "hw/hw.h"
  27
  28 #define D(x)
  29
  30 #define R_ISR       0
  31 #define R_IPR       1
  32 #define R_IER       2
  33 #define R_IAR       3
  34 #define R_SIE       4
  35 #define R_CIE       5
  36 #define R_IVR       6
  37 #define R_MER       7
  38 #define R_MAX       8
  39
  40 struct xlx_pic
  41 {
  42     SysBusDevice busdev;
  43     MemoryRegion mmio;
  44     qemu_irq parent_irq;
  45
  46     /* Configuration reg chosen at synthesis-time. QEMU populates
  47        the bits at board-setup.  */
  48     uint32_t c_kind_of_intr;
  49
  50     /* Runtime control registers.  */
  51     uint32_t regs[R_MAX];
  52     /* state of the interrupt input pins */
  53     uint32_t irq_pin_state;
  54 };
  55
  56 static void update_irq(struct xlx_pic *p)
  57 {
  58     uint32_t i;
  59
  60     /* level triggered interrupt */
  61     if (p->regs[R_MER] & 2) {
  62         p->regs[R_ISR] |= p->irq_pin_state & ~p->c_kind_of_intr;
  63     }
  64
  65     /* Update the pending register.  */
  66     p->regs[R_IPR] = p->regs[R_ISR] & p->regs[R_IER];
  67
  68     /* Update the vector register.  */
  69     for (i = 0; i < 32; i++) {
  70         if (p->regs[R_IPR] & (1 << i))
  71             break;
  72     }
  73     if (i == 32)
  74         i = ~0;
  75
  76     p->regs[R_IVR] = i;
  77     qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
  78 }
  79
  80 static uint64_t
  81 pic_read(void *opaque, hwaddr addr, unsigned int size)
  82 {
  83     struct xlx_pic *p = opaque;
  84     uint32_t r = 0;
  85
  86     addr >>= 2;
  87     switch (addr)
  88     {
  89         default:
  90             if (addr < ARRAY_SIZE(p->regs))
  91                 r = p->regs[addr];
  92             break;
  93
  94     }
  95     D(printf("%s %x=%x\n", __func__, addr * 4, r));
  96     return r;
  97 }
  98
  99 static void
 100 pic_write(void *opaque, hwaddr addr,
 101           uint64_t val64, unsigned int size)
 102 {
 103     struct xlx_pic *p = opaque;
 104     uint32_t value = val64;
 105
 106     addr >>= 2;
 107     D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
 108     switch (addr)
 109     {
 110         case R_IAR:
 111             p->regs[R_ISR] &= ~value; /* ACK.  */
 112             break;
 113         case R_SIE:
 114             p->regs[R_IER] |= value;  /* Atomic set ie.  */
 115             break;
 116         case R_CIE:
 117             p->regs[R_IER] &= ~value; /* Atomic clear ie.  */
 118             break;
 119         case R_ISR:
 120             if ((p->regs[R_MER] & 2)) {
 121                 break;
 122             }
 123             /* fallthrough */
 124         default:
 125             if (addr < ARRAY_SIZE(p->regs))
 126                 p->regs[addr] = value;
 127             break;
 128     }
 129     update_irq(p);
 130 }
 131
 132 static const MemoryRegionOps pic_ops = {
 133     .read = pic_read,
 134     .write = pic_write,
 135     .endianness = DEVICE_NATIVE_ENDIAN,
 136     .valid = {
 137         .min_access_size = 4,
 138         .max_access_size = 4
 139     }
 140 };
 141
 142 static void irq_handler(void *opaque, int irq, int level)
 143 {
 144     struct xlx_pic *p = opaque;
 145
 146     /* edge triggered interrupt */
 147     if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
 148         p->regs[R_ISR] |= (level << irq);
 149     }
 150
 151     p->irq_pin_state &= ~(1 << irq);
 152     p->irq_pin_state |= level << irq;
 153     update_irq(p);
 154 }
 155
 156 static int xilinx_intc_init(SysBusDevice *dev)
 157 {
 158     struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev);
 159
 160     qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
 161     sysbus_init_irq(dev, &p->parent_irq);
 162
 163     memory_region_init_io(&p->mmio, &pic_ops, p, "xlnx.xps-intc", R_MAX * 4);
 164     sysbus_init_mmio(dev, &p->mmio);
 165     return 0;
 166 }
 167
 168 static Property xilinx_intc_properties[] = {
 169     DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
 170     DEFINE_PROP_END_OF_LIST(),
 171 };
 172
 173 static void xilinx_intc_class_init(ObjectClass *klass, void *data)
 174 {
 175     DeviceClass *dc = DEVICE_CLASS(klass);
 176     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 177
 178     k->init = xilinx_intc_init;
 179     dc->props = xilinx_intc_properties;
 180 }
 181
 182 static const TypeInfo xilinx_intc_info = {
 183     .name          = "xlnx.xps-intc",
 184     .parent        = TYPE_SYS_BUS_DEVICE,
 185     .instance_size = sizeof(struct xlx_pic),
 186     .class_init    = xilinx_intc_class_init,
 187 };
 188
 189 static void xilinx_intc_register_types(void)
 190 {
 191     type_register_static(&xilinx_intc_info);
 192 }
 193
 194 type_init(xilinx_intc_register_types)