2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Gerd Hoffmann <kraxel@redhat.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-timer.h"
25 #include "intel-hda.h"
26 #include "intel-hda-defs.h"
29 /* --------------------------------------------------------------------- */
32 static Property hda_props
[] = {
33 DEFINE_PROP_UINT32("cad", HDACodecDevice
, cad
, -1),
34 DEFINE_PROP_END_OF_LIST()
37 static struct BusInfo hda_codec_bus_info
= {
39 .size
= sizeof(HDACodecBus
),
43 void hda_codec_bus_init(DeviceState
*dev
, HDACodecBus
*bus
,
44 hda_codec_response_func response
,
45 hda_codec_xfer_func xfer
)
47 qbus_create_inplace(&bus
->qbus
, &hda_codec_bus_info
, dev
, NULL
);
48 bus
->response
= response
;
52 static int hda_codec_dev_init(DeviceState
*qdev
)
54 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, qdev
->parent_bus
);
55 HDACodecDevice
*dev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
56 HDACodecDeviceClass
*cdc
= HDA_CODEC_DEVICE_GET_CLASS(dev
);
59 dev
->cad
= bus
->next_cad
;
64 bus
->next_cad
= dev
->cad
+ 1;
65 return cdc
->init(dev
);
68 static int hda_codec_dev_exit(DeviceState
*qdev
)
70 HDACodecDevice
*dev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
71 HDACodecDeviceClass
*cdc
= HDA_CODEC_DEVICE_GET_CLASS(dev
);
79 HDACodecDevice
*hda_codec_find(HDACodecBus
*bus
, uint32_t cad
)
84 QTAILQ_FOREACH(qdev
, &bus
->qbus
.children
, sibling
) {
85 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
86 if (cdev
->cad
== cad
) {
93 void hda_codec_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
95 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
96 bus
->response(dev
, solicited
, response
);
99 bool hda_codec_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
100 uint8_t *buf
, uint32_t len
)
102 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
103 return bus
->xfer(dev
, stnr
, output
, buf
, len
);
106 /* --------------------------------------------------------------------- */
107 /* intel hda emulation */
109 typedef struct IntelHDAStream IntelHDAStream
;
110 typedef struct IntelHDAState IntelHDAState
;
111 typedef struct IntelHDAReg IntelHDAReg
;
119 struct IntelHDAStream
{
132 uint32_t bsize
, be
, bp
;
135 struct IntelHDAState
{
172 IntelHDAStream st
[8];
177 int64_t wall_base_ns
;
180 const IntelHDAReg
*last_reg
;
184 uint32_t repeat_count
;
192 const char *name
; /* register name */
193 uint32_t size
; /* size in bytes */
194 uint32_t reset
; /* reset value */
195 uint32_t wmask
; /* write mask */
196 uint32_t wclear
; /* write 1 to clear bits */
197 uint32_t offset
; /* location in IntelHDAState */
198 uint32_t shift
; /* byte access entries for dwords */
200 void (*whandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
);
201 void (*rhandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
);
204 static void intel_hda_reset(DeviceState
*dev
);
206 /* --------------------------------------------------------------------- */
208 static target_phys_addr_t
intel_hda_addr(uint32_t lbase
, uint32_t ubase
)
210 target_phys_addr_t addr
;
212 #if TARGET_PHYS_ADDR_BITS == 32
222 static void intel_hda_update_int_sts(IntelHDAState
*d
)
227 /* update controller status */
228 if (d
->rirb_sts
& ICH6_RBSTS_IRQ
) {
231 if (d
->rirb_sts
& ICH6_RBSTS_OVERRUN
) {
234 if (d
->state_sts
& d
->wake_en
) {
238 /* update stream status */
239 for (i
= 0; i
< 8; i
++) {
240 /* buffer completion interrupt */
241 if (d
->st
[i
].ctl
& (1 << 26)) {
246 /* update global status */
247 if (sts
& d
->int_ctl
) {
254 static void intel_hda_update_irq(IntelHDAState
*d
)
256 int msi
= d
->msi
&& msi_enabled(&d
->pci
);
259 intel_hda_update_int_sts(d
);
260 if (d
->int_sts
& (1 << 31) && d
->int_ctl
& (1 << 31)) {
265 dprint(d
, 2, "%s: level %d [%s]\n", __FUNCTION__
,
266 level
, msi
? "msi" : "intx");
269 msi_notify(&d
->pci
, 0);
272 qemu_set_irq(d
->pci
.irq
[0], level
);
276 static int intel_hda_send_command(IntelHDAState
*d
, uint32_t verb
)
278 uint32_t cad
, nid
, data
;
279 HDACodecDevice
*codec
;
280 HDACodecDeviceClass
*cdc
;
282 cad
= (verb
>> 28) & 0x0f;
283 if (verb
& (1 << 27)) {
284 /* indirect node addressing, not specified in HDA 1.0 */
285 dprint(d
, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__
);
288 nid
= (verb
>> 20) & 0x7f;
289 data
= verb
& 0xfffff;
291 codec
= hda_codec_find(&d
->codecs
, cad
);
293 dprint(d
, 1, "%s: addressed non-existing codec\n", __FUNCTION__
);
296 cdc
= HDA_CODEC_DEVICE_GET_CLASS(codec
);
297 cdc
->command(codec
, nid
, data
);
301 static void intel_hda_corb_run(IntelHDAState
*d
)
303 target_phys_addr_t addr
;
306 if (d
->ics
& ICH6_IRS_BUSY
) {
307 dprint(d
, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__
, d
->icw
);
308 intel_hda_send_command(d
, d
->icw
);
313 if (!(d
->corb_ctl
& ICH6_CORBCTL_RUN
)) {
314 dprint(d
, 2, "%s: !run\n", __FUNCTION__
);
317 if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
318 dprint(d
, 2, "%s: corb ring empty\n", __FUNCTION__
);
321 if (d
->rirb_count
== d
->rirb_cnt
) {
322 dprint(d
, 2, "%s: rirb count reached\n", __FUNCTION__
);
326 rp
= (d
->corb_rp
+ 1) & 0xff;
327 addr
= intel_hda_addr(d
->corb_lbase
, d
->corb_ubase
);
328 verb
= ldl_le_pci_dma(&d
->pci
, addr
+ 4*rp
);
331 dprint(d
, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__
, rp
, verb
);
332 intel_hda_send_command(d
, verb
);
336 static void intel_hda_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
338 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
339 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
340 target_phys_addr_t addr
;
343 if (d
->ics
& ICH6_IRS_BUSY
) {
344 dprint(d
, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
345 __FUNCTION__
, response
, dev
->cad
);
347 d
->ics
&= ~(ICH6_IRS_BUSY
| 0xf0);
348 d
->ics
|= (ICH6_IRS_VALID
| (dev
->cad
<< 4));
352 if (!(d
->rirb_ctl
& ICH6_RBCTL_DMA_EN
)) {
353 dprint(d
, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__
);
357 ex
= (solicited
? 0 : (1 << 4)) | dev
->cad
;
358 wp
= (d
->rirb_wp
+ 1) & 0xff;
359 addr
= intel_hda_addr(d
->rirb_lbase
, d
->rirb_ubase
);
360 stl_le_pci_dma(&d
->pci
, addr
+ 8*wp
, response
);
361 stl_le_pci_dma(&d
->pci
, addr
+ 8*wp
+ 4, ex
);
364 dprint(d
, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
365 __FUNCTION__
, wp
, response
, ex
);
368 if (d
->rirb_count
== d
->rirb_cnt
) {
369 dprint(d
, 2, "%s: rirb count reached (%d)\n", __FUNCTION__
, d
->rirb_count
);
370 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
371 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
372 intel_hda_update_irq(d
);
374 } else if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
375 dprint(d
, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__
,
376 d
->rirb_count
, d
->rirb_cnt
);
377 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
378 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
379 intel_hda_update_irq(d
);
384 static bool intel_hda_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
385 uint8_t *buf
, uint32_t len
)
387 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
388 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
389 target_phys_addr_t addr
;
390 uint32_t s
, copy
, left
;
394 st
= output
? d
->st
+ 4 : d
->st
;
395 for (s
= 0; s
< 4; s
++) {
396 if (stnr
== ((st
[s
].ctl
>> 20) & 0x0f)) {
404 if (st
->bpl
== NULL
) {
407 if (st
->ctl
& (1 << 26)) {
409 * Wait with the next DMA xfer until the guest
410 * has acked the buffer completion interrupt
418 if (copy
> st
->bsize
- st
->lpib
)
419 copy
= st
->bsize
- st
->lpib
;
420 if (copy
> st
->bpl
[st
->be
].len
- st
->bp
)
421 copy
= st
->bpl
[st
->be
].len
- st
->bp
;
423 dprint(d
, 3, "dma: entry %d, pos %d/%d, copy %d\n",
424 st
->be
, st
->bp
, st
->bpl
[st
->be
].len
, copy
);
426 pci_dma_rw(&d
->pci
, st
->bpl
[st
->be
].addr
+ st
->bp
, buf
, copy
, !output
);
432 if (st
->bpl
[st
->be
].len
== st
->bp
) {
433 /* bpl entry filled */
434 if (st
->bpl
[st
->be
].flags
& 0x01) {
439 if (st
->be
== st
->bentries
) {
440 /* bpl wrap around */
446 if (d
->dp_lbase
& 0x01) {
447 addr
= intel_hda_addr(d
->dp_lbase
& ~0x01, d
->dp_ubase
);
448 stl_le_pci_dma(&d
->pci
, addr
+ 8*s
, st
->lpib
);
450 dprint(d
, 3, "dma: --\n");
453 st
->ctl
|= (1 << 26); /* buffer completion interrupt */
454 intel_hda_update_irq(d
);
459 static void intel_hda_parse_bdl(IntelHDAState
*d
, IntelHDAStream
*st
)
461 target_phys_addr_t addr
;
465 addr
= intel_hda_addr(st
->bdlp_lbase
, st
->bdlp_ubase
);
466 st
->bentries
= st
->lvi
+1;
468 st
->bpl
= g_malloc(sizeof(bpl
) * st
->bentries
);
469 for (i
= 0; i
< st
->bentries
; i
++, addr
+= 16) {
470 pci_dma_read(&d
->pci
, addr
, buf
, 16);
471 st
->bpl
[i
].addr
= le64_to_cpu(*(uint64_t *)buf
);
472 st
->bpl
[i
].len
= le32_to_cpu(*(uint32_t *)(buf
+ 8));
473 st
->bpl
[i
].flags
= le32_to_cpu(*(uint32_t *)(buf
+ 12));
474 dprint(d
, 1, "bdl/%d: 0x%" PRIx64
" +0x%x, 0x%x\n",
475 i
, st
->bpl
[i
].addr
, st
->bpl
[i
].len
, st
->bpl
[i
].flags
);
484 static void intel_hda_notify_codecs(IntelHDAState
*d
, uint32_t stream
, bool running
, bool output
)
487 HDACodecDevice
*cdev
;
489 QTAILQ_FOREACH(qdev
, &d
->codecs
.qbus
.children
, sibling
) {
490 HDACodecDeviceClass
*cdc
;
492 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
493 cdc
= HDA_CODEC_DEVICE_GET_CLASS(cdev
);
495 cdc
->stream(cdev
, stream
, running
, output
);
500 /* --------------------------------------------------------------------- */
502 static void intel_hda_set_g_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
504 if ((d
->g_ctl
& ICH6_GCTL_RESET
) == 0) {
505 intel_hda_reset(&d
->pci
.qdev
);
509 static void intel_hda_set_wake_en(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
511 intel_hda_update_irq(d
);
514 static void intel_hda_set_state_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
516 intel_hda_update_irq(d
);
519 static void intel_hda_set_int_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
521 intel_hda_update_irq(d
);
524 static void intel_hda_get_wall_clk(IntelHDAState
*d
, const IntelHDAReg
*reg
)
528 ns
= qemu_get_clock_ns(vm_clock
) - d
->wall_base_ns
;
529 d
->wall_clk
= (uint32_t)(ns
* 24 / 1000); /* 24 MHz */
532 static void intel_hda_set_corb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
534 intel_hda_corb_run(d
);
537 static void intel_hda_set_corb_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
539 intel_hda_corb_run(d
);
542 static void intel_hda_set_rirb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
544 if (d
->rirb_wp
& ICH6_RIRBWP_RST
) {
549 static void intel_hda_set_rirb_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
551 intel_hda_update_irq(d
);
553 if ((old
& ICH6_RBSTS_IRQ
) && !(d
->rirb_sts
& ICH6_RBSTS_IRQ
)) {
554 /* cleared ICH6_RBSTS_IRQ */
556 intel_hda_corb_run(d
);
560 static void intel_hda_set_ics(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
562 if (d
->ics
& ICH6_IRS_BUSY
) {
563 intel_hda_corb_run(d
);
567 static void intel_hda_set_st_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
569 bool output
= reg
->stream
>= 4;
570 IntelHDAStream
*st
= d
->st
+ reg
->stream
;
572 if (st
->ctl
& 0x01) {
574 dprint(d
, 1, "st #%d: reset\n", reg
->stream
);
577 if ((st
->ctl
& 0x02) != (old
& 0x02)) {
578 uint32_t stnr
= (st
->ctl
>> 20) & 0x0f;
579 /* run bit flipped */
580 if (st
->ctl
& 0x02) {
582 dprint(d
, 1, "st #%d: start %d (ring buf %d bytes)\n",
583 reg
->stream
, stnr
, st
->cbl
);
584 intel_hda_parse_bdl(d
, st
);
585 intel_hda_notify_codecs(d
, stnr
, true, output
);
588 dprint(d
, 1, "st #%d: stop %d\n", reg
->stream
, stnr
);
589 intel_hda_notify_codecs(d
, stnr
, false, output
);
592 intel_hda_update_irq(d
);
595 /* --------------------------------------------------------------------- */
597 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
599 static const struct IntelHDAReg regtab
[] = {
601 [ ICH6_REG_GCAP
] = {
606 [ ICH6_REG_VMIN
] = {
610 [ ICH6_REG_VMAJ
] = {
615 [ ICH6_REG_OUTPAY
] = {
620 [ ICH6_REG_INPAY
] = {
625 [ ICH6_REG_GCTL
] = {
629 .offset
= offsetof(IntelHDAState
, g_ctl
),
630 .whandler
= intel_hda_set_g_ctl
,
632 [ ICH6_REG_WAKEEN
] = {
636 .offset
= offsetof(IntelHDAState
, wake_en
),
637 .whandler
= intel_hda_set_wake_en
,
639 [ ICH6_REG_STATESTS
] = {
644 .offset
= offsetof(IntelHDAState
, state_sts
),
645 .whandler
= intel_hda_set_state_sts
,
649 [ ICH6_REG_INTCTL
] = {
653 .offset
= offsetof(IntelHDAState
, int_ctl
),
654 .whandler
= intel_hda_set_int_ctl
,
656 [ ICH6_REG_INTSTS
] = {
660 .wclear
= 0xc00000ff,
661 .offset
= offsetof(IntelHDAState
, int_sts
),
665 [ ICH6_REG_WALLCLK
] = {
668 .offset
= offsetof(IntelHDAState
, wall_clk
),
669 .rhandler
= intel_hda_get_wall_clk
,
671 [ ICH6_REG_WALLCLK
+ 0x2000 ] = {
672 .name
= "WALLCLK(alias)",
674 .offset
= offsetof(IntelHDAState
, wall_clk
),
675 .rhandler
= intel_hda_get_wall_clk
,
679 [ ICH6_REG_CORBLBASE
] = {
683 .offset
= offsetof(IntelHDAState
, corb_lbase
),
685 [ ICH6_REG_CORBUBASE
] = {
689 .offset
= offsetof(IntelHDAState
, corb_ubase
),
691 [ ICH6_REG_CORBWP
] = {
695 .offset
= offsetof(IntelHDAState
, corb_wp
),
696 .whandler
= intel_hda_set_corb_wp
,
698 [ ICH6_REG_CORBRP
] = {
702 .offset
= offsetof(IntelHDAState
, corb_rp
),
704 [ ICH6_REG_CORBCTL
] = {
708 .offset
= offsetof(IntelHDAState
, corb_ctl
),
709 .whandler
= intel_hda_set_corb_ctl
,
711 [ ICH6_REG_CORBSTS
] = {
716 .offset
= offsetof(IntelHDAState
, corb_sts
),
718 [ ICH6_REG_CORBSIZE
] = {
722 .offset
= offsetof(IntelHDAState
, corb_size
),
724 [ ICH6_REG_RIRBLBASE
] = {
728 .offset
= offsetof(IntelHDAState
, rirb_lbase
),
730 [ ICH6_REG_RIRBUBASE
] = {
734 .offset
= offsetof(IntelHDAState
, rirb_ubase
),
736 [ ICH6_REG_RIRBWP
] = {
740 .offset
= offsetof(IntelHDAState
, rirb_wp
),
741 .whandler
= intel_hda_set_rirb_wp
,
743 [ ICH6_REG_RINTCNT
] = {
747 .offset
= offsetof(IntelHDAState
, rirb_cnt
),
749 [ ICH6_REG_RIRBCTL
] = {
753 .offset
= offsetof(IntelHDAState
, rirb_ctl
),
755 [ ICH6_REG_RIRBSTS
] = {
760 .offset
= offsetof(IntelHDAState
, rirb_sts
),
761 .whandler
= intel_hda_set_rirb_sts
,
763 [ ICH6_REG_RIRBSIZE
] = {
767 .offset
= offsetof(IntelHDAState
, rirb_size
),
770 [ ICH6_REG_DPLBASE
] = {
774 .offset
= offsetof(IntelHDAState
, dp_lbase
),
776 [ ICH6_REG_DPUBASE
] = {
780 .offset
= offsetof(IntelHDAState
, dp_ubase
),
787 .offset
= offsetof(IntelHDAState
, icw
),
792 .offset
= offsetof(IntelHDAState
, irr
),
799 .offset
= offsetof(IntelHDAState
, ics
),
800 .whandler
= intel_hda_set_ics
,
803 #define HDA_STREAM(_t, _i) \
804 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
806 .name = _t stringify(_i) " CTL", \
808 .wmask = 0x1cff001f, \
809 .offset = offsetof(IntelHDAState, st[_i].ctl), \
810 .whandler = intel_hda_set_st_ctl, \
812 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
814 .name = _t stringify(_i) " CTL(stnr)", \
817 .wmask = 0x00ff0000, \
818 .offset = offsetof(IntelHDAState, st[_i].ctl), \
819 .whandler = intel_hda_set_st_ctl, \
821 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
823 .name = _t stringify(_i) " CTL(sts)", \
826 .wmask = 0x1c000000, \
827 .wclear = 0x1c000000, \
828 .offset = offsetof(IntelHDAState, st[_i].ctl), \
829 .whandler = intel_hda_set_st_ctl, \
831 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
833 .name = _t stringify(_i) " LPIB", \
835 .offset = offsetof(IntelHDAState, st[_i].lpib), \
837 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
839 .name = _t stringify(_i) " LPIB(alias)", \
841 .offset = offsetof(IntelHDAState, st[_i].lpib), \
843 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
845 .name = _t stringify(_i) " CBL", \
847 .wmask = 0xffffffff, \
848 .offset = offsetof(IntelHDAState, st[_i].cbl), \
850 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
852 .name = _t stringify(_i) " LVI", \
855 .offset = offsetof(IntelHDAState, st[_i].lvi), \
857 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
859 .name = _t stringify(_i) " FIFOS", \
861 .reset = HDA_BUFFER_SIZE, \
863 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
865 .name = _t stringify(_i) " FMT", \
868 .offset = offsetof(IntelHDAState, st[_i].fmt), \
870 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
872 .name = _t stringify(_i) " BDLPL", \
874 .wmask = 0xffffff80, \
875 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
877 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
879 .name = _t stringify(_i) " BDLPU", \
881 .wmask = 0xffffffff, \
882 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
897 static const IntelHDAReg
*intel_hda_reg_find(IntelHDAState
*d
, target_phys_addr_t addr
)
899 const IntelHDAReg
*reg
;
901 if (addr
>= sizeof(regtab
)/sizeof(regtab
[0])) {
905 if (reg
->name
== NULL
) {
911 dprint(d
, 1, "unknown register, addr 0x%x\n", (int) addr
);
915 static uint32_t *intel_hda_reg_addr(IntelHDAState
*d
, const IntelHDAReg
*reg
)
917 uint8_t *addr
= (void*)d
;
920 return (uint32_t*)addr
;
923 static void intel_hda_reg_write(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t val
,
934 time_t now
= time(NULL
);
935 if (d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== val
) {
937 if (d
->last_sec
!= now
) {
938 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
943 if (d
->repeat_count
) {
944 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
946 dprint(d
, 2, "write %-16s: 0x%x (%x)\n", reg
->name
, val
, wmask
);
954 assert(reg
->offset
!= 0);
956 addr
= intel_hda_reg_addr(d
, reg
);
961 wmask
<<= reg
->shift
;
965 *addr
|= wmask
& val
;
966 *addr
&= ~(val
& reg
->wclear
);
969 reg
->whandler(d
, reg
, old
);
973 static uint32_t intel_hda_reg_read(IntelHDAState
*d
, const IntelHDAReg
*reg
,
983 reg
->rhandler(d
, reg
);
986 if (reg
->offset
== 0) {
987 /* constant read-only register */
990 addr
= intel_hda_reg_addr(d
, reg
);
998 time_t now
= time(NULL
);
999 if (!d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== ret
) {
1001 if (d
->last_sec
!= now
) {
1002 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1004 d
->repeat_count
= 0;
1007 if (d
->repeat_count
) {
1008 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1010 dprint(d
, 2, "read %-16s: 0x%x (%x)\n", reg
->name
, ret
, rmask
);
1015 d
->repeat_count
= 0;
1021 static void intel_hda_regs_reset(IntelHDAState
*d
)
1026 for (i
= 0; i
< sizeof(regtab
)/sizeof(regtab
[0]); i
++) {
1027 if (regtab
[i
].name
== NULL
) {
1030 if (regtab
[i
].offset
== 0) {
1033 addr
= intel_hda_reg_addr(d
, regtab
+ i
);
1034 *addr
= regtab
[i
].reset
;
1038 /* --------------------------------------------------------------------- */
1040 static void intel_hda_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1042 IntelHDAState
*d
= opaque
;
1043 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1045 intel_hda_reg_write(d
, reg
, val
, 0xff);
1048 static void intel_hda_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1050 IntelHDAState
*d
= opaque
;
1051 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1053 intel_hda_reg_write(d
, reg
, val
, 0xffff);
1056 static void intel_hda_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1058 IntelHDAState
*d
= opaque
;
1059 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1061 intel_hda_reg_write(d
, reg
, val
, 0xffffffff);
1064 static uint32_t intel_hda_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1066 IntelHDAState
*d
= opaque
;
1067 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1069 return intel_hda_reg_read(d
, reg
, 0xff);
1072 static uint32_t intel_hda_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1074 IntelHDAState
*d
= opaque
;
1075 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1077 return intel_hda_reg_read(d
, reg
, 0xffff);
1080 static uint32_t intel_hda_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1082 IntelHDAState
*d
= opaque
;
1083 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1085 return intel_hda_reg_read(d
, reg
, 0xffffffff);
1088 static const MemoryRegionOps intel_hda_mmio_ops
= {
1091 intel_hda_mmio_readb
,
1092 intel_hda_mmio_readw
,
1093 intel_hda_mmio_readl
,
1096 intel_hda_mmio_writeb
,
1097 intel_hda_mmio_writew
,
1098 intel_hda_mmio_writel
,
1101 .endianness
= DEVICE_NATIVE_ENDIAN
,
1104 /* --------------------------------------------------------------------- */
1106 static void intel_hda_reset(DeviceState
*dev
)
1108 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
.qdev
, dev
);
1110 HDACodecDevice
*cdev
;
1112 intel_hda_regs_reset(d
);
1113 d
->wall_base_ns
= qemu_get_clock_ns(vm_clock
);
1116 QTAILQ_FOREACH(qdev
, &d
->codecs
.qbus
.children
, sibling
) {
1117 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
1118 device_reset(DEVICE(cdev
));
1119 d
->state_sts
|= (1 << cdev
->cad
);
1121 intel_hda_update_irq(d
);
1124 static int intel_hda_init(PCIDevice
*pci
)
1126 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1127 uint8_t *conf
= d
->pci
.config
;
1129 d
->name
= object_get_typename(OBJECT(d
));
1131 pci_config_set_interrupt_pin(conf
, 1);
1133 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1136 memory_region_init_io(&d
->mmio
, &intel_hda_mmio_ops
, d
,
1137 "intel-hda", 0x4000);
1138 pci_register_bar(&d
->pci
, 0, 0, &d
->mmio
);
1140 msi_init(&d
->pci
, 0x50, 1, true, false);
1143 hda_codec_bus_init(&d
->pci
.qdev
, &d
->codecs
,
1144 intel_hda_response
, intel_hda_xfer
);
1149 static int intel_hda_exit(PCIDevice
*pci
)
1151 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1153 msi_uninit(&d
->pci
);
1154 memory_region_destroy(&d
->mmio
);
1158 static void intel_hda_write_config(PCIDevice
*pci
, uint32_t addr
,
1159 uint32_t val
, int len
)
1161 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1163 pci_default_write_config(pci
, addr
, val
, len
);
1165 msi_write_config(pci
, addr
, val
, len
);
1169 static int intel_hda_post_load(void *opaque
, int version
)
1171 IntelHDAState
* d
= opaque
;
1174 dprint(d
, 1, "%s\n", __FUNCTION__
);
1175 for (i
= 0; i
< ARRAY_SIZE(d
->st
); i
++) {
1176 if (d
->st
[i
].ctl
& 0x02) {
1177 intel_hda_parse_bdl(d
, &d
->st
[i
]);
1180 intel_hda_update_irq(d
);
1184 static const VMStateDescription vmstate_intel_hda_stream
= {
1185 .name
= "intel-hda-stream",
1187 .fields
= (VMStateField
[]) {
1188 VMSTATE_UINT32(ctl
, IntelHDAStream
),
1189 VMSTATE_UINT32(lpib
, IntelHDAStream
),
1190 VMSTATE_UINT32(cbl
, IntelHDAStream
),
1191 VMSTATE_UINT32(lvi
, IntelHDAStream
),
1192 VMSTATE_UINT32(fmt
, IntelHDAStream
),
1193 VMSTATE_UINT32(bdlp_lbase
, IntelHDAStream
),
1194 VMSTATE_UINT32(bdlp_ubase
, IntelHDAStream
),
1195 VMSTATE_END_OF_LIST()
1199 static const VMStateDescription vmstate_intel_hda
= {
1200 .name
= "intel-hda",
1202 .post_load
= intel_hda_post_load
,
1203 .fields
= (VMStateField
[]) {
1204 VMSTATE_PCI_DEVICE(pci
, IntelHDAState
),
1207 VMSTATE_UINT32(g_ctl
, IntelHDAState
),
1208 VMSTATE_UINT32(wake_en
, IntelHDAState
),
1209 VMSTATE_UINT32(state_sts
, IntelHDAState
),
1210 VMSTATE_UINT32(int_ctl
, IntelHDAState
),
1211 VMSTATE_UINT32(int_sts
, IntelHDAState
),
1212 VMSTATE_UINT32(wall_clk
, IntelHDAState
),
1213 VMSTATE_UINT32(corb_lbase
, IntelHDAState
),
1214 VMSTATE_UINT32(corb_ubase
, IntelHDAState
),
1215 VMSTATE_UINT32(corb_rp
, IntelHDAState
),
1216 VMSTATE_UINT32(corb_wp
, IntelHDAState
),
1217 VMSTATE_UINT32(corb_ctl
, IntelHDAState
),
1218 VMSTATE_UINT32(corb_sts
, IntelHDAState
),
1219 VMSTATE_UINT32(corb_size
, IntelHDAState
),
1220 VMSTATE_UINT32(rirb_lbase
, IntelHDAState
),
1221 VMSTATE_UINT32(rirb_ubase
, IntelHDAState
),
1222 VMSTATE_UINT32(rirb_wp
, IntelHDAState
),
1223 VMSTATE_UINT32(rirb_cnt
, IntelHDAState
),
1224 VMSTATE_UINT32(rirb_ctl
, IntelHDAState
),
1225 VMSTATE_UINT32(rirb_sts
, IntelHDAState
),
1226 VMSTATE_UINT32(rirb_size
, IntelHDAState
),
1227 VMSTATE_UINT32(dp_lbase
, IntelHDAState
),
1228 VMSTATE_UINT32(dp_ubase
, IntelHDAState
),
1229 VMSTATE_UINT32(icw
, IntelHDAState
),
1230 VMSTATE_UINT32(irr
, IntelHDAState
),
1231 VMSTATE_UINT32(ics
, IntelHDAState
),
1232 VMSTATE_STRUCT_ARRAY(st
, IntelHDAState
, 8, 0,
1233 vmstate_intel_hda_stream
,
1236 /* additional state info */
1237 VMSTATE_UINT32(rirb_count
, IntelHDAState
),
1238 VMSTATE_INT64(wall_base_ns
, IntelHDAState
),
1240 VMSTATE_END_OF_LIST()
1244 static Property intel_hda_properties
[] = {
1245 DEFINE_PROP_UINT32("debug", IntelHDAState
, debug
, 0),
1246 DEFINE_PROP_UINT32("msi", IntelHDAState
, msi
, 1),
1247 DEFINE_PROP_END_OF_LIST(),
1250 static void intel_hda_class_init(ObjectClass
*klass
, void *data
)
1252 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1253 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1255 k
->init
= intel_hda_init
;
1256 k
->exit
= intel_hda_exit
;
1257 k
->config_write
= intel_hda_write_config
;
1258 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1259 k
->device_id
= 0x2668;
1261 k
->class_id
= PCI_CLASS_MULTIMEDIA_HD_AUDIO
;
1262 dc
->desc
= "Intel HD Audio Controller";
1263 dc
->reset
= intel_hda_reset
;
1264 dc
->vmsd
= &vmstate_intel_hda
;
1265 dc
->props
= intel_hda_properties
;
1268 static TypeInfo intel_hda_info
= {
1269 .name
= "intel-hda",
1270 .parent
= TYPE_PCI_DEVICE
,
1271 .instance_size
= sizeof(IntelHDAState
),
1272 .class_init
= intel_hda_class_init
,
1275 static void hda_codec_device_class_init(ObjectClass
*klass
, void *data
)
1277 DeviceClass
*k
= DEVICE_CLASS(klass
);
1278 k
->init
= hda_codec_dev_init
;
1279 k
->exit
= hda_codec_dev_exit
;
1280 k
->bus_info
= &hda_codec_bus_info
;
1283 static TypeInfo hda_codec_device_type_info
= {
1284 .name
= TYPE_HDA_CODEC_DEVICE
,
1285 .parent
= TYPE_DEVICE
,
1286 .instance_size
= sizeof(HDACodecDevice
),
1288 .class_size
= sizeof(HDACodecDeviceClass
),
1289 .class_init
= hda_codec_device_class_init
,
1292 static void intel_hda_register_types(void)
1294 type_register_static(&intel_hda_info
);
1295 type_register_static(&hda_codec_device_type_info
);
1298 type_init(intel_hda_register_types
)
1301 * create intel hda controller with codec attached to it,
1302 * so '-soundhw hda' works.
1304 int intel_hda_and_codec_init(PCIBus
*bus
)
1306 PCIDevice
*controller
;
1310 controller
= pci_create_simple(bus
, -1, "intel-hda");
1311 hdabus
= QLIST_FIRST(&controller
->qdev
.child_bus
);
1312 codec
= qdev_create(hdabus
, "hda-duplex");
1313 qdev_init_nofail(codec
);