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1 /*
2 * QEMU SPARC iommu emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25
26 /* debug iommu */
27 //#define DEBUG_IOMMU
28
29 #ifdef DEBUG_IOMMU
30 #define DPRINTF(fmt, args...) \
31 do { printf("IOMMU: " fmt , ##args); } while (0)
32 #else
33 #define DPRINTF(fmt, args...)
34 #endif
35
36 #define IOMMU_NREGS (3*4096/4)
37 #define IOMMU_CTRL (0x0000 >> 2)
38 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
39 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
40 #define IOMMU_VERSION 0x04000000
41 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
42 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
43 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
44 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
45 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
46 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
47 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
48 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
49 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
50 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
51 #define IOMMU_CTRL_MASK 0x0000001d
52
53 #define IOMMU_BASE (0x0004 >> 2)
54 #define IOMMU_BASE_MASK 0x07fffc00
55
56 #define IOMMU_TLBFLUSH (0x0014 >> 2)
57 #define IOMMU_TLBFLUSH_MASK 0xffffffff
58
59 #define IOMMU_PGFLUSH (0x0018 >> 2)
60 #define IOMMU_PGFLUSH_MASK 0xffffffff
61
62 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
63 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
64 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
65 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
66 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
67 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
68 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
69 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
70 produced by this device as pure
71 physical. */
72 #define IOMMU_SBCFG_MASK 0x00010003
73
74 #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
75 #define IOMMU_ARBEN_MASK 0x001f0000
76 #define IOMMU_MID 0x00000008
77
78 /* The format of an iopte in the page tables */
79 #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
80 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
81 #define IOPTE_WRITE 0x00000004 /* Writeable */
82 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
83 #define IOPTE_WAZ 0x00000001 /* Write as zeros */
84
85 #define PAGE_SHIFT 12
86 #define PAGE_SIZE (1 << PAGE_SHIFT)
87 #define PAGE_MASK (PAGE_SIZE - 1)
88
89 typedef struct IOMMUState {
90 uint32_t addr;
91 uint32_t regs[IOMMU_NREGS];
92 uint32_t iostart;
93 } IOMMUState;
94
95 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
96 {
97 IOMMUState *s = opaque;
98 uint32_t saddr;
99
100 saddr = (addr - s->addr) >> 2;
101 switch (saddr) {
102 default:
103 DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]);
104 return s->regs[saddr];
105 break;
106 }
107 return 0;
108 }
109
110 static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
111 {
112 IOMMUState *s = opaque;
113 uint32_t saddr;
114
115 saddr = (addr - s->addr) >> 2;
116 DPRINTF("write reg[%d] = %x\n", saddr, val);
117 switch (saddr) {
118 case IOMMU_CTRL:
119 switch (val & IOMMU_CTRL_RNGE) {
120 case IOMMU_RNGE_16MB:
121 s->iostart = 0xff000000;
122 break;
123 case IOMMU_RNGE_32MB:
124 s->iostart = 0xfe000000;
125 break;
126 case IOMMU_RNGE_64MB:
127 s->iostart = 0xfc000000;
128 break;
129 case IOMMU_RNGE_128MB:
130 s->iostart = 0xf8000000;
131 break;
132 case IOMMU_RNGE_256MB:
133 s->iostart = 0xf0000000;
134 break;
135 case IOMMU_RNGE_512MB:
136 s->iostart = 0xe0000000;
137 break;
138 case IOMMU_RNGE_1GB:
139 s->iostart = 0xc0000000;
140 break;
141 default:
142 case IOMMU_RNGE_2GB:
143 s->iostart = 0x80000000;
144 break;
145 }
146 DPRINTF("iostart = %x\n", s->iostart);
147 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
148 break;
149 case IOMMU_BASE:
150 s->regs[saddr] = val & IOMMU_BASE_MASK;
151 break;
152 case IOMMU_TLBFLUSH:
153 DPRINTF("tlb flush %x\n", val);
154 s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
155 break;
156 case IOMMU_PGFLUSH:
157 DPRINTF("page flush %x\n", val);
158 s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
159 break;
160 case IOMMU_SBCFG0:
161 case IOMMU_SBCFG1:
162 case IOMMU_SBCFG2:
163 case IOMMU_SBCFG3:
164 s->regs[saddr] = val & IOMMU_SBCFG_MASK;
165 break;
166 case IOMMU_ARBEN:
167 // XXX implement SBus probing: fault when reading unmapped
168 // addresses, fault cause and address stored to MMU/IOMMU
169 s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
170 break;
171 default:
172 s->regs[saddr] = val;
173 break;
174 }
175 }
176
177 static CPUReadMemoryFunc *iommu_mem_read[3] = {
178 iommu_mem_readw,
179 iommu_mem_readw,
180 iommu_mem_readw,
181 };
182
183 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
184 iommu_mem_writew,
185 iommu_mem_writew,
186 iommu_mem_writew,
187 };
188
189 uint32_t iommu_translate_local(void *opaque, uint32_t addr)
190 {
191 IOMMUState *s = opaque;
192 uint32_t iopte, pa, tmppte;
193
194 iopte = s->regs[1] << 4;
195 addr &= ~s->iostart;
196 iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
197 pa = ldl_phys(iopte);
198 tmppte = pa;
199 pa = ((pa & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
200 DPRINTF("xlate dva %x => pa %x (iopte[%x] = %x)\n", addr, pa, iopte, tmppte);
201 return pa;
202 }
203
204 static void iommu_save(QEMUFile *f, void *opaque)
205 {
206 IOMMUState *s = opaque;
207 int i;
208
209 qemu_put_be32s(f, &s->addr);
210 for (i = 0; i < IOMMU_NREGS; i++)
211 qemu_put_be32s(f, &s->regs[i]);
212 qemu_put_be32s(f, &s->iostart);
213 }
214
215 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
216 {
217 IOMMUState *s = opaque;
218 int i;
219
220 if (version_id != 1)
221 return -EINVAL;
222
223 qemu_get_be32s(f, &s->addr);
224 for (i = 0; i < IOMMU_NREGS; i++)
225 qemu_put_be32s(f, &s->regs[i]);
226 qemu_get_be32s(f, &s->iostart);
227
228 return 0;
229 }
230
231 static void iommu_reset(void *opaque)
232 {
233 IOMMUState *s = opaque;
234
235 memset(s->regs, 0, IOMMU_NREGS * 4);
236 s->iostart = 0;
237 s->regs[0] = IOMMU_VERSION;
238 }
239
240 void *iommu_init(uint32_t addr)
241 {
242 IOMMUState *s;
243 int iommu_io_memory;
244
245 s = qemu_mallocz(sizeof(IOMMUState));
246 if (!s)
247 return NULL;
248
249 s->addr = addr;
250
251 iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
252 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
253
254 register_savevm("iommu", addr, 1, iommu_save, iommu_load, s);
255 qemu_register_reset(iommu_reset, s);
256 return s;
257 }
258