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1 /*
2 * QEMU SPARC iommu emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25
26 /* debug iommu */
27 //#define DEBUG_IOMMU
28
29 #ifdef DEBUG_IOMMU
30 #define DPRINTF(fmt, args...) \
31 do { printf("IOMMU: " fmt , ##args); } while (0)
32 #else
33 #define DPRINTF(fmt, args...)
34 #endif
35
36 #define IOMMU_NREGS (3*4096/4)
37 #define IOMMU_CTRL (0x0000 >> 2)
38 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
39 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
40 #define IOMMU_VERSION 0x04000000
41 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
42 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
43 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
44 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
45 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
46 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
47 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
48 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
49 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
50 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
51 #define IOMMU_CTRL_MASK 0x0000001d
52
53 #define IOMMU_BASE (0x0004 >> 2)
54 #define IOMMU_BASE_MASK 0x07fffc00
55
56 #define IOMMU_TLBFLUSH (0x0014 >> 2)
57 #define IOMMU_TLBFLUSH_MASK 0xffffffff
58
59 #define IOMMU_PGFLUSH (0x0018 >> 2)
60 #define IOMMU_PGFLUSH_MASK 0xffffffff
61
62 #define IOMMU_AFSR (0x1000 >> 2)
63 #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
64 #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
65 #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
66 #define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
67 #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
68 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
69 #define IOMMU_AFSR_RESV 0x00f00000 /* Reserved, forced to 0x8 by hardware */
70 #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
71 #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
72 #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
73
74 #define IOMMU_AFAR (0x1004 >> 2)
75
76 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
77 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
78 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
79 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
80 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
81 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
82 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
83 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
84 produced by this device as pure
85 physical. */
86 #define IOMMU_SBCFG_MASK 0x00010003
87
88 #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
89 #define IOMMU_ARBEN_MASK 0x001f0000
90 #define IOMMU_MID 0x00000008
91
92 /* The format of an iopte in the page tables */
93 #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
94 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
95 #define IOPTE_WRITE 0x00000004 /* Writeable */
96 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
97 #define IOPTE_WAZ 0x00000001 /* Write as zeros */
98
99 #define PAGE_SHIFT 12
100 #define PAGE_SIZE (1 << PAGE_SHIFT)
101 #define PAGE_MASK (PAGE_SIZE - 1)
102
103 typedef struct IOMMUState {
104 target_phys_addr_t addr;
105 uint32_t regs[IOMMU_NREGS];
106 target_phys_addr_t iostart;
107 } IOMMUState;
108
109 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
110 {
111 IOMMUState *s = opaque;
112 target_phys_addr_t saddr;
113
114 saddr = (addr - s->addr) >> 2;
115 switch (saddr) {
116 default:
117 DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
118 return s->regs[saddr];
119 break;
120 }
121 return 0;
122 }
123
124 static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
125 {
126 IOMMUState *s = opaque;
127 target_phys_addr_t saddr;
128
129 saddr = (addr - s->addr) >> 2;
130 DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
131 switch (saddr) {
132 case IOMMU_CTRL:
133 switch (val & IOMMU_CTRL_RNGE) {
134 case IOMMU_RNGE_16MB:
135 s->iostart = 0xffffffffff000000ULL;
136 break;
137 case IOMMU_RNGE_32MB:
138 s->iostart = 0xfffffffffe000000ULL;
139 break;
140 case IOMMU_RNGE_64MB:
141 s->iostart = 0xfffffffffc000000ULL;
142 break;
143 case IOMMU_RNGE_128MB:
144 s->iostart = 0xfffffffff8000000ULL;
145 break;
146 case IOMMU_RNGE_256MB:
147 s->iostart = 0xfffffffff0000000ULL;
148 break;
149 case IOMMU_RNGE_512MB:
150 s->iostart = 0xffffffffe0000000ULL;
151 break;
152 case IOMMU_RNGE_1GB:
153 s->iostart = 0xffffffffc0000000ULL;
154 break;
155 default:
156 case IOMMU_RNGE_2GB:
157 s->iostart = 0xffffffff80000000ULL;
158 break;
159 }
160 DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
161 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
162 break;
163 case IOMMU_BASE:
164 s->regs[saddr] = val & IOMMU_BASE_MASK;
165 break;
166 case IOMMU_TLBFLUSH:
167 DPRINTF("tlb flush %x\n", val);
168 s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
169 break;
170 case IOMMU_PGFLUSH:
171 DPRINTF("page flush %x\n", val);
172 s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
173 break;
174 case IOMMU_SBCFG0:
175 case IOMMU_SBCFG1:
176 case IOMMU_SBCFG2:
177 case IOMMU_SBCFG3:
178 s->regs[saddr] = val & IOMMU_SBCFG_MASK;
179 break;
180 case IOMMU_ARBEN:
181 // XXX implement SBus probing: fault when reading unmapped
182 // addresses, fault cause and address stored to MMU/IOMMU
183 s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
184 break;
185 default:
186 s->regs[saddr] = val;
187 break;
188 }
189 }
190
191 static CPUReadMemoryFunc *iommu_mem_read[3] = {
192 iommu_mem_readw,
193 iommu_mem_readw,
194 iommu_mem_readw,
195 };
196
197 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
198 iommu_mem_writew,
199 iommu_mem_writew,
200 iommu_mem_writew,
201 };
202
203 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
204 {
205 uint32_t iopte, ret;
206 #ifdef DEBUG_IOMMU
207 target_phys_addr_t pa = addr;
208 #endif
209
210 iopte = s->regs[IOMMU_BASE] << 4;
211 addr &= ~s->iostart;
212 iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
213 ret = ldl_phys(iopte);
214 DPRINTF("get flags addr " TARGET_FMT_plx " => pte %x, *ptes = %x\n", pa,
215 iopte, ret);
216
217 return ret;
218 }
219
220 static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
221 target_phys_addr_t addr,
222 uint32_t pte)
223 {
224 uint32_t tmppte;
225 target_phys_addr_t pa;
226
227 tmppte = pte;
228 pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
229 DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
230 " (iopte = %x)\n", addr, pa, tmppte);
231
232 return pa;
233 }
234
235 static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write)
236 {
237 DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
238 s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | (8 << 20) |
239 IOMMU_AFSR_FAV;
240 if (!is_write)
241 s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
242 s->regs[IOMMU_AFAR] = addr;
243 }
244
245 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
246 uint8_t *buf, int len, int is_write)
247 {
248 int l;
249 uint32_t flags;
250 target_phys_addr_t page, phys_addr;
251
252 while (len > 0) {
253 page = addr & TARGET_PAGE_MASK;
254 l = (page + TARGET_PAGE_SIZE) - addr;
255 if (l > len)
256 l = len;
257 flags = iommu_page_get_flags(opaque, page);
258 if (!(flags & IOPTE_VALID)) {
259 iommu_bad_addr(opaque, page, is_write);
260 return;
261 }
262 phys_addr = iommu_translate_pa(opaque, addr, flags);
263 if (is_write) {
264 if (!(flags & IOPTE_WRITE)) {
265 iommu_bad_addr(opaque, page, is_write);
266 return;
267 }
268 cpu_physical_memory_write(phys_addr, buf, len);
269 } else {
270 cpu_physical_memory_read(phys_addr, buf, len);
271 }
272 len -= l;
273 buf += l;
274 addr += l;
275 }
276 }
277
278 static void iommu_save(QEMUFile *f, void *opaque)
279 {
280 IOMMUState *s = opaque;
281 int i;
282
283 for (i = 0; i < IOMMU_NREGS; i++)
284 qemu_put_be32s(f, &s->regs[i]);
285 qemu_put_be64s(f, &s->iostart);
286 }
287
288 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
289 {
290 IOMMUState *s = opaque;
291 int i;
292
293 if (version_id != 2)
294 return -EINVAL;
295
296 for (i = 0; i < IOMMU_NREGS; i++)
297 qemu_get_be32s(f, &s->regs[i]);
298 qemu_get_be64s(f, &s->iostart);
299
300 return 0;
301 }
302
303 static void iommu_reset(void *opaque)
304 {
305 IOMMUState *s = opaque;
306
307 memset(s->regs, 0, IOMMU_NREGS * 4);
308 s->iostart = 0;
309 s->regs[IOMMU_CTRL] = IOMMU_VERSION;
310 }
311
312 void *iommu_init(target_phys_addr_t addr)
313 {
314 IOMMUState *s;
315 int iommu_io_memory;
316
317 s = qemu_mallocz(sizeof(IOMMUState));
318 if (!s)
319 return NULL;
320
321 s->addr = addr;
322
323 iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
324 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
325
326 register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
327 qemu_register_reset(iommu_reset, s);
328 return s;
329 }
330