hw/iommu.c

   1 /*
   2  * QEMU SPARC iommu emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26
  27 /* debug iommu */
  28 //#define DEBUG_IOMMU
  29
  30 #ifdef DEBUG_IOMMU
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("IOMMU: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 #define IOMMU_NREGS (3*4096/4)
  38 #define IOMMU_CTRL          (0x0000 >> 2)
  39 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  40 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  41 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  42 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  43 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  44 #define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  45 #define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  46 #define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  47 #define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  48 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  49 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  50 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  51 #define IOMMU_CTRL_MASK     0x0000001d
  52
  53 #define IOMMU_BASE          (0x0004 >> 2)
  54 #define IOMMU_BASE_MASK     0x07fffc00
  55
  56 #define IOMMU_TLBFLUSH      (0x0014 >> 2)
  57 #define IOMMU_TLBFLUSH_MASK 0xffffffff
  58
  59 #define IOMMU_PGFLUSH       (0x0018 >> 2)
  60 #define IOMMU_PGFLUSH_MASK  0xffffffff
  61
  62 #define IOMMU_AFSR          (0x1000 >> 2)
  63 #define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  64 #define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
  65                                           transaction */
  66 #define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
  67                                           12.8 us. */
  68 #define IOMMU_AFSR_BE       0x10000000 /* Write access received error
  69                                           acknowledge */
  70 #define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  71 #define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  72 #define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
  73                                           hardware */
  74 #define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  75 #define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  76 #define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  77
  78 #define IOMMU_AFAR          (0x1004 >> 2)
  79
  80 #define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  81 #define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  82 #define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  83 #define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
  84 #define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
  85                                           bypass enabled */
  86 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
  87 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
  88 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
  89                                           produced by this device as pure
  90                                           physical. */
  91 #define IOMMU_SBCFG_MASK    0x00010003
  92
  93 #define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
  94 #define IOMMU_ARBEN_MASK    0x001f0000
  95 #define IOMMU_MID           0x00000008
  96
  97 /* The format of an iopte in the page tables */
  98 #define IOPTE_PAGE          0x07ffff00 /* Physical page number (PA[30:12]) */
  99 #define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
 100                                           Viking/MXCC) */
 101 #define IOPTE_WRITE         0x00000004 /* Writeable */
 102 #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
 103 #define IOPTE_WAZ           0x00000001 /* Write as zeros */
 104
 105 #define PAGE_SHIFT      12
 106 #define PAGE_SIZE       (1 << PAGE_SHIFT)
 107 #define PAGE_MASK       (PAGE_SIZE - 1)
 108
 109 typedef struct IOMMUState {
 110     target_phys_addr_t addr;
 111     uint32_t regs[IOMMU_NREGS];
 112     target_phys_addr_t iostart;
 113     uint32_t version;
 114 } IOMMUState;
 115
 116 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
 117 {
 118     IOMMUState *s = opaque;
 119     target_phys_addr_t saddr;
 120
 121     saddr = (addr - s->addr) >> 2;
 122     switch (saddr) {
 123     default:
 124         DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
 125         return s->regs[saddr];
 126         break;
 127     }
 128     return 0;
 129 }
 130
 131 static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
 132                              uint32_t val)
 133 {
 134     IOMMUState *s = opaque;
 135     target_phys_addr_t saddr;
 136
 137     saddr = (addr - s->addr) >> 2;
 138     DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
 139     switch (saddr) {
 140     case IOMMU_CTRL:
 141         switch (val & IOMMU_CTRL_RNGE) {
 142         case IOMMU_RNGE_16MB:
 143             s->iostart = 0xffffffffff000000ULL;
 144             break;
 145         case IOMMU_RNGE_32MB:
 146             s->iostart = 0xfffffffffe000000ULL;
 147             break;
 148         case IOMMU_RNGE_64MB:
 149             s->iostart = 0xfffffffffc000000ULL;
 150             break;
 151         case IOMMU_RNGE_128MB:
 152             s->iostart = 0xfffffffff8000000ULL;
 153             break;
 154         case IOMMU_RNGE_256MB:
 155             s->iostart = 0xfffffffff0000000ULL;
 156             break;
 157         case IOMMU_RNGE_512MB:
 158             s->iostart = 0xffffffffe0000000ULL;
 159             break;
 160         case IOMMU_RNGE_1GB:
 161             s->iostart = 0xffffffffc0000000ULL;
 162             break;
 163         default:
 164         case IOMMU_RNGE_2GB:
 165             s->iostart = 0xffffffff80000000ULL;
 166             break;
 167         }
 168         DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
 169         s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 170         break;
 171     case IOMMU_BASE:
 172         s->regs[saddr] = val & IOMMU_BASE_MASK;
 173         break;
 174     case IOMMU_TLBFLUSH:
 175         DPRINTF("tlb flush %x\n", val);
 176         s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 177         break;
 178     case IOMMU_PGFLUSH:
 179         DPRINTF("page flush %x\n", val);
 180         s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 181         break;
 182     case IOMMU_SBCFG0:
 183     case IOMMU_SBCFG1:
 184     case IOMMU_SBCFG2:
 185     case IOMMU_SBCFG3:
 186         s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 187         break;
 188     case IOMMU_ARBEN:
 189         // XXX implement SBus probing: fault when reading unmapped
 190         // addresses, fault cause and address stored to MMU/IOMMU
 191         s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 192         break;
 193     default:
 194         s->regs[saddr] = val;
 195         break;
 196     }
 197 }
 198
 199 static CPUReadMemoryFunc *iommu_mem_read[3] = {
 200     iommu_mem_readw,
 201     iommu_mem_readw,
 202     iommu_mem_readw,
 203 };
 204
 205 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
 206     iommu_mem_writew,
 207     iommu_mem_writew,
 208     iommu_mem_writew,
 209 };
 210
 211 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
 212 {
 213     uint32_t ret;
 214     target_phys_addr_t iopte;
 215 #ifdef DEBUG_IOMMU
 216     target_phys_addr_t pa = addr;
 217 #endif
 218
 219     iopte = s->regs[IOMMU_BASE] << 4;
 220     addr &= ~s->iostart;
 221     iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
 222     cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
 223     tswap32s(&ret);
 224     DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
 225             ", *pte = %x\n", pa, iopte, ret);
 226
 227     return ret;
 228 }
 229
 230 static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
 231                                              target_phys_addr_t addr,
 232                                              uint32_t pte)
 233 {
 234     uint32_t tmppte;
 235     target_phys_addr_t pa;
 236
 237     tmppte = pte;
 238     pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
 239     DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
 240             " (iopte = %x)\n", addr, pa, tmppte);
 241
 242     return pa;
 243 }
 244
 245 static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
 246                            int is_write)
 247 {
 248     DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
 249     s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
 250         IOMMU_AFSR_FAV;
 251     if (!is_write)
 252         s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 253     s->regs[IOMMU_AFAR] = addr;
 254 }
 255
 256 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
 257                            uint8_t *buf, int len, int is_write)
 258 {
 259     int l;
 260     uint32_t flags;
 261     target_phys_addr_t page, phys_addr;
 262
 263     while (len > 0) {
 264         page = addr & TARGET_PAGE_MASK;
 265         l = (page + TARGET_PAGE_SIZE) - addr;
 266         if (l > len)
 267             l = len;
 268         flags = iommu_page_get_flags(opaque, page);
 269         if (!(flags & IOPTE_VALID)) {
 270             iommu_bad_addr(opaque, page, is_write);
 271             return;
 272         }
 273         phys_addr = iommu_translate_pa(opaque, addr, flags);
 274         if (is_write) {
 275             if (!(flags & IOPTE_WRITE)) {
 276                 iommu_bad_addr(opaque, page, is_write);
 277                 return;
 278             }
 279             cpu_physical_memory_write(phys_addr, buf, len);
 280         } else {
 281             cpu_physical_memory_read(phys_addr, buf, len);
 282         }
 283         len -= l;
 284         buf += l;
 285         addr += l;
 286     }
 287 }
 288
 289 static void iommu_save(QEMUFile *f, void *opaque)
 290 {
 291     IOMMUState *s = opaque;
 292     int i;
 293
 294     for (i = 0; i < IOMMU_NREGS; i++)
 295         qemu_put_be32s(f, &s->regs[i]);
 296     qemu_put_be64s(f, &s->iostart);
 297 }
 298
 299 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
 300 {
 301     IOMMUState *s = opaque;
 302     int i;
 303
 304     if (version_id != 2)
 305         return -EINVAL;
 306
 307     for (i = 0; i < IOMMU_NREGS; i++)
 308         qemu_get_be32s(f, &s->regs[i]);
 309     qemu_get_be64s(f, &s->iostart);
 310
 311     return 0;
 312 }
 313
 314 static void iommu_reset(void *opaque)
 315 {
 316     IOMMUState *s = opaque;
 317
 318     memset(s->regs, 0, IOMMU_NREGS * 4);
 319     s->iostart = 0;
 320     s->regs[IOMMU_CTRL] = s->version;
 321     s->regs[IOMMU_ARBEN] = IOMMU_MID;
 322     s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
 323 }
 324
 325 void *iommu_init(target_phys_addr_t addr, uint32_t version)
 326 {
 327     IOMMUState *s;
 328     int iommu_io_memory;
 329
 330     s = qemu_mallocz(sizeof(IOMMUState));
 331     if (!s)
 332         return NULL;
 333
 334     s->addr = addr;
 335     s->version = version;
 336
 337     iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
 338                                              iommu_mem_write, s);
 339     cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
 340
 341     register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
 342     qemu_register_reset(iommu_reset, s);
 343     iommu_reset(s);
 344     return s;
 345 }