hw/lm32/lm32_boards.c

   1 /*
   2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "hw/sysbus.h"
  21 #include "hw/hw.h"
  22 #include "hw/flash.h"
  23 #include "hw/devices.h"
  24 #include "hw/boards.h"
  25 #include "hw/loader.h"
  26 #include "sysemu/blockdev.h"
  27 #include "elf.h"
  28 #include "hw/lm32_hwsetup.h"
  29 #include "hw/lm32.h"
  30 #include "exec/address-spaces.h"
  31
  32 typedef struct {
  33     LM32CPU *cpu;
  34     hwaddr bootstrap_pc;
  35     hwaddr flash_base;
  36     hwaddr hwsetup_base;
  37     hwaddr initrd_base;
  38     size_t initrd_size;
  39     hwaddr cmdline_base;
  40 } ResetInfo;
  41
  42 static void cpu_irq_handler(void *opaque, int irq, int level)
  43 {
  44     LM32CPU *cpu = opaque;
  45     CPULM32State *env = &cpu->env;
  46     CPUState *cs = CPU(cpu);
  47
  48     if (level) {
  49         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  50     } else {
  51         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  52     }
  53 }
  54
  55 static void main_cpu_reset(void *opaque)
  56 {
  57     ResetInfo *reset_info = opaque;
  58     CPULM32State *env = &reset_info->cpu->env;
  59
  60     cpu_reset(CPU(reset_info->cpu));
  61
  62     /* init defaults */
  63     env->pc = (uint32_t)reset_info->bootstrap_pc;
  64     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
  65     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
  66     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
  67     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
  68         reset_info->initrd_size);
  69     env->eba = reset_info->flash_base;
  70     env->deba = reset_info->flash_base;
  71 }
  72
  73 static void lm32_evr_init(QEMUMachineInitArgs *args)
  74 {
  75     const char *cpu_model = args->cpu_model;
  76     const char *kernel_filename = args->kernel_filename;
  77     LM32CPU *cpu;
  78     CPULM32State *env;
  79     DriveInfo *dinfo;
  80     MemoryRegion *address_space_mem =  get_system_memory();
  81     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
  82     qemu_irq *cpu_irq, irq[32];
  83     ResetInfo *reset_info;
  84     int i;
  85
  86     /* memory map */
  87     hwaddr flash_base  = 0x04000000;
  88     size_t flash_sector_size       = 256 * 1024;
  89     size_t flash_size              = 32 * 1024 * 1024;
  90     hwaddr ram_base    = 0x08000000;
  91     size_t ram_size                = 64 * 1024 * 1024;
  92     hwaddr timer0_base = 0x80002000;
  93     hwaddr uart0_base  = 0x80006000;
  94     hwaddr timer1_base = 0x8000a000;
  95     int uart0_irq                  = 0;
  96     int timer0_irq                 = 1;
  97     int timer1_irq                 = 3;
  98
  99     reset_info = g_malloc0(sizeof(ResetInfo));
 100
 101     if (cpu_model == NULL) {
 102         cpu_model = "lm32-full";
 103     }
 104     cpu = cpu_lm32_init(cpu_model);
 105     env = &cpu->env;
 106     reset_info->cpu = cpu;
 107
 108     reset_info->flash_base = flash_base;
 109
 110     memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
 111     vmstate_register_ram_global(phys_ram);
 112     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 113
 114     dinfo = drive_get(IF_PFLASH, 0, 0);
 115     /* Spansion S29NS128P */
 116     pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
 117                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
 118                           flash_size / flash_sector_size, 1, 2,
 119                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 120
 121     /* create irq lines */
 122     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
 123     env->pic_state = lm32_pic_init(*cpu_irq);
 124     for (i = 0; i < 32; i++) {
 125         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 126     }
 127
 128     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 129     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 130     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 131
 132     /* make sure juart isn't the first chardev */
 133     env->juart_state = lm32_juart_init();
 134
 135     reset_info->bootstrap_pc = flash_base;
 136
 137     if (kernel_filename) {
 138         uint64_t entry;
 139         int kernel_size;
 140
 141         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 142                                1, ELF_MACHINE, 0);
 143         reset_info->bootstrap_pc = entry;
 144
 145         if (kernel_size < 0) {
 146             kernel_size = load_image_targphys(kernel_filename, ram_base,
 147                                               ram_size);
 148             reset_info->bootstrap_pc = ram_base;
 149         }
 150
 151         if (kernel_size < 0) {
 152             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 153                     kernel_filename);
 154             exit(1);
 155         }
 156     }
 157
 158     qemu_register_reset(main_cpu_reset, reset_info);
 159 }
 160
 161 static void lm32_uclinux_init(QEMUMachineInitArgs *args)
 162 {
 163     const char *cpu_model = args->cpu_model;
 164     const char *kernel_filename = args->kernel_filename;
 165     const char *kernel_cmdline = args->kernel_cmdline;
 166     const char *initrd_filename = args->initrd_filename;
 167     LM32CPU *cpu;
 168     CPULM32State *env;
 169     DriveInfo *dinfo;
 170     MemoryRegion *address_space_mem =  get_system_memory();
 171     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
 172     qemu_irq *cpu_irq, irq[32];
 173     HWSetup *hw;
 174     ResetInfo *reset_info;
 175     int i;
 176
 177     /* memory map */
 178     hwaddr flash_base   = 0x04000000;
 179     size_t flash_sector_size        = 256 * 1024;
 180     size_t flash_size               = 32 * 1024 * 1024;
 181     hwaddr ram_base     = 0x08000000;
 182     size_t ram_size                 = 64 * 1024 * 1024;
 183     hwaddr uart0_base   = 0x80000000;
 184     hwaddr timer0_base  = 0x80002000;
 185     hwaddr timer1_base  = 0x80010000;
 186     hwaddr timer2_base  = 0x80012000;
 187     int uart0_irq                   = 0;
 188     int timer0_irq                  = 1;
 189     int timer1_irq                  = 20;
 190     int timer2_irq                  = 21;
 191     hwaddr hwsetup_base = 0x0bffe000;
 192     hwaddr cmdline_base = 0x0bfff000;
 193     hwaddr initrd_base  = 0x08400000;
 194     size_t initrd_max               = 0x01000000;
 195
 196     reset_info = g_malloc0(sizeof(ResetInfo));
 197
 198     if (cpu_model == NULL) {
 199         cpu_model = "lm32-full";
 200     }
 201     cpu = cpu_lm32_init(cpu_model);
 202     env = &cpu->env;
 203     reset_info->cpu = cpu;
 204
 205     reset_info->flash_base = flash_base;
 206
 207     memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
 208     vmstate_register_ram_global(phys_ram);
 209     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 210
 211     dinfo = drive_get(IF_PFLASH, 0, 0);
 212     /* Spansion S29NS128P */
 213     pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
 214                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
 215                           flash_size / flash_sector_size, 1, 2,
 216                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 217
 218     /* create irq lines */
 219     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
 220     env->pic_state = lm32_pic_init(*cpu_irq);
 221     for (i = 0; i < 32; i++) {
 222         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 223     }
 224
 225     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 226     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 227     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 228     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
 229
 230     /* make sure juart isn't the first chardev */
 231     env->juart_state = lm32_juart_init();
 232
 233     reset_info->bootstrap_pc = flash_base;
 234
 235     if (kernel_filename) {
 236         uint64_t entry;
 237         int kernel_size;
 238
 239         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 240                                1, ELF_MACHINE, 0);
 241         reset_info->bootstrap_pc = entry;
 242
 243         if (kernel_size < 0) {
 244             kernel_size = load_image_targphys(kernel_filename, ram_base,
 245                                               ram_size);
 246             reset_info->bootstrap_pc = ram_base;
 247         }
 248
 249         if (kernel_size < 0) {
 250             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 251                     kernel_filename);
 252             exit(1);
 253         }
 254     }
 255
 256     /* generate a rom with the hardware description */
 257     hw = hwsetup_init();
 258     hwsetup_add_cpu(hw, "LM32", 75000000);
 259     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
 260     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
 261     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
 262     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
 263     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
 264     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
 265     hwsetup_add_trailer(hw);
 266     hwsetup_create_rom(hw, hwsetup_base);
 267     hwsetup_free(hw);
 268
 269     reset_info->hwsetup_base = hwsetup_base;
 270
 271     if (kernel_cmdline && strlen(kernel_cmdline)) {
 272         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 273                 kernel_cmdline);
 274         reset_info->cmdline_base = cmdline_base;
 275     }
 276
 277     if (initrd_filename) {
 278         size_t initrd_size;
 279         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 280                 initrd_max);
 281         reset_info->initrd_base = initrd_base;
 282         reset_info->initrd_size = initrd_size;
 283     }
 284
 285     qemu_register_reset(main_cpu_reset, reset_info);
 286 }
 287
 288 static QEMUMachine lm32_evr_machine = {
 289     .name = "lm32-evr",
 290     .desc = "LatticeMico32 EVR32 eval system",
 291     .init = lm32_evr_init,
 292     .is_default = 1,
 293     DEFAULT_MACHINE_OPTIONS,
 294 };
 295
 296 static QEMUMachine lm32_uclinux_machine = {
 297     .name = "lm32-uclinux",
 298     .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
 299     .init = lm32_uclinux_init,
 300     .is_default = 0,
 301     DEFAULT_MACHINE_OPTIONS,
 302 };
 303
 304 static void lm32_machine_init(void)
 305 {
 306     qemu_register_machine(&lm32_uclinux_machine);
 307     qemu_register_machine(&lm32_evr_machine);
 308 }
 309
 310 machine_init(lm32_machine_init);