hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "hpet_emul.h"
  30
  31 //#define DEBUG_CMOS
  32
  33 #define RTC_SECONDS             0
  34 #define RTC_SECONDS_ALARM       1
  35 #define RTC_MINUTES             2
  36 #define RTC_MINUTES_ALARM       3
  37 #define RTC_HOURS               4
  38 #define RTC_HOURS_ALARM         5
  39 #define RTC_ALARM_DONT_CARE    0xC0
  40
  41 #define RTC_DAY_OF_WEEK         6
  42 #define RTC_DAY_OF_MONTH        7
  43 #define RTC_MONTH               8
  44 #define RTC_YEAR                9
  45
  46 #define RTC_REG_A               10
  47 #define RTC_REG_B               11
  48 #define RTC_REG_C               12
  49 #define RTC_REG_D               13
  50
  51 #define REG_A_UIP 0x80
  52
  53 #define REG_B_SET  0x80
  54 #define REG_B_PIE  0x40
  55 #define REG_B_AIE  0x20
  56 #define REG_B_UIE  0x10
  57 #define REG_B_SQWE 0x08
  58 #define REG_B_DM   0x04
  59
  60 #define REG_C_UF   0x10
  61 #define REG_C_IRQF 0x80
  62 #define REG_C_PF   0x40
  63 #define REG_C_AF   0x20
  64
  65 struct RTCState {
  66     ISADevice dev;
  67     uint8_t cmos_data[128];
  68     uint8_t cmos_index;
  69     struct tm current_tm;
  70     int32_t base_year;
  71     qemu_irq irq;
  72     qemu_irq sqw_irq;
  73     int it_shift;
  74     /* periodic timer */
  75     QEMUTimer *periodic_timer;
  76     int64_t next_periodic_time;
  77     /* second update */
  78     int64_t next_second_time;
  79 #ifdef TARGET_I386
  80     uint32_t irq_coalesced;
  81     uint32_t period;
  82     QEMUTimer *coalesced_timer;
  83 #endif
  84     QEMUTimer *second_timer;
  85     QEMUTimer *second_timer2;
  86 };
  87
  88 static void rtc_irq_raise(qemu_irq irq) {
  89     /* When HPET is operating in legacy mode, RTC interrupts are disabled
  90      * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
  91      * mode is established while interrupt is raised. We want it to
  92      * be lowered in any case
  93      */
  94 #if defined TARGET_I386 || defined TARGET_X86_64
  95     if (!hpet_in_legacy_mode())
  96 #endif
  97         qemu_irq_raise(irq);
  98 }
  99
 100 static void rtc_set_time(RTCState *s);
 101 static void rtc_copy_date(RTCState *s);
 102
 103 #ifdef TARGET_I386
 104 static void rtc_coalesced_timer_update(RTCState *s)
 105 {
 106     if (s->irq_coalesced == 0) {
 107         qemu_del_timer(s->coalesced_timer);
 108     } else {
 109         /* divide each RTC interval to 2 - 8 smaller intervals */
 110         int c = MIN(s->irq_coalesced, 7) + 1;
 111         int64_t next_clock = qemu_get_clock(vm_clock) +
 112                 muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 113         qemu_mod_timer(s->coalesced_timer, next_clock);
 114     }
 115 }
 116
 117 static void rtc_coalesced_timer(void *opaque)
 118 {
 119     RTCState *s = opaque;
 120
 121     if (s->irq_coalesced != 0) {
 122         apic_reset_irq_delivered();
 123         s->cmos_data[RTC_REG_C] |= 0xc0;
 124         rtc_irq_raise(s->irq);
 125         if (apic_get_irq_delivered()) {
 126             s->irq_coalesced--;
 127         }
 128     }
 129
 130     rtc_coalesced_timer_update(s);
 131 }
 132 #endif
 133
 134 static void rtc_timer_update(RTCState *s, int64_t current_time)
 135 {
 136     int period_code, period;
 137     int64_t cur_clock, next_irq_clock;
 138     int enable_pie;
 139
 140     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 141 #if defined TARGET_I386 || defined TARGET_X86_64
 142     /* disable periodic timer if hpet is in legacy mode, since interrupts are
 143      * disabled anyway.
 144      */
 145     enable_pie = !hpet_in_legacy_mode();
 146 #else
 147     enable_pie = 1;
 148 #endif
 149     if (period_code != 0
 150         && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
 151             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 152         if (period_code <= 2)
 153             period_code += 7;
 154         /* period in 32 Khz cycles */
 155         period = 1 << (period_code - 1);
 156 #ifdef TARGET_I386
 157         if(period != s->period)
 158             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 159         s->period = period;
 160 #endif
 161         /* compute 32 khz clock */
 162         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 163         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 164         s->next_periodic_time = muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 165         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 166     } else {
 167 #ifdef TARGET_I386
 168         s->irq_coalesced = 0;
 169 #endif
 170         qemu_del_timer(s->periodic_timer);
 171     }
 172 }
 173
 174 static void rtc_periodic_timer(void *opaque)
 175 {
 176     RTCState *s = opaque;
 177
 178     rtc_timer_update(s, s->next_periodic_time);
 179     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 180         s->cmos_data[RTC_REG_C] |= 0xc0;
 181 #ifdef TARGET_I386
 182         if(rtc_td_hack) {
 183             apic_reset_irq_delivered();
 184             rtc_irq_raise(s->irq);
 185             if (!apic_get_irq_delivered()) {
 186                 s->irq_coalesced++;
 187                 rtc_coalesced_timer_update(s);
 188             }
 189         } else
 190 #endif
 191         rtc_irq_raise(s->irq);
 192     }
 193     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 194         /* Not square wave at all but we don't want 2048Hz interrupts!
 195            Must be seen as a pulse.  */
 196         qemu_irq_raise(s->sqw_irq);
 197     }
 198 }
 199
 200 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 201 {
 202     RTCState *s = opaque;
 203
 204     if ((addr & 1) == 0) {
 205         s->cmos_index = data & 0x7f;
 206     } else {
 207 #ifdef DEBUG_CMOS
 208         printf("cmos: write index=0x%02x val=0x%02x\n",
 209                s->cmos_index, data);
 210 #endif
 211         switch(s->cmos_index) {
 212         case RTC_SECONDS_ALARM:
 213         case RTC_MINUTES_ALARM:
 214         case RTC_HOURS_ALARM:
 215             /* XXX: not supported */
 216             s->cmos_data[s->cmos_index] = data;
 217             break;
 218         case RTC_SECONDS:
 219         case RTC_MINUTES:
 220         case RTC_HOURS:
 221         case RTC_DAY_OF_WEEK:
 222         case RTC_DAY_OF_MONTH:
 223         case RTC_MONTH:
 224         case RTC_YEAR:
 225             s->cmos_data[s->cmos_index] = data;
 226             /* if in set mode, do not update the time */
 227             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 228                 rtc_set_time(s);
 229             }
 230             break;
 231         case RTC_REG_A:
 232             /* UIP bit is read only */
 233             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 234                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 235             rtc_timer_update(s, qemu_get_clock(vm_clock));
 236             break;
 237         case RTC_REG_B:
 238             if (data & REG_B_SET) {
 239                 /* set mode: reset UIP mode */
 240                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 241                 data &= ~REG_B_UIE;
 242             } else {
 243                 /* if disabling set mode, update the time */
 244                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 245                     rtc_set_time(s);
 246                 }
 247             }
 248             s->cmos_data[RTC_REG_B] = data;
 249             rtc_timer_update(s, qemu_get_clock(vm_clock));
 250             break;
 251         case RTC_REG_C:
 252         case RTC_REG_D:
 253             /* cannot write to them */
 254             break;
 255         default:
 256             s->cmos_data[s->cmos_index] = data;
 257             break;
 258         }
 259     }
 260 }
 261
 262 static inline int to_bcd(RTCState *s, int a)
 263 {
 264     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 265         return a;
 266     } else {
 267         return ((a / 10) << 4) | (a % 10);
 268     }
 269 }
 270
 271 static inline int from_bcd(RTCState *s, int a)
 272 {
 273     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 274         return a;
 275     } else {
 276         return ((a >> 4) * 10) + (a & 0x0f);
 277     }
 278 }
 279
 280 static void rtc_set_time(RTCState *s)
 281 {
 282     struct tm *tm = &s->current_tm;
 283
 284     tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
 285     tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
 286     tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 287     if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
 288         (s->cmos_data[RTC_HOURS] & 0x80)) {
 289         tm->tm_hour += 12;
 290     }
 291     tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 292     tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 293     tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 294     tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 295 }
 296
 297 static void rtc_copy_date(RTCState *s)
 298 {
 299     const struct tm *tm = &s->current_tm;
 300     int year;
 301
 302     s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
 303     s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
 304     if (s->cmos_data[RTC_REG_B] & 0x02) {
 305         /* 24 hour format */
 306         s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
 307     } else {
 308         /* 12 hour format */
 309         s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
 310         if (tm->tm_hour >= 12)
 311             s->cmos_data[RTC_HOURS] |= 0x80;
 312     }
 313     s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
 314     s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
 315     s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
 316     year = (tm->tm_year - s->base_year) % 100;
 317     if (year < 0)
 318         year += 100;
 319     s->cmos_data[RTC_YEAR] = to_bcd(s, year);
 320 }
 321
 322 /* month is between 0 and 11. */
 323 static int get_days_in_month(int month, int year)
 324 {
 325     static const int days_tab[12] = {
 326         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 327     };
 328     int d;
 329     if ((unsigned )month >= 12)
 330         return 31;
 331     d = days_tab[month];
 332     if (month == 1) {
 333         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 334             d++;
 335     }
 336     return d;
 337 }
 338
 339 /* update 'tm' to the next second */
 340 static void rtc_next_second(struct tm *tm)
 341 {
 342     int days_in_month;
 343
 344     tm->tm_sec++;
 345     if ((unsigned)tm->tm_sec >= 60) {
 346         tm->tm_sec = 0;
 347         tm->tm_min++;
 348         if ((unsigned)tm->tm_min >= 60) {
 349             tm->tm_min = 0;
 350             tm->tm_hour++;
 351             if ((unsigned)tm->tm_hour >= 24) {
 352                 tm->tm_hour = 0;
 353                 /* next day */
 354                 tm->tm_wday++;
 355                 if ((unsigned)tm->tm_wday >= 7)
 356                     tm->tm_wday = 0;
 357                 days_in_month = get_days_in_month(tm->tm_mon,
 358                                                   tm->tm_year + 1900);
 359                 tm->tm_mday++;
 360                 if (tm->tm_mday < 1) {
 361                     tm->tm_mday = 1;
 362                 } else if (tm->tm_mday > days_in_month) {
 363                     tm->tm_mday = 1;
 364                     tm->tm_mon++;
 365                     if (tm->tm_mon >= 12) {
 366                         tm->tm_mon = 0;
 367                         tm->tm_year++;
 368                     }
 369                 }
 370             }
 371         }
 372     }
 373 }
 374
 375
 376 static void rtc_update_second(void *opaque)
 377 {
 378     RTCState *s = opaque;
 379     int64_t delay;
 380
 381     /* if the oscillator is not in normal operation, we do not update */
 382     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 383         s->next_second_time += get_ticks_per_sec();
 384         qemu_mod_timer(s->second_timer, s->next_second_time);
 385     } else {
 386         rtc_next_second(&s->current_tm);
 387
 388         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 389             /* update in progress bit */
 390             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 391         }
 392         /* should be 244 us = 8 / 32768 seconds, but currently the
 393            timers do not have the necessary resolution. */
 394         delay = (get_ticks_per_sec() * 1) / 100;
 395         if (delay < 1)
 396             delay = 1;
 397         qemu_mod_timer(s->second_timer2,
 398                        s->next_second_time + delay);
 399     }
 400 }
 401
 402 static void rtc_update_second2(void *opaque)
 403 {
 404     RTCState *s = opaque;
 405
 406     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 407         rtc_copy_date(s);
 408     }
 409
 410     /* check alarm */
 411     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 412         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 413              s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
 414             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 415              s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
 416             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 417              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 418
 419             s->cmos_data[RTC_REG_C] |= 0xa0;
 420             rtc_irq_raise(s->irq);
 421         }
 422     }
 423
 424     /* update ended interrupt */
 425     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 426     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 427       s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 428       rtc_irq_raise(s->irq);
 429     }
 430
 431     /* clear update in progress bit */
 432     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 433
 434     s->next_second_time += get_ticks_per_sec();
 435     qemu_mod_timer(s->second_timer, s->next_second_time);
 436 }
 437
 438 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 439 {
 440     RTCState *s = opaque;
 441     int ret;
 442     if ((addr & 1) == 0) {
 443         return 0xff;
 444     } else {
 445         switch(s->cmos_index) {
 446         case RTC_SECONDS:
 447         case RTC_MINUTES:
 448         case RTC_HOURS:
 449         case RTC_DAY_OF_WEEK:
 450         case RTC_DAY_OF_MONTH:
 451         case RTC_MONTH:
 452         case RTC_YEAR:
 453             ret = s->cmos_data[s->cmos_index];
 454             break;
 455         case RTC_REG_A:
 456             ret = s->cmos_data[s->cmos_index];
 457             break;
 458         case RTC_REG_C:
 459             ret = s->cmos_data[s->cmos_index];
 460             qemu_irq_lower(s->irq);
 461             s->cmos_data[RTC_REG_C] = 0x00;
 462             break;
 463         default:
 464             ret = s->cmos_data[s->cmos_index];
 465             break;
 466         }
 467 #ifdef DEBUG_CMOS
 468         printf("cmos: read index=0x%02x val=0x%02x\n",
 469                s->cmos_index, ret);
 470 #endif
 471         return ret;
 472     }
 473 }
 474
 475 void rtc_set_memory(RTCState *s, int addr, int val)
 476 {
 477     if (addr >= 0 && addr <= 127)
 478         s->cmos_data[addr] = val;
 479 }
 480
 481 void rtc_set_date(RTCState *s, const struct tm *tm)
 482 {
 483     s->current_tm = *tm;
 484     rtc_copy_date(s);
 485 }
 486
 487 /* PC cmos mappings */
 488 #define REG_IBM_CENTURY_BYTE        0x32
 489 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 490
 491 static void rtc_set_date_from_host(RTCState *s)
 492 {
 493     struct tm tm;
 494     int val;
 495
 496     /* set the CMOS date */
 497     qemu_get_timedate(&tm, 0);
 498     rtc_set_date(s, &tm);
 499
 500     val = to_bcd(s, (tm.tm_year / 100) + 19);
 501     rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
 502     rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
 503 }
 504
 505 static void rtc_save(QEMUFile *f, void *opaque)
 506 {
 507     RTCState *s = opaque;
 508
 509     qemu_put_buffer(f, s->cmos_data, 128);
 510     qemu_put_8s(f, &s->cmos_index);
 511
 512     qemu_put_be32(f, s->current_tm.tm_sec);
 513     qemu_put_be32(f, s->current_tm.tm_min);
 514     qemu_put_be32(f, s->current_tm.tm_hour);
 515     qemu_put_be32(f, s->current_tm.tm_wday);
 516     qemu_put_be32(f, s->current_tm.tm_mday);
 517     qemu_put_be32(f, s->current_tm.tm_mon);
 518     qemu_put_be32(f, s->current_tm.tm_year);
 519
 520     qemu_put_timer(f, s->periodic_timer);
 521     qemu_put_be64(f, s->next_periodic_time);
 522
 523     qemu_put_be64(f, s->next_second_time);
 524     qemu_put_timer(f, s->second_timer);
 525     qemu_put_timer(f, s->second_timer2);
 526 }
 527
 528 static int rtc_load(QEMUFile *f, void *opaque, int version_id)
 529 {
 530     RTCState *s = opaque;
 531
 532     if (version_id != 1)
 533         return -EINVAL;
 534
 535     qemu_get_buffer(f, s->cmos_data, 128);
 536     qemu_get_8s(f, &s->cmos_index);
 537
 538     s->current_tm.tm_sec=qemu_get_be32(f);
 539     s->current_tm.tm_min=qemu_get_be32(f);
 540     s->current_tm.tm_hour=qemu_get_be32(f);
 541     s->current_tm.tm_wday=qemu_get_be32(f);
 542     s->current_tm.tm_mday=qemu_get_be32(f);
 543     s->current_tm.tm_mon=qemu_get_be32(f);
 544     s->current_tm.tm_year=qemu_get_be32(f);
 545
 546     qemu_get_timer(f, s->periodic_timer);
 547     s->next_periodic_time=qemu_get_be64(f);
 548
 549     s->next_second_time=qemu_get_be64(f);
 550     qemu_get_timer(f, s->second_timer);
 551     qemu_get_timer(f, s->second_timer2);
 552     return 0;
 553 }
 554
 555 #ifdef TARGET_I386
 556 static void rtc_save_td(QEMUFile *f, void *opaque)
 557 {
 558     RTCState *s = opaque;
 559
 560     qemu_put_be32(f, s->irq_coalesced);
 561     qemu_put_be32(f, s->period);
 562 }
 563
 564 static int rtc_load_td(QEMUFile *f, void *opaque, int version_id)
 565 {
 566     RTCState *s = opaque;
 567
 568     if (version_id != 1)
 569         return -EINVAL;
 570
 571     s->irq_coalesced = qemu_get_be32(f);
 572     s->period = qemu_get_be32(f);
 573     rtc_coalesced_timer_update(s);
 574     return 0;
 575 }
 576 #endif
 577
 578 static void rtc_reset(void *opaque)
 579 {
 580     RTCState *s = opaque;
 581
 582     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 583     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 584
 585     qemu_irq_lower(s->irq);
 586
 587 #ifdef TARGET_I386
 588     if (rtc_td_hack)
 589             s->irq_coalesced = 0;
 590 #endif
 591 }
 592
 593 static int rtc_initfn(ISADevice *dev)
 594 {
 595     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 596     int base = 0x70;
 597     int isairq = 8;
 598
 599     isa_init_irq(dev, &s->irq, isairq);
 600
 601     s->cmos_data[RTC_REG_A] = 0x26;
 602     s->cmos_data[RTC_REG_B] = 0x02;
 603     s->cmos_data[RTC_REG_C] = 0x00;
 604     s->cmos_data[RTC_REG_D] = 0x80;
 605
 606     rtc_set_date_from_host(s);
 607
 608     s->periodic_timer = qemu_new_timer(vm_clock,
 609                                        rtc_periodic_timer, s);
 610 #ifdef TARGET_I386
 611     if (rtc_td_hack)
 612         s->coalesced_timer = qemu_new_timer(vm_clock, rtc_coalesced_timer, s);
 613 #endif
 614     s->second_timer = qemu_new_timer(vm_clock,
 615                                      rtc_update_second, s);
 616     s->second_timer2 = qemu_new_timer(vm_clock,
 617                                       rtc_update_second2, s);
 618
 619     s->next_second_time = qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 99) / 100;
 620     qemu_mod_timer(s->second_timer2, s->next_second_time);
 621
 622     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 623     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 624
 625     register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
 626 #ifdef TARGET_I386
 627     if (rtc_td_hack)
 628         register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
 629 #endif
 630     qemu_register_reset(rtc_reset, s);
 631     return 0;
 632 }
 633
 634 RTCState *rtc_init(int base_year)
 635 {
 636     ISADevice *dev;
 637
 638     dev = isa_create("mc146818rtc");
 639     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 640     qdev_init(&dev->qdev);
 641     return DO_UPCAST(RTCState, dev, dev);
 642 }
 643
 644 static ISADeviceInfo mc146818rtc_info = {
 645     .qdev.name     = "mc146818rtc",
 646     .qdev.size     = sizeof(RTCState),
 647     .qdev.no_user  = 1,
 648     .init          = rtc_initfn,
 649     .qdev.props    = (Property[]) {
 650         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 651         DEFINE_PROP_END_OF_LIST(),
 652     }
 653 };
 654
 655 static void mc146818rtc_register(void)
 656 {
 657     isa_qdev_register(&mc146818rtc_info);
 658 }
 659 device_init(mc146818rtc_register)
 660
 661 /* Memory mapped interface */
 662 static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
 663 {
 664     RTCState *s = opaque;
 665
 666     return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
 667 }
 668
 669 static void cmos_mm_writeb (void *opaque,
 670                             target_phys_addr_t addr, uint32_t value)
 671 {
 672     RTCState *s = opaque;
 673
 674     cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 675 }
 676
 677 static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
 678 {
 679     RTCState *s = opaque;
 680     uint32_t val;
 681
 682     val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 683 #ifdef TARGET_WORDS_BIGENDIAN
 684     val = bswap16(val);
 685 #endif
 686     return val;
 687 }
 688
 689 static void cmos_mm_writew (void *opaque,
 690                             target_phys_addr_t addr, uint32_t value)
 691 {
 692     RTCState *s = opaque;
 693 #ifdef TARGET_WORDS_BIGENDIAN
 694     value = bswap16(value);
 695 #endif
 696     cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 697 }
 698
 699 static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
 700 {
 701     RTCState *s = opaque;
 702     uint32_t val;
 703
 704     val = cmos_ioport_read(s, addr >> s->it_shift);
 705 #ifdef TARGET_WORDS_BIGENDIAN
 706     val = bswap32(val);
 707 #endif
 708     return val;
 709 }
 710
 711 static void cmos_mm_writel (void *opaque,
 712                             target_phys_addr_t addr, uint32_t value)
 713 {
 714     RTCState *s = opaque;
 715 #ifdef TARGET_WORDS_BIGENDIAN
 716     value = bswap32(value);
 717 #endif
 718     cmos_ioport_write(s, addr >> s->it_shift, value);
 719 }
 720
 721 static CPUReadMemoryFunc * const rtc_mm_read[] = {
 722     &cmos_mm_readb,
 723     &cmos_mm_readw,
 724     &cmos_mm_readl,
 725 };
 726
 727 static CPUWriteMemoryFunc * const rtc_mm_write[] = {
 728     &cmos_mm_writeb,
 729     &cmos_mm_writew,
 730     &cmos_mm_writel,
 731 };
 732
 733 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
 734                       int base_year)
 735 {
 736     RTCState *s;
 737     int io_memory;
 738
 739     s = qemu_mallocz(sizeof(RTCState));
 740
 741     s->irq = irq;
 742     s->cmos_data[RTC_REG_A] = 0x26;
 743     s->cmos_data[RTC_REG_B] = 0x02;
 744     s->cmos_data[RTC_REG_C] = 0x00;
 745     s->cmos_data[RTC_REG_D] = 0x80;
 746
 747     s->base_year = base_year;
 748     rtc_set_date_from_host(s);
 749
 750     s->periodic_timer = qemu_new_timer(vm_clock,
 751                                        rtc_periodic_timer, s);
 752     s->second_timer = qemu_new_timer(vm_clock,
 753                                      rtc_update_second, s);
 754     s->second_timer2 = qemu_new_timer(vm_clock,
 755                                       rtc_update_second2, s);
 756
 757     s->next_second_time = qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 99) / 100;
 758     qemu_mod_timer(s->second_timer2, s->next_second_time);
 759
 760     io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s);
 761     cpu_register_physical_memory(base, 2 << it_shift, io_memory);
 762
 763     register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
 764 #ifdef TARGET_I386
 765     if (rtc_td_hack)
 766         register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
 767 #endif
 768     qemu_register_reset(rtc_reset, s);
 769     return s;
 770 }