hw/milkymist-minimac2.c

   1 /*
   2  *  QEMU model of the Milkymist minimac2 block.
   3  *
   4  *  Copyright (c) 2011 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   not available yet
  22  *
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/sysbus.h"
  27 #include "trace.h"
  28 #include "net/net.h"
  29 #include "qemu/error-report.h"
  30 #include "hw/qdev-addr.h"
  31
  32 #include <zlib.h>
  33
  34 enum {
  35     R_SETUP = 0,
  36     R_MDIO,
  37     R_STATE0,
  38     R_COUNT0,
  39     R_STATE1,
  40     R_COUNT1,
  41     R_TXCOUNT,
  42     R_MAX
  43 };
  44
  45 enum {
  46     SETUP_PHY_RST = (1<<0),
  47 };
  48
  49 enum {
  50     MDIO_DO  = (1<<0),
  51     MDIO_DI  = (1<<1),
  52     MDIO_OE  = (1<<2),
  53     MDIO_CLK = (1<<3),
  54 };
  55
  56 enum {
  57     STATE_EMPTY   = 0,
  58     STATE_LOADED  = 1,
  59     STATE_PENDING = 2,
  60 };
  61
  62 enum {
  63     MDIO_OP_WRITE = 1,
  64     MDIO_OP_READ  = 2,
  65 };
  66
  67 enum mdio_state {
  68     MDIO_STATE_IDLE,
  69     MDIO_STATE_READING,
  70     MDIO_STATE_WRITING,
  71 };
  72
  73 enum {
  74     R_PHY_ID1  = 2,
  75     R_PHY_ID2  = 3,
  76     R_PHY_MAX  = 32
  77 };
  78
  79 #define MINIMAC2_MTU 1530
  80 #define MINIMAC2_BUFFER_SIZE 2048
  81
  82 struct MilkymistMinimac2MdioState {
  83     int last_clk;
  84     int count;
  85     uint32_t data;
  86     uint16_t data_out;
  87     int state;
  88
  89     uint8_t phy_addr;
  90     uint8_t reg_addr;
  91 };
  92 typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
  93
  94 struct MilkymistMinimac2State {
  95     SysBusDevice busdev;
  96     NICState *nic;
  97     NICConf conf;
  98     char *phy_model;
  99     MemoryRegion buffers;
 100     MemoryRegion regs_region;
 101
 102     qemu_irq rx_irq;
 103     qemu_irq tx_irq;
 104
 105     uint32_t regs[R_MAX];
 106
 107     MilkymistMinimac2MdioState mdio;
 108
 109     uint16_t phy_regs[R_PHY_MAX];
 110
 111     uint8_t *rx0_buf;
 112     uint8_t *rx1_buf;
 113     uint8_t *tx_buf;
 114 };
 115 typedef struct MilkymistMinimac2State MilkymistMinimac2State;
 116
 117 static const uint8_t preamble_sfd[] = {
 118         0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
 119 };
 120
 121 static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
 122         uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
 123 {
 124     trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
 125
 126     /* nop */
 127 }
 128
 129 static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
 130         uint8_t phy_addr, uint8_t reg_addr)
 131 {
 132     uint16_t r = s->phy_regs[reg_addr];
 133
 134     trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
 135
 136     return r;
 137 }
 138
 139 static void minimac2_update_mdio(MilkymistMinimac2State *s)
 140 {
 141     MilkymistMinimac2MdioState *m = &s->mdio;
 142
 143     /* detect rising clk edge */
 144     if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
 145         /* shift data in */
 146         int bit = ((s->regs[R_MDIO] & MDIO_DO)
 147                    && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
 148         m->data = (m->data << 1) | bit;
 149
 150         /* check for sync */
 151         if (m->data == 0xffffffff) {
 152             m->count = 32;
 153         }
 154
 155         if (m->count == 16) {
 156             uint8_t start = (m->data >> 14) & 0x3;
 157             uint8_t op = (m->data >> 12) & 0x3;
 158             uint8_t ta = (m->data) & 0x3;
 159
 160             if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
 161                 m->state = MDIO_STATE_WRITING;
 162             } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
 163                 m->state = MDIO_STATE_READING;
 164             } else {
 165                 m->state = MDIO_STATE_IDLE;
 166             }
 167
 168             if (m->state != MDIO_STATE_IDLE) {
 169                 m->phy_addr = (m->data >> 7) & 0x1f;
 170                 m->reg_addr = (m->data >> 2) & 0x1f;
 171             }
 172
 173             if (m->state == MDIO_STATE_READING) {
 174                 m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
 175                         m->reg_addr);
 176             }
 177         }
 178
 179         if (m->count < 16 && m->state == MDIO_STATE_READING) {
 180             int bit = (m->data_out & 0x8000) ? 1 : 0;
 181             m->data_out <<= 1;
 182
 183             if (bit) {
 184                 s->regs[R_MDIO] |= MDIO_DI;
 185             } else {
 186                 s->regs[R_MDIO] &= ~MDIO_DI;
 187             }
 188         }
 189
 190         if (m->count == 0 && m->state) {
 191             if (m->state == MDIO_STATE_WRITING) {
 192                 uint16_t data = m->data & 0xffff;
 193                 minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
 194             }
 195             m->state = MDIO_STATE_IDLE;
 196         }
 197         m->count--;
 198     }
 199
 200     m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
 201 }
 202
 203 static size_t assemble_frame(uint8_t *buf, size_t size,
 204         const uint8_t *payload, size_t payload_size)
 205 {
 206     uint32_t crc;
 207
 208     if (size < payload_size + 12) {
 209         error_report("milkymist_minimac2: received too big ethernet frame");
 210         return 0;
 211     }
 212
 213     /* prepend preamble and sfd */
 214     memcpy(buf, preamble_sfd, 8);
 215
 216     /* now copy the payload */
 217     memcpy(buf + 8, payload, payload_size);
 218
 219     /* pad frame if needed */
 220     if (payload_size < 60) {
 221         memset(buf + payload_size + 8, 0, 60 - payload_size);
 222         payload_size = 60;
 223     }
 224
 225     /* append fcs */
 226     crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
 227     memcpy(buf + payload_size + 8, &crc, 4);
 228
 229     return payload_size + 12;
 230 }
 231
 232 static void minimac2_tx(MilkymistMinimac2State *s)
 233 {
 234     uint32_t txcount = s->regs[R_TXCOUNT];
 235     uint8_t *buf = s->tx_buf;
 236
 237     if (txcount < 64) {
 238         error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
 239                 txcount, 64);
 240         goto err;
 241     }
 242
 243     if (txcount > MINIMAC2_MTU) {
 244         error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
 245                 txcount, MINIMAC2_MTU);
 246         goto err;
 247     }
 248
 249     if (memcmp(buf, preamble_sfd, 8) != 0) {
 250         error_report("milkymist_minimac2: frame doesn't contain the preamble "
 251                 "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
 252                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
 253         goto err;
 254     }
 255
 256     trace_milkymist_minimac2_tx_frame(txcount - 12);
 257
 258     /* send packet, skipping preamble and sfd */
 259     qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
 260
 261     s->regs[R_TXCOUNT] = 0;
 262
 263 err:
 264     trace_milkymist_minimac2_pulse_irq_tx();
 265     qemu_irq_pulse(s->tx_irq);
 266 }
 267
 268 static void update_rx_interrupt(MilkymistMinimac2State *s)
 269 {
 270     if (s->regs[R_STATE0] == STATE_PENDING
 271             || s->regs[R_STATE1] == STATE_PENDING) {
 272         trace_milkymist_minimac2_raise_irq_rx();
 273         qemu_irq_raise(s->rx_irq);
 274     } else {
 275         trace_milkymist_minimac2_lower_irq_rx();
 276         qemu_irq_lower(s->rx_irq);
 277     }
 278 }
 279
 280 static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 281 {
 282     MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 283
 284     uint32_t r_count;
 285     uint32_t r_state;
 286     uint8_t *rx_buf;
 287
 288     size_t frame_size;
 289
 290     trace_milkymist_minimac2_rx_frame(buf, size);
 291
 292     /* choose appropriate slot */
 293     if (s->regs[R_STATE0] == STATE_LOADED) {
 294         r_count = R_COUNT0;
 295         r_state = R_STATE0;
 296         rx_buf = s->rx0_buf;
 297     } else if (s->regs[R_STATE1] == STATE_LOADED) {
 298         r_count = R_COUNT1;
 299         r_state = R_STATE1;
 300         rx_buf = s->rx1_buf;
 301     } else {
 302         trace_milkymist_minimac2_drop_rx_frame(buf);
 303         return size;
 304     }
 305
 306     /* assemble frame */
 307     frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
 308
 309     if (frame_size == 0) {
 310         return size;
 311     }
 312
 313     trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
 314
 315     /* update slot */
 316     s->regs[r_count] = frame_size;
 317     s->regs[r_state] = STATE_PENDING;
 318
 319     update_rx_interrupt(s);
 320
 321     return size;
 322 }
 323
 324 static uint64_t
 325 minimac2_read(void *opaque, hwaddr addr, unsigned size)
 326 {
 327     MilkymistMinimac2State *s = opaque;
 328     uint32_t r = 0;
 329
 330     addr >>= 2;
 331     switch (addr) {
 332     case R_SETUP:
 333     case R_MDIO:
 334     case R_STATE0:
 335     case R_COUNT0:
 336     case R_STATE1:
 337     case R_COUNT1:
 338     case R_TXCOUNT:
 339         r = s->regs[addr];
 340         break;
 341
 342     default:
 343         error_report("milkymist_minimac2: read access to unknown register 0x"
 344                 TARGET_FMT_plx, addr << 2);
 345         break;
 346     }
 347
 348     trace_milkymist_minimac2_memory_read(addr << 2, r);
 349
 350     return r;
 351 }
 352
 353 static void
 354 minimac2_write(void *opaque, hwaddr addr, uint64_t value,
 355                unsigned size)
 356 {
 357     MilkymistMinimac2State *s = opaque;
 358
 359     trace_milkymist_minimac2_memory_read(addr, value);
 360
 361     addr >>= 2;
 362     switch (addr) {
 363     case R_MDIO:
 364     {
 365         /* MDIO_DI is read only */
 366         int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
 367         s->regs[R_MDIO] = value;
 368         if (mdio_di) {
 369             s->regs[R_MDIO] |= mdio_di;
 370         } else {
 371             s->regs[R_MDIO] &= ~mdio_di;
 372         }
 373
 374         minimac2_update_mdio(s);
 375     } break;
 376     case R_TXCOUNT:
 377         s->regs[addr] = value;
 378         if (value > 0) {
 379             minimac2_tx(s);
 380         }
 381         break;
 382     case R_STATE0:
 383     case R_STATE1:
 384         s->regs[addr] = value;
 385         update_rx_interrupt(s);
 386         break;
 387     case R_SETUP:
 388     case R_COUNT0:
 389     case R_COUNT1:
 390         s->regs[addr] = value;
 391         break;
 392
 393     default:
 394         error_report("milkymist_minimac2: write access to unknown register 0x"
 395                 TARGET_FMT_plx, addr << 2);
 396         break;
 397     }
 398 }
 399
 400 static const MemoryRegionOps minimac2_ops = {
 401     .read = minimac2_read,
 402     .write = minimac2_write,
 403     .valid = {
 404         .min_access_size = 4,
 405         .max_access_size = 4,
 406     },
 407     .endianness = DEVICE_NATIVE_ENDIAN,
 408 };
 409
 410 static int minimac2_can_rx(NetClientState *nc)
 411 {
 412     MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 413
 414     if (s->regs[R_STATE0] == STATE_LOADED) {
 415         return 1;
 416     }
 417     if (s->regs[R_STATE1] == STATE_LOADED) {
 418         return 1;
 419     }
 420
 421     return 0;
 422 }
 423
 424 static void minimac2_cleanup(NetClientState *nc)
 425 {
 426     MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 427
 428     s->nic = NULL;
 429 }
 430
 431 static void milkymist_minimac2_reset(DeviceState *d)
 432 {
 433     MilkymistMinimac2State *s =
 434             container_of(d, MilkymistMinimac2State, busdev.qdev);
 435     int i;
 436
 437     for (i = 0; i < R_MAX; i++) {
 438         s->regs[i] = 0;
 439     }
 440     for (i = 0; i < R_PHY_MAX; i++) {
 441         s->phy_regs[i] = 0;
 442     }
 443
 444     /* defaults */
 445     s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
 446     s->phy_regs[R_PHY_ID2] = 0x161a;
 447 }
 448
 449 static NetClientInfo net_milkymist_minimac2_info = {
 450     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 451     .size = sizeof(NICState),
 452     .can_receive = minimac2_can_rx,
 453     .receive = minimac2_rx,
 454     .cleanup = minimac2_cleanup,
 455 };
 456
 457 static int milkymist_minimac2_init(SysBusDevice *dev)
 458 {
 459     MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev);
 460     size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
 461
 462     sysbus_init_irq(dev, &s->rx_irq);
 463     sysbus_init_irq(dev, &s->tx_irq);
 464
 465     memory_region_init_io(&s->regs_region, &minimac2_ops, s,
 466                           "milkymist-minimac2", R_MAX * 4);
 467     sysbus_init_mmio(dev, &s->regs_region);
 468
 469     /* register buffers memory */
 470     memory_region_init_ram(&s->buffers, "milkymist-minimac2.buffers",
 471                            buffers_size);
 472     vmstate_register_ram_global(&s->buffers);
 473     s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
 474     s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
 475     s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
 476
 477     sysbus_init_mmio(dev, &s->buffers);
 478
 479     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 480     s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
 481                           object_get_typename(OBJECT(dev)), dev->qdev.id, s);
 482     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 483
 484     return 0;
 485 }
 486
 487 static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
 488     .name = "milkymist-minimac2-mdio",
 489     .version_id = 1,
 490     .minimum_version_id = 1,
 491     .minimum_version_id_old = 1,
 492     .fields      = (VMStateField[]) {
 493         VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
 494         VMSTATE_INT32(count, MilkymistMinimac2MdioState),
 495         VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
 496         VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
 497         VMSTATE_INT32(state, MilkymistMinimac2MdioState),
 498         VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
 499         VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
 500         VMSTATE_END_OF_LIST()
 501     }
 502 };
 503
 504 static const VMStateDescription vmstate_milkymist_minimac2 = {
 505     .name = "milkymist-minimac2",
 506     .version_id = 1,
 507     .minimum_version_id = 1,
 508     .minimum_version_id_old = 1,
 509     .fields      = (VMStateField[]) {
 510         VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
 511         VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
 512         VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
 513                 vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
 514         VMSTATE_END_OF_LIST()
 515     }
 516 };
 517
 518 static Property milkymist_minimac2_properties[] = {
 519     DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
 520     DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
 521     DEFINE_PROP_END_OF_LIST(),
 522 };
 523
 524 static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
 525 {
 526     DeviceClass *dc = DEVICE_CLASS(klass);
 527     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 528
 529     k->init = milkymist_minimac2_init;
 530     dc->reset = milkymist_minimac2_reset;
 531     dc->vmsd = &vmstate_milkymist_minimac2;
 532     dc->props = milkymist_minimac2_properties;
 533 }
 534
 535 static const TypeInfo milkymist_minimac2_info = {
 536     .name          = "milkymist-minimac2",
 537     .parent        = TYPE_SYS_BUS_DEVICE,
 538     .instance_size = sizeof(MilkymistMinimac2State),
 539     .class_init    = milkymist_minimac2_class_init,
 540 };
 541
 542 static void milkymist_minimac2_register_types(void)
 543 {
 544     type_register_static(&milkymist_minimac2_info);
 545 }
 546
 547 type_init(milkymist_minimac2_register_types)