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PPC: Make BookE FIT/WDT timers more lazy
[qemu.git] / hw / mips / gt64xxx_pci.c
1 /*
2 * QEMU GT64120 PCI host
3 *
4 * Copyright (c) 2006,2007 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "hw/hw.h"
26 #include "hw/mips/mips.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "hw/i386/pc.h"
30 #include "exec/address-spaces.h"
31
32 //#define DEBUG
33
34 #ifdef DEBUG
35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
36 #else
37 #define DPRINTF(fmt, ...)
38 #endif
39
40 #define GT_REGS (0x1000 >> 2)
41
42 /* CPU Configuration */
43 #define GT_CPU (0x000 >> 2)
44 #define GT_MULTI (0x120 >> 2)
45
46 /* CPU Address Decode */
47 #define GT_SCS10LD (0x008 >> 2)
48 #define GT_SCS10HD (0x010 >> 2)
49 #define GT_SCS32LD (0x018 >> 2)
50 #define GT_SCS32HD (0x020 >> 2)
51 #define GT_CS20LD (0x028 >> 2)
52 #define GT_CS20HD (0x030 >> 2)
53 #define GT_CS3BOOTLD (0x038 >> 2)
54 #define GT_CS3BOOTHD (0x040 >> 2)
55 #define GT_PCI0IOLD (0x048 >> 2)
56 #define GT_PCI0IOHD (0x050 >> 2)
57 #define GT_PCI0M0LD (0x058 >> 2)
58 #define GT_PCI0M0HD (0x060 >> 2)
59 #define GT_PCI0M1LD (0x080 >> 2)
60 #define GT_PCI0M1HD (0x088 >> 2)
61 #define GT_PCI1IOLD (0x090 >> 2)
62 #define GT_PCI1IOHD (0x098 >> 2)
63 #define GT_PCI1M0LD (0x0a0 >> 2)
64 #define GT_PCI1M0HD (0x0a8 >> 2)
65 #define GT_PCI1M1LD (0x0b0 >> 2)
66 #define GT_PCI1M1HD (0x0b8 >> 2)
67 #define GT_ISD (0x068 >> 2)
68
69 #define GT_SCS10AR (0x0d0 >> 2)
70 #define GT_SCS32AR (0x0d8 >> 2)
71 #define GT_CS20R (0x0e0 >> 2)
72 #define GT_CS3BOOTR (0x0e8 >> 2)
73
74 #define GT_PCI0IOREMAP (0x0f0 >> 2)
75 #define GT_PCI0M0REMAP (0x0f8 >> 2)
76 #define GT_PCI0M1REMAP (0x100 >> 2)
77 #define GT_PCI1IOREMAP (0x108 >> 2)
78 #define GT_PCI1M0REMAP (0x110 >> 2)
79 #define GT_PCI1M1REMAP (0x118 >> 2)
80
81 /* CPU Error Report */
82 #define GT_CPUERR_ADDRLO (0x070 >> 2)
83 #define GT_CPUERR_ADDRHI (0x078 >> 2)
84 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
85 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
86 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
87
88 /* CPU Sync Barrier */
89 #define GT_PCI0SYNC (0x0c0 >> 2)
90 #define GT_PCI1SYNC (0x0c8 >> 2)
91
92 /* SDRAM and Device Address Decode */
93 #define GT_SCS0LD (0x400 >> 2)
94 #define GT_SCS0HD (0x404 >> 2)
95 #define GT_SCS1LD (0x408 >> 2)
96 #define GT_SCS1HD (0x40c >> 2)
97 #define GT_SCS2LD (0x410 >> 2)
98 #define GT_SCS2HD (0x414 >> 2)
99 #define GT_SCS3LD (0x418 >> 2)
100 #define GT_SCS3HD (0x41c >> 2)
101 #define GT_CS0LD (0x420 >> 2)
102 #define GT_CS0HD (0x424 >> 2)
103 #define GT_CS1LD (0x428 >> 2)
104 #define GT_CS1HD (0x42c >> 2)
105 #define GT_CS2LD (0x430 >> 2)
106 #define GT_CS2HD (0x434 >> 2)
107 #define GT_CS3LD (0x438 >> 2)
108 #define GT_CS3HD (0x43c >> 2)
109 #define GT_BOOTLD (0x440 >> 2)
110 #define GT_BOOTHD (0x444 >> 2)
111 #define GT_ADERR (0x470 >> 2)
112
113 /* SDRAM Configuration */
114 #define GT_SDRAM_CFG (0x448 >> 2)
115 #define GT_SDRAM_OPMODE (0x474 >> 2)
116 #define GT_SDRAM_BM (0x478 >> 2)
117 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
118
119 /* SDRAM Parameters */
120 #define GT_SDRAM_B0 (0x44c >> 2)
121 #define GT_SDRAM_B1 (0x450 >> 2)
122 #define GT_SDRAM_B2 (0x454 >> 2)
123 #define GT_SDRAM_B3 (0x458 >> 2)
124
125 /* Device Parameters */
126 #define GT_DEV_B0 (0x45c >> 2)
127 #define GT_DEV_B1 (0x460 >> 2)
128 #define GT_DEV_B2 (0x464 >> 2)
129 #define GT_DEV_B3 (0x468 >> 2)
130 #define GT_DEV_BOOT (0x46c >> 2)
131
132 /* ECC */
133 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
134 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
135 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
136 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
137 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
138
139 /* DMA Record */
140 #define GT_DMA0_CNT (0x800 >> 2)
141 #define GT_DMA1_CNT (0x804 >> 2)
142 #define GT_DMA2_CNT (0x808 >> 2)
143 #define GT_DMA3_CNT (0x80c >> 2)
144 #define GT_DMA0_SA (0x810 >> 2)
145 #define GT_DMA1_SA (0x814 >> 2)
146 #define GT_DMA2_SA (0x818 >> 2)
147 #define GT_DMA3_SA (0x81c >> 2)
148 #define GT_DMA0_DA (0x820 >> 2)
149 #define GT_DMA1_DA (0x824 >> 2)
150 #define GT_DMA2_DA (0x828 >> 2)
151 #define GT_DMA3_DA (0x82c >> 2)
152 #define GT_DMA0_NEXT (0x830 >> 2)
153 #define GT_DMA1_NEXT (0x834 >> 2)
154 #define GT_DMA2_NEXT (0x838 >> 2)
155 #define GT_DMA3_NEXT (0x83c >> 2)
156 #define GT_DMA0_CUR (0x870 >> 2)
157 #define GT_DMA1_CUR (0x874 >> 2)
158 #define GT_DMA2_CUR (0x878 >> 2)
159 #define GT_DMA3_CUR (0x87c >> 2)
160
161 /* DMA Channel Control */
162 #define GT_DMA0_CTRL (0x840 >> 2)
163 #define GT_DMA1_CTRL (0x844 >> 2)
164 #define GT_DMA2_CTRL (0x848 >> 2)
165 #define GT_DMA3_CTRL (0x84c >> 2)
166
167 /* DMA Arbiter */
168 #define GT_DMA_ARB (0x860 >> 2)
169
170 /* Timer/Counter */
171 #define GT_TC0 (0x850 >> 2)
172 #define GT_TC1 (0x854 >> 2)
173 #define GT_TC2 (0x858 >> 2)
174 #define GT_TC3 (0x85c >> 2)
175 #define GT_TC_CONTROL (0x864 >> 2)
176
177 /* PCI Internal */
178 #define GT_PCI0_CMD (0xc00 >> 2)
179 #define GT_PCI0_TOR (0xc04 >> 2)
180 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
181 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
182 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
183 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
184 #define GT_PCI1_IACK (0xc30 >> 2)
185 #define GT_PCI0_IACK (0xc34 >> 2)
186 #define GT_PCI0_BARE (0xc3c >> 2)
187 #define GT_PCI0_PREFMBR (0xc40 >> 2)
188 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
189 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
190 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
191 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
192 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
193 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
194 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
195 #define GT_PCI1_CMD (0xc80 >> 2)
196 #define GT_PCI1_TOR (0xc84 >> 2)
197 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
198 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
199 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
200 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
201 #define GT_PCI1_BARE (0xcbc >> 2)
202 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
203 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
204 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
205 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
206 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
207 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
208 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
209 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
210 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
211 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
212 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
213 #define GT_PCI0_CFGDATA (0xcfc >> 2)
214
215 /* Interrupts */
216 #define GT_INTRCAUSE (0xc18 >> 2)
217 #define GT_INTRMASK (0xc1c >> 2)
218 #define GT_PCI0_ICMASK (0xc24 >> 2)
219 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
220 #define GT_CPU_INTSEL (0xc70 >> 2)
221 #define GT_PCI0_INTSEL (0xc74 >> 2)
222 #define GT_HINTRCAUSE (0xc98 >> 2)
223 #define GT_HINTRMASK (0xc9c >> 2)
224 #define GT_PCI0_HICMASK (0xca4 >> 2)
225 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
226
227 #define PCI_MAPPING_ENTRY(regname) \
228 hwaddr regname ##_start; \
229 hwaddr regname ##_length; \
230 MemoryRegion regname ##_mem
231
232 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
233
234 #define GT64120_PCI_HOST_BRIDGE(obj) \
235 OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
236
237 typedef struct GT64120State {
238 PCIHostState parent_obj;
239
240 uint32_t regs[GT_REGS];
241 PCI_MAPPING_ENTRY(PCI0IO);
242 PCI_MAPPING_ENTRY(ISD);
243 } GT64120State;
244
245 /* Adjust range to avoid touching space which isn't mappable via PCI */
246 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
247 0x1fc00000 - 0x1fd00000 */
248 static void check_reserved_space (hwaddr *start,
249 hwaddr *length)
250 {
251 hwaddr begin = *start;
252 hwaddr end = *start + *length;
253
254 if (end >= 0x1e000000LL && end < 0x1f100000LL)
255 end = 0x1e000000LL;
256 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
257 begin = 0x1f100000LL;
258 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
259 end = 0x1fc00000LL;
260 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
261 begin = 0x1fd00000LL;
262 /* XXX: This is broken when a reserved range splits the requested range */
263 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
264 end = 0x1e000000LL;
265 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
266 end = 0x1fc00000LL;
267
268 *start = begin;
269 *length = end - begin;
270 }
271
272 static void gt64120_isd_mapping(GT64120State *s)
273 {
274 hwaddr start = s->regs[GT_ISD] << 21;
275 hwaddr length = 0x1000;
276
277 if (s->ISD_length) {
278 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
279 }
280 check_reserved_space(&start, &length);
281 length = 0x1000;
282 /* Map new address */
283 DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx
284 " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n",
285 s->ISD_length, s->ISD_start, length, start);
286 s->ISD_start = start;
287 s->ISD_length = length;
288 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
289 }
290
291 static void gt64120_pci_mapping(GT64120State *s)
292 {
293 /* Update IO mapping */
294 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
295 {
296 /* Unmap old IO address */
297 if (s->PCI0IO_length)
298 {
299 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
300 memory_region_destroy(&s->PCI0IO_mem);
301 }
302 /* Map new IO address */
303 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
304 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
305 isa_mem_base = s->PCI0IO_start;
306 if (s->PCI0IO_length) {
307 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "isa_mmio",
308 get_system_io(), 0, s->PCI0IO_length);
309 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
310 &s->PCI0IO_mem);
311 }
312 }
313 }
314
315 static void gt64120_writel (void *opaque, hwaddr addr,
316 uint64_t val, unsigned size)
317 {
318 GT64120State *s = opaque;
319 PCIHostState *phb = PCI_HOST_BRIDGE(s);
320 uint32_t saddr;
321
322 if (!(s->regs[GT_CPU] & 0x00001000))
323 val = bswap32(val);
324
325 saddr = (addr & 0xfff) >> 2;
326 switch (saddr) {
327
328 /* CPU Configuration */
329 case GT_CPU:
330 s->regs[GT_CPU] = val;
331 break;
332 case GT_MULTI:
333 /* Read-only register as only one GT64xxx is present on the CPU bus */
334 break;
335
336 /* CPU Address Decode */
337 case GT_PCI0IOLD:
338 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
339 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
340 gt64120_pci_mapping(s);
341 break;
342 case GT_PCI0M0LD:
343 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
344 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
345 break;
346 case GT_PCI0M1LD:
347 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
348 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
349 break;
350 case GT_PCI1IOLD:
351 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
352 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
353 break;
354 case GT_PCI1M0LD:
355 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
356 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
357 break;
358 case GT_PCI1M1LD:
359 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
360 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
361 break;
362 case GT_PCI0IOHD:
363 s->regs[saddr] = val & 0x0000007f;
364 gt64120_pci_mapping(s);
365 break;
366 case GT_PCI0M0HD:
367 case GT_PCI0M1HD:
368 case GT_PCI1IOHD:
369 case GT_PCI1M0HD:
370 case GT_PCI1M1HD:
371 s->regs[saddr] = val & 0x0000007f;
372 break;
373 case GT_ISD:
374 s->regs[saddr] = val & 0x00007fff;
375 gt64120_isd_mapping(s);
376 break;
377
378 case GT_PCI0IOREMAP:
379 case GT_PCI0M0REMAP:
380 case GT_PCI0M1REMAP:
381 case GT_PCI1IOREMAP:
382 case GT_PCI1M0REMAP:
383 case GT_PCI1M1REMAP:
384 s->regs[saddr] = val & 0x000007ff;
385 break;
386
387 /* CPU Error Report */
388 case GT_CPUERR_ADDRLO:
389 case GT_CPUERR_ADDRHI:
390 case GT_CPUERR_DATALO:
391 case GT_CPUERR_DATAHI:
392 case GT_CPUERR_PARITY:
393 /* Read-only registers, do nothing */
394 break;
395
396 /* CPU Sync Barrier */
397 case GT_PCI0SYNC:
398 case GT_PCI1SYNC:
399 /* Read-only registers, do nothing */
400 break;
401
402 /* SDRAM and Device Address Decode */
403 case GT_SCS0LD:
404 case GT_SCS0HD:
405 case GT_SCS1LD:
406 case GT_SCS1HD:
407 case GT_SCS2LD:
408 case GT_SCS2HD:
409 case GT_SCS3LD:
410 case GT_SCS3HD:
411 case GT_CS0LD:
412 case GT_CS0HD:
413 case GT_CS1LD:
414 case GT_CS1HD:
415 case GT_CS2LD:
416 case GT_CS2HD:
417 case GT_CS3LD:
418 case GT_CS3HD:
419 case GT_BOOTLD:
420 case GT_BOOTHD:
421 case GT_ADERR:
422 /* SDRAM Configuration */
423 case GT_SDRAM_CFG:
424 case GT_SDRAM_OPMODE:
425 case GT_SDRAM_BM:
426 case GT_SDRAM_ADDRDECODE:
427 /* Accept and ignore SDRAM interleave configuration */
428 s->regs[saddr] = val;
429 break;
430
431 /* Device Parameters */
432 case GT_DEV_B0:
433 case GT_DEV_B1:
434 case GT_DEV_B2:
435 case GT_DEV_B3:
436 case GT_DEV_BOOT:
437 /* Not implemented */
438 DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
439 break;
440
441 /* ECC */
442 case GT_ECC_ERRDATALO:
443 case GT_ECC_ERRDATAHI:
444 case GT_ECC_MEM:
445 case GT_ECC_CALC:
446 case GT_ECC_ERRADDR:
447 /* Read-only registers, do nothing */
448 break;
449
450 /* DMA Record */
451 case GT_DMA0_CNT:
452 case GT_DMA1_CNT:
453 case GT_DMA2_CNT:
454 case GT_DMA3_CNT:
455 case GT_DMA0_SA:
456 case GT_DMA1_SA:
457 case GT_DMA2_SA:
458 case GT_DMA3_SA:
459 case GT_DMA0_DA:
460 case GT_DMA1_DA:
461 case GT_DMA2_DA:
462 case GT_DMA3_DA:
463 case GT_DMA0_NEXT:
464 case GT_DMA1_NEXT:
465 case GT_DMA2_NEXT:
466 case GT_DMA3_NEXT:
467 case GT_DMA0_CUR:
468 case GT_DMA1_CUR:
469 case GT_DMA2_CUR:
470 case GT_DMA3_CUR:
471 /* Not implemented */
472 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
473 break;
474
475 /* DMA Channel Control */
476 case GT_DMA0_CTRL:
477 case GT_DMA1_CTRL:
478 case GT_DMA2_CTRL:
479 case GT_DMA3_CTRL:
480 /* Not implemented */
481 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
482 break;
483
484 /* DMA Arbiter */
485 case GT_DMA_ARB:
486 /* Not implemented */
487 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
488 break;
489
490 /* Timer/Counter */
491 case GT_TC0:
492 case GT_TC1:
493 case GT_TC2:
494 case GT_TC3:
495 case GT_TC_CONTROL:
496 /* Not implemented */
497 DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
498 break;
499
500 /* PCI Internal */
501 case GT_PCI0_CMD:
502 case GT_PCI1_CMD:
503 s->regs[saddr] = val & 0x0401fc0f;
504 break;
505 case GT_PCI0_TOR:
506 case GT_PCI0_BS_SCS10:
507 case GT_PCI0_BS_SCS32:
508 case GT_PCI0_BS_CS20:
509 case GT_PCI0_BS_CS3BT:
510 case GT_PCI1_IACK:
511 case GT_PCI0_IACK:
512 case GT_PCI0_BARE:
513 case GT_PCI0_PREFMBR:
514 case GT_PCI0_SCS10_BAR:
515 case GT_PCI0_SCS32_BAR:
516 case GT_PCI0_CS20_BAR:
517 case GT_PCI0_CS3BT_BAR:
518 case GT_PCI0_SSCS10_BAR:
519 case GT_PCI0_SSCS32_BAR:
520 case GT_PCI0_SCS3BT_BAR:
521 case GT_PCI1_TOR:
522 case GT_PCI1_BS_SCS10:
523 case GT_PCI1_BS_SCS32:
524 case GT_PCI1_BS_CS20:
525 case GT_PCI1_BS_CS3BT:
526 case GT_PCI1_BARE:
527 case GT_PCI1_PREFMBR:
528 case GT_PCI1_SCS10_BAR:
529 case GT_PCI1_SCS32_BAR:
530 case GT_PCI1_CS20_BAR:
531 case GT_PCI1_CS3BT_BAR:
532 case GT_PCI1_SSCS10_BAR:
533 case GT_PCI1_SSCS32_BAR:
534 case GT_PCI1_SCS3BT_BAR:
535 case GT_PCI1_CFGADDR:
536 case GT_PCI1_CFGDATA:
537 /* not implemented */
538 break;
539 case GT_PCI0_CFGADDR:
540 phb->config_reg = val & 0x80fffffc;
541 break;
542 case GT_PCI0_CFGDATA:
543 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
544 val = bswap32(val);
545 }
546 if (phb->config_reg & (1u << 31)) {
547 pci_data_write(phb->bus, phb->config_reg, val, 4);
548 }
549 break;
550
551 /* Interrupts */
552 case GT_INTRCAUSE:
553 /* not really implemented */
554 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
555 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
556 DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
557 break;
558 case GT_INTRMASK:
559 s->regs[saddr] = val & 0x3c3ffffe;
560 DPRINTF("INTRMASK %" PRIx64 "\n", val);
561 break;
562 case GT_PCI0_ICMASK:
563 s->regs[saddr] = val & 0x03fffffe;
564 DPRINTF("ICMASK %" PRIx64 "\n", val);
565 break;
566 case GT_PCI0_SERR0MASK:
567 s->regs[saddr] = val & 0x0000003f;
568 DPRINTF("SERR0MASK %" PRIx64 "\n", val);
569 break;
570
571 /* Reserved when only PCI_0 is configured. */
572 case GT_HINTRCAUSE:
573 case GT_CPU_INTSEL:
574 case GT_PCI0_INTSEL:
575 case GT_HINTRMASK:
576 case GT_PCI0_HICMASK:
577 case GT_PCI1_SERR1MASK:
578 /* not implemented */
579 break;
580
581 /* SDRAM Parameters */
582 case GT_SDRAM_B0:
583 case GT_SDRAM_B1:
584 case GT_SDRAM_B2:
585 case GT_SDRAM_B3:
586 /* We don't simulate electrical parameters of the SDRAM.
587 Accept, but ignore the values. */
588 s->regs[saddr] = val;
589 break;
590
591 default:
592 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
593 break;
594 }
595 }
596
597 static uint64_t gt64120_readl (void *opaque,
598 hwaddr addr, unsigned size)
599 {
600 GT64120State *s = opaque;
601 PCIHostState *phb = PCI_HOST_BRIDGE(s);
602 uint32_t val;
603 uint32_t saddr;
604
605 saddr = (addr & 0xfff) >> 2;
606 switch (saddr) {
607
608 /* CPU Configuration */
609 case GT_MULTI:
610 /* Only one GT64xxx is present on the CPU bus, return
611 the initial value */
612 val = s->regs[saddr];
613 break;
614
615 /* CPU Error Report */
616 case GT_CPUERR_ADDRLO:
617 case GT_CPUERR_ADDRHI:
618 case GT_CPUERR_DATALO:
619 case GT_CPUERR_DATAHI:
620 case GT_CPUERR_PARITY:
621 /* Emulated memory has no error, always return the initial
622 values */
623 val = s->regs[saddr];
624 break;
625
626 /* CPU Sync Barrier */
627 case GT_PCI0SYNC:
628 case GT_PCI1SYNC:
629 /* Reading those register should empty all FIFO on the PCI
630 bus, which are not emulated. The return value should be
631 a random value that should be ignored. */
632 val = 0xc000ffee;
633 break;
634
635 /* ECC */
636 case GT_ECC_ERRDATALO:
637 case GT_ECC_ERRDATAHI:
638 case GT_ECC_MEM:
639 case GT_ECC_CALC:
640 case GT_ECC_ERRADDR:
641 /* Emulated memory has no error, always return the initial
642 values */
643 val = s->regs[saddr];
644 break;
645
646 case GT_CPU:
647 case GT_SCS10LD:
648 case GT_SCS10HD:
649 case GT_SCS32LD:
650 case GT_SCS32HD:
651 case GT_CS20LD:
652 case GT_CS20HD:
653 case GT_CS3BOOTLD:
654 case GT_CS3BOOTHD:
655 case GT_SCS10AR:
656 case GT_SCS32AR:
657 case GT_CS20R:
658 case GT_CS3BOOTR:
659 case GT_PCI0IOLD:
660 case GT_PCI0M0LD:
661 case GT_PCI0M1LD:
662 case GT_PCI1IOLD:
663 case GT_PCI1M0LD:
664 case GT_PCI1M1LD:
665 case GT_PCI0IOHD:
666 case GT_PCI0M0HD:
667 case GT_PCI0M1HD:
668 case GT_PCI1IOHD:
669 case GT_PCI1M0HD:
670 case GT_PCI1M1HD:
671 case GT_PCI0IOREMAP:
672 case GT_PCI0M0REMAP:
673 case GT_PCI0M1REMAP:
674 case GT_PCI1IOREMAP:
675 case GT_PCI1M0REMAP:
676 case GT_PCI1M1REMAP:
677 case GT_ISD:
678 val = s->regs[saddr];
679 break;
680 case GT_PCI0_IACK:
681 /* Read the IRQ number */
682 val = pic_read_irq(isa_pic);
683 break;
684
685 /* SDRAM and Device Address Decode */
686 case GT_SCS0LD:
687 case GT_SCS0HD:
688 case GT_SCS1LD:
689 case GT_SCS1HD:
690 case GT_SCS2LD:
691 case GT_SCS2HD:
692 case GT_SCS3LD:
693 case GT_SCS3HD:
694 case GT_CS0LD:
695 case GT_CS0HD:
696 case GT_CS1LD:
697 case GT_CS1HD:
698 case GT_CS2LD:
699 case GT_CS2HD:
700 case GT_CS3LD:
701 case GT_CS3HD:
702 case GT_BOOTLD:
703 case GT_BOOTHD:
704 case GT_ADERR:
705 val = s->regs[saddr];
706 break;
707
708 /* SDRAM Configuration */
709 case GT_SDRAM_CFG:
710 case GT_SDRAM_OPMODE:
711 case GT_SDRAM_BM:
712 case GT_SDRAM_ADDRDECODE:
713 val = s->regs[saddr];
714 break;
715
716 /* SDRAM Parameters */
717 case GT_SDRAM_B0:
718 case GT_SDRAM_B1:
719 case GT_SDRAM_B2:
720 case GT_SDRAM_B3:
721 /* We don't simulate electrical parameters of the SDRAM.
722 Just return the last written value. */
723 val = s->regs[saddr];
724 break;
725
726 /* Device Parameters */
727 case GT_DEV_B0:
728 case GT_DEV_B1:
729 case GT_DEV_B2:
730 case GT_DEV_B3:
731 case GT_DEV_BOOT:
732 val = s->regs[saddr];
733 break;
734
735 /* DMA Record */
736 case GT_DMA0_CNT:
737 case GT_DMA1_CNT:
738 case GT_DMA2_CNT:
739 case GT_DMA3_CNT:
740 case GT_DMA0_SA:
741 case GT_DMA1_SA:
742 case GT_DMA2_SA:
743 case GT_DMA3_SA:
744 case GT_DMA0_DA:
745 case GT_DMA1_DA:
746 case GT_DMA2_DA:
747 case GT_DMA3_DA:
748 case GT_DMA0_NEXT:
749 case GT_DMA1_NEXT:
750 case GT_DMA2_NEXT:
751 case GT_DMA3_NEXT:
752 case GT_DMA0_CUR:
753 case GT_DMA1_CUR:
754 case GT_DMA2_CUR:
755 case GT_DMA3_CUR:
756 val = s->regs[saddr];
757 break;
758
759 /* DMA Channel Control */
760 case GT_DMA0_CTRL:
761 case GT_DMA1_CTRL:
762 case GT_DMA2_CTRL:
763 case GT_DMA3_CTRL:
764 val = s->regs[saddr];
765 break;
766
767 /* DMA Arbiter */
768 case GT_DMA_ARB:
769 val = s->regs[saddr];
770 break;
771
772 /* Timer/Counter */
773 case GT_TC0:
774 case GT_TC1:
775 case GT_TC2:
776 case GT_TC3:
777 case GT_TC_CONTROL:
778 val = s->regs[saddr];
779 break;
780
781 /* PCI Internal */
782 case GT_PCI0_CFGADDR:
783 val = phb->config_reg;
784 break;
785 case GT_PCI0_CFGDATA:
786 if (!(phb->config_reg & (1 << 31))) {
787 val = 0xffffffff;
788 } else {
789 val = pci_data_read(phb->bus, phb->config_reg, 4);
790 }
791 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
792 val = bswap32(val);
793 }
794 break;
795
796 case GT_PCI0_CMD:
797 case GT_PCI0_TOR:
798 case GT_PCI0_BS_SCS10:
799 case GT_PCI0_BS_SCS32:
800 case GT_PCI0_BS_CS20:
801 case GT_PCI0_BS_CS3BT:
802 case GT_PCI1_IACK:
803 case GT_PCI0_BARE:
804 case GT_PCI0_PREFMBR:
805 case GT_PCI0_SCS10_BAR:
806 case GT_PCI0_SCS32_BAR:
807 case GT_PCI0_CS20_BAR:
808 case GT_PCI0_CS3BT_BAR:
809 case GT_PCI0_SSCS10_BAR:
810 case GT_PCI0_SSCS32_BAR:
811 case GT_PCI0_SCS3BT_BAR:
812 case GT_PCI1_CMD:
813 case GT_PCI1_TOR:
814 case GT_PCI1_BS_SCS10:
815 case GT_PCI1_BS_SCS32:
816 case GT_PCI1_BS_CS20:
817 case GT_PCI1_BS_CS3BT:
818 case GT_PCI1_BARE:
819 case GT_PCI1_PREFMBR:
820 case GT_PCI1_SCS10_BAR:
821 case GT_PCI1_SCS32_BAR:
822 case GT_PCI1_CS20_BAR:
823 case GT_PCI1_CS3BT_BAR:
824 case GT_PCI1_SSCS10_BAR:
825 case GT_PCI1_SSCS32_BAR:
826 case GT_PCI1_SCS3BT_BAR:
827 case GT_PCI1_CFGADDR:
828 case GT_PCI1_CFGDATA:
829 val = s->regs[saddr];
830 break;
831
832 /* Interrupts */
833 case GT_INTRCAUSE:
834 val = s->regs[saddr];
835 DPRINTF("INTRCAUSE %x\n", val);
836 break;
837 case GT_INTRMASK:
838 val = s->regs[saddr];
839 DPRINTF("INTRMASK %x\n", val);
840 break;
841 case GT_PCI0_ICMASK:
842 val = s->regs[saddr];
843 DPRINTF("ICMASK %x\n", val);
844 break;
845 case GT_PCI0_SERR0MASK:
846 val = s->regs[saddr];
847 DPRINTF("SERR0MASK %x\n", val);
848 break;
849
850 /* Reserved when only PCI_0 is configured. */
851 case GT_HINTRCAUSE:
852 case GT_CPU_INTSEL:
853 case GT_PCI0_INTSEL:
854 case GT_HINTRMASK:
855 case GT_PCI0_HICMASK:
856 case GT_PCI1_SERR1MASK:
857 val = s->regs[saddr];
858 break;
859
860 default:
861 val = s->regs[saddr];
862 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
863 break;
864 }
865
866 if (!(s->regs[GT_CPU] & 0x00001000))
867 val = bswap32(val);
868
869 return val;
870 }
871
872 static const MemoryRegionOps isd_mem_ops = {
873 .read = gt64120_readl,
874 .write = gt64120_writel,
875 .endianness = DEVICE_NATIVE_ENDIAN,
876 };
877
878 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
879 {
880 int slot;
881
882 slot = (pci_dev->devfn >> 3);
883
884 switch (slot) {
885 /* PIIX4 USB */
886 case 10:
887 return 3;
888 /* AMD 79C973 Ethernet */
889 case 11:
890 return 1;
891 /* Crystal 4281 Sound */
892 case 12:
893 return 2;
894 /* PCI slot 1 to 4 */
895 case 18 ... 21:
896 return ((slot - 18) + irq_num) & 0x03;
897 /* Unknown device, don't do any translation */
898 default:
899 return irq_num;
900 }
901 }
902
903 static int pci_irq_levels[4];
904
905 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
906 {
907 int i, pic_irq, pic_level;
908 qemu_irq *pic = opaque;
909
910 pci_irq_levels[irq_num] = level;
911
912 /* now we change the pic irq level according to the piix irq mappings */
913 /* XXX: optimize */
914 pic_irq = piix4_dev->config[0x60 + irq_num];
915 if (pic_irq < 16) {
916 /* The pic level is the logical OR of all the PCI irqs mapped
917 to it */
918 pic_level = 0;
919 for (i = 0; i < 4; i++) {
920 if (pic_irq == piix4_dev->config[0x60 + i])
921 pic_level |= pci_irq_levels[i];
922 }
923 qemu_set_irq(pic[pic_irq], pic_level);
924 }
925 }
926
927
928 static void gt64120_reset(void *opaque)
929 {
930 GT64120State *s = opaque;
931
932 /* FIXME: Malta specific hw assumptions ahead */
933
934 /* CPU Configuration */
935 #ifdef TARGET_WORDS_BIGENDIAN
936 s->regs[GT_CPU] = 0x00000000;
937 #else
938 s->regs[GT_CPU] = 0x00001000;
939 #endif
940 s->regs[GT_MULTI] = 0x00000003;
941
942 /* CPU Address decode */
943 s->regs[GT_SCS10LD] = 0x00000000;
944 s->regs[GT_SCS10HD] = 0x00000007;
945 s->regs[GT_SCS32LD] = 0x00000008;
946 s->regs[GT_SCS32HD] = 0x0000000f;
947 s->regs[GT_CS20LD] = 0x000000e0;
948 s->regs[GT_CS20HD] = 0x00000070;
949 s->regs[GT_CS3BOOTLD] = 0x000000f8;
950 s->regs[GT_CS3BOOTHD] = 0x0000007f;
951
952 s->regs[GT_PCI0IOLD] = 0x00000080;
953 s->regs[GT_PCI0IOHD] = 0x0000000f;
954 s->regs[GT_PCI0M0LD] = 0x00000090;
955 s->regs[GT_PCI0M0HD] = 0x0000001f;
956 s->regs[GT_ISD] = 0x000000a0;
957 s->regs[GT_PCI0M1LD] = 0x00000790;
958 s->regs[GT_PCI0M1HD] = 0x0000001f;
959 s->regs[GT_PCI1IOLD] = 0x00000100;
960 s->regs[GT_PCI1IOHD] = 0x0000000f;
961 s->regs[GT_PCI1M0LD] = 0x00000110;
962 s->regs[GT_PCI1M0HD] = 0x0000001f;
963 s->regs[GT_PCI1M1LD] = 0x00000120;
964 s->regs[GT_PCI1M1HD] = 0x0000002f;
965
966 s->regs[GT_SCS10AR] = 0x00000000;
967 s->regs[GT_SCS32AR] = 0x00000008;
968 s->regs[GT_CS20R] = 0x000000e0;
969 s->regs[GT_CS3BOOTR] = 0x000000f8;
970
971 s->regs[GT_PCI0IOREMAP] = 0x00000080;
972 s->regs[GT_PCI0M0REMAP] = 0x00000090;
973 s->regs[GT_PCI0M1REMAP] = 0x00000790;
974 s->regs[GT_PCI1IOREMAP] = 0x00000100;
975 s->regs[GT_PCI1M0REMAP] = 0x00000110;
976 s->regs[GT_PCI1M1REMAP] = 0x00000120;
977
978 /* CPU Error Report */
979 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
980 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
981 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
982 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
983 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
984
985 /* CPU Sync Barrier */
986 s->regs[GT_PCI0SYNC] = 0x00000000;
987 s->regs[GT_PCI1SYNC] = 0x00000000;
988
989 /* SDRAM and Device Address Decode */
990 s->regs[GT_SCS0LD] = 0x00000000;
991 s->regs[GT_SCS0HD] = 0x00000007;
992 s->regs[GT_SCS1LD] = 0x00000008;
993 s->regs[GT_SCS1HD] = 0x0000000f;
994 s->regs[GT_SCS2LD] = 0x00000010;
995 s->regs[GT_SCS2HD] = 0x00000017;
996 s->regs[GT_SCS3LD] = 0x00000018;
997 s->regs[GT_SCS3HD] = 0x0000001f;
998 s->regs[GT_CS0LD] = 0x000000c0;
999 s->regs[GT_CS0HD] = 0x000000c7;
1000 s->regs[GT_CS1LD] = 0x000000c8;
1001 s->regs[GT_CS1HD] = 0x000000cf;
1002 s->regs[GT_CS2LD] = 0x000000d0;
1003 s->regs[GT_CS2HD] = 0x000000df;
1004 s->regs[GT_CS3LD] = 0x000000f0;
1005 s->regs[GT_CS3HD] = 0x000000fb;
1006 s->regs[GT_BOOTLD] = 0x000000fc;
1007 s->regs[GT_BOOTHD] = 0x000000ff;
1008 s->regs[GT_ADERR] = 0xffffffff;
1009
1010 /* SDRAM Configuration */
1011 s->regs[GT_SDRAM_CFG] = 0x00000200;
1012 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1013 s->regs[GT_SDRAM_BM] = 0x00000007;
1014 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1015
1016 /* SDRAM Parameters */
1017 s->regs[GT_SDRAM_B0] = 0x00000005;
1018 s->regs[GT_SDRAM_B1] = 0x00000005;
1019 s->regs[GT_SDRAM_B2] = 0x00000005;
1020 s->regs[GT_SDRAM_B3] = 0x00000005;
1021
1022 /* ECC */
1023 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1024 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1025 s->regs[GT_ECC_MEM] = 0x00000000;
1026 s->regs[GT_ECC_CALC] = 0x00000000;
1027 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1028
1029 /* Device Parameters */
1030 s->regs[GT_DEV_B0] = 0x386fffff;
1031 s->regs[GT_DEV_B1] = 0x386fffff;
1032 s->regs[GT_DEV_B2] = 0x386fffff;
1033 s->regs[GT_DEV_B3] = 0x386fffff;
1034 s->regs[GT_DEV_BOOT] = 0x146fffff;
1035
1036 /* DMA registers are all zeroed at reset */
1037
1038 /* Timer/Counter */
1039 s->regs[GT_TC0] = 0xffffffff;
1040 s->regs[GT_TC1] = 0x00ffffff;
1041 s->regs[GT_TC2] = 0x00ffffff;
1042 s->regs[GT_TC3] = 0x00ffffff;
1043 s->regs[GT_TC_CONTROL] = 0x00000000;
1044
1045 /* PCI Internal */
1046 #ifdef TARGET_WORDS_BIGENDIAN
1047 s->regs[GT_PCI0_CMD] = 0x00000000;
1048 #else
1049 s->regs[GT_PCI0_CMD] = 0x00010001;
1050 #endif
1051 s->regs[GT_PCI0_TOR] = 0x0000070f;
1052 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1053 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1054 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1055 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1056 s->regs[GT_PCI1_IACK] = 0x00000000;
1057 s->regs[GT_PCI0_IACK] = 0x00000000;
1058 s->regs[GT_PCI0_BARE] = 0x0000000f;
1059 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1060 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1061 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1062 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1063 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1064 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1065 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1066 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1067 #ifdef TARGET_WORDS_BIGENDIAN
1068 s->regs[GT_PCI1_CMD] = 0x00000000;
1069 #else
1070 s->regs[GT_PCI1_CMD] = 0x00010001;
1071 #endif
1072 s->regs[GT_PCI1_TOR] = 0x0000070f;
1073 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1074 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1075 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1076 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1077 s->regs[GT_PCI1_BARE] = 0x0000000f;
1078 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1079 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1080 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1081 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1082 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1083 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1084 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1085 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1086 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1087 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1088 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1089
1090 /* Interrupt registers are all zeroed at reset */
1091
1092 gt64120_isd_mapping(s);
1093 gt64120_pci_mapping(s);
1094 }
1095
1096 PCIBus *gt64120_register(qemu_irq *pic)
1097 {
1098 GT64120State *d;
1099 PCIHostState *phb;
1100 DeviceState *dev;
1101
1102 dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
1103 qdev_init_nofail(dev);
1104 d = GT64120_PCI_HOST_BRIDGE(dev);
1105 phb = PCI_HOST_BRIDGE(dev);
1106 phb->bus = pci_register_bus(dev, "pci",
1107 gt64120_pci_set_irq, gt64120_pci_map_irq,
1108 pic,
1109 get_system_memory(),
1110 get_system_io(),
1111 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1112 memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);
1113
1114 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1115 return phb->bus;
1116 }
1117
1118 static int gt64120_init(SysBusDevice *dev)
1119 {
1120 GT64120State *s;
1121
1122 s = GT64120_PCI_HOST_BRIDGE(dev);
1123
1124 /* FIXME: This value is computed from registers during reset, but some
1125 devices (e.g. VGA card) need to know it when they are registered.
1126 This also mean that changing the register to change the mapping
1127 does not fully work. */
1128 isa_mem_base = 0x10000000;
1129 qemu_register_reset(gt64120_reset, s);
1130 return 0;
1131 }
1132
1133 static int gt64120_pci_init(PCIDevice *d)
1134 {
1135 /* FIXME: Malta specific hw assumptions ahead */
1136 pci_set_word(d->config + PCI_COMMAND, 0);
1137 pci_set_word(d->config + PCI_STATUS,
1138 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1139 pci_config_set_prog_interface(d->config, 0);
1140 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1141 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1142 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1143 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1144 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1145 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1146 pci_set_byte(d->config + 0x3d, 0x01);
1147
1148 return 0;
1149 }
1150
1151 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1152 {
1153 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1154
1155 k->init = gt64120_pci_init;
1156 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1157 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1158 k->revision = 0x10;
1159 k->class_id = PCI_CLASS_BRIDGE_HOST;
1160 }
1161
1162 static const TypeInfo gt64120_pci_info = {
1163 .name = "gt64120_pci",
1164 .parent = TYPE_PCI_DEVICE,
1165 .instance_size = sizeof(PCIDevice),
1166 .class_init = gt64120_pci_class_init,
1167 };
1168
1169 static void gt64120_class_init(ObjectClass *klass, void *data)
1170 {
1171 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1172
1173 sdc->init = gt64120_init;
1174 }
1175
1176 static const TypeInfo gt64120_info = {
1177 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1178 .parent = TYPE_PCI_HOST_BRIDGE,
1179 .instance_size = sizeof(GT64120State),
1180 .class_init = gt64120_class_init,
1181 };
1182
1183 static void gt64120_pci_register_types(void)
1184 {
1185 type_register_static(&gt64120_info);
1186 type_register_static(&gt64120_pci_info);
1187 }
1188
1189 type_init(gt64120_pci_register_types)
Qemu copy for testing