hw/mips_int.c

   1 #include "vl.h"
   2 #include "cpu.h"
   3
   4 /* Raise IRQ to CPU if necessary. It must be called every time the active
   5    IRQ may change */
   6 void cpu_mips_update_irq(CPUState *env)
   7 {
   8     if ((env->CP0_Status & (1 << CP0St_IE)) &&
   9         !(env->CP0_Status & (1 << CP0St_EXL)) &&
  10         !(env->CP0_Status & (1 << CP0St_ERL)) &&
  11         !(env->hflags & MIPS_HFLAG_DM)) {
  12         if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
  13             !(env->interrupt_request & CPU_INTERRUPT_HARD)) {
  14             cpu_interrupt(env, CPU_INTERRUPT_HARD);
  15         }
  16     } else
  17         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  18 }
  19
  20 static void cpu_mips_irq_request(void *opaque, int irq, int level)
  21 {
  22     CPUState *env = (CPUState *)opaque;
  23
  24     if (irq < 0 || irq > 7)
  25         return;
  26
  27     if (level) {
  28         env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
  29     } else {
  30         env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
  31     }
  32     cpu_mips_update_irq(env);
  33 }
  34
  35 void cpu_mips_irq_init_cpu(CPUState *env)
  36 {
  37     qemu_irq *qi;
  38     int i;
  39
  40     qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
  41     for (i = 0; i < 8; i++) {
  42         env->irq[i] = qi[i];
  43     }
  44 }