hw/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "mips_cpudevs.h"
  28 #include "pc.h"
  29 #include "isa.h"
  30 #include "fdc.h"
  31 #include "sysemu.h"
  32 #include "arch_init.h"
  33 #include "boards.h"
  34 #include "net.h"
  35 #include "esp.h"
  36 #include "mips-bios.h"
  37 #include "loader.h"
  38 #include "mc146818rtc.h"
  39 #include "i8254.h"
  40 #include "pcspk.h"
  41 #include "blockdev.h"
  42 #include "sysbus.h"
  43 #include "exec-memory.h"
  44
  45 enum jazz_model_e
  46 {
  47     JAZZ_MAGNUM,
  48     JAZZ_PICA61,
  49 };
  50
  51 static void main_cpu_reset(void *opaque)
  52 {
  53     CPUMIPSState *env = opaque;
  54     cpu_state_reset(env);
  55 }
  56
  57 static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
  58 {
  59     return cpu_inw(0x71);
  60 }
  61
  62 static void rtc_write(void *opaque, target_phys_addr_t addr,
  63                       uint64_t val, unsigned size)
  64 {
  65     cpu_outw(0x71, val & 0xff);
  66 }
  67
  68 static const MemoryRegionOps rtc_ops = {
  69     .read = rtc_read,
  70     .write = rtc_write,
  71     .endianness = DEVICE_NATIVE_ENDIAN,
  72 };
  73
  74 static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
  75                                unsigned size)
  76 {
  77     /* Nothing to do. That is only to ensure that
  78      * the current DMA acknowledge cycle is completed. */
  79     return 0xff;
  80 }
  81
  82 static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
  83                             uint64_t val, unsigned size)
  84 {
  85     /* Nothing to do. That is only to ensure that
  86      * the current DMA acknowledge cycle is completed. */
  87 }
  88
  89 static const MemoryRegionOps dma_dummy_ops = {
  90     .read = dma_dummy_read,
  91     .write = dma_dummy_write,
  92     .endianness = DEVICE_NATIVE_ENDIAN,
  93 };
  94
  95 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
  96 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
  97
  98 static void cpu_request_exit(void *opaque, int irq, int level)
  99 {
 100     CPUMIPSState *env = cpu_single_env;
 101
 102     if (env && level) {
 103         cpu_exit(env);
 104     }
 105 }
 106
 107 static void mips_jazz_init(MemoryRegion *address_space,
 108                            MemoryRegion *address_space_io,
 109                            ram_addr_t ram_size,
 110                            const char *cpu_model,
 111                            enum jazz_model_e jazz_model)
 112 {
 113     char *filename;
 114     int bios_size, n;
 115     MIPSCPU *cpu;
 116     CPUMIPSState *env;
 117     qemu_irq *rc4030, *i8259;
 118     rc4030_dma *dmas;
 119     void* rc4030_opaque;
 120     MemoryRegion *rtc = g_new(MemoryRegion, 1);
 121     MemoryRegion *i8042 = g_new(MemoryRegion, 1);
 122     MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
 123     NICInfo *nd;
 124     DeviceState *dev;
 125     SysBusDevice *sysbus;
 126     ISABus *isa_bus;
 127     ISADevice *pit;
 128     DriveInfo *fds[MAX_FD];
 129     qemu_irq esp_reset, dma_enable;
 130     qemu_irq *cpu_exit_irq;
 131     MemoryRegion *ram = g_new(MemoryRegion, 1);
 132     MemoryRegion *bios = g_new(MemoryRegion, 1);
 133     MemoryRegion *bios2 = g_new(MemoryRegion, 1);
 134
 135     /* init CPUs */
 136     if (cpu_model == NULL) {
 137 #ifdef TARGET_MIPS64
 138         cpu_model = "R4000";
 139 #else
 140         /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
 141         cpu_model = "24Kf";
 142 #endif
 143     }
 144     cpu = cpu_mips_init(cpu_model);
 145     if (cpu == NULL) {
 146         fprintf(stderr, "Unable to find CPU definition\n");
 147         exit(1);
 148     }
 149     env = &cpu->env;
 150     qemu_register_reset(main_cpu_reset, env);
 151
 152     /* allocate RAM */
 153     memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
 154     vmstate_register_ram_global(ram);
 155     memory_region_add_subregion(address_space, 0, ram);
 156
 157     memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
 158     vmstate_register_ram_global(bios);
 159     memory_region_set_readonly(bios, true);
 160     memory_region_init_alias(bios2, "mips_jazz.bios", bios,
 161                              0, MAGNUM_BIOS_SIZE);
 162     memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
 163     memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
 164
 165     /* load the BIOS image. */
 166     if (bios_name == NULL)
 167         bios_name = BIOS_FILENAME;
 168     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 169     if (filename) {
 170         bios_size = load_image_targphys(filename, 0xfff00000LL,
 171                                         MAGNUM_BIOS_SIZE);
 172         g_free(filename);
 173     } else {
 174         bios_size = -1;
 175     }
 176     if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
 177         fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
 178                 bios_name);
 179         exit(1);
 180     }
 181
 182     /* Init CPU internal devices */
 183     cpu_mips_irq_init_cpu(env);
 184     cpu_mips_clock_init(env);
 185
 186     /* Chipset */
 187     rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
 188                                 address_space);
 189     memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
 190     memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
 191
 192     /* ISA devices */
 193     isa_bus = isa_bus_new(NULL, address_space_io);
 194     i8259 = i8259_init(isa_bus, env->irq[4]);
 195     isa_bus_irqs(isa_bus, i8259);
 196     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 197     DMA_init(0, cpu_exit_irq);
 198     pit = pit_init(isa_bus, 0x40, 0, NULL);
 199     pcspk_init(isa_bus, pit);
 200
 201     /* ISA IO space at 0x90000000 */
 202     isa_mmio_init(0x90000000, 0x01000000);
 203     isa_mem_base = 0x11000000;
 204
 205     /* Video card */
 206     switch (jazz_model) {
 207     case JAZZ_MAGNUM:
 208         dev = qdev_create(NULL, "sysbus-g364");
 209         qdev_init_nofail(dev);
 210         sysbus = sysbus_from_qdev(dev);
 211         sysbus_mmio_map(sysbus, 0, 0x60080000);
 212         sysbus_mmio_map(sysbus, 1, 0x40000000);
 213         sysbus_connect_irq(sysbus, 0, rc4030[3]);
 214         {
 215             /* Simple ROM, so user doesn't have to provide one */
 216             MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
 217             memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000);
 218             vmstate_register_ram_global(rom_mr);
 219             memory_region_set_readonly(rom_mr, true);
 220             uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
 221             memory_region_add_subregion(address_space, 0x60000000, rom_mr);
 222             rom[0] = 0x10; /* Mips G364 */
 223         }
 224         break;
 225     case JAZZ_PICA61:
 226         isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
 227         break;
 228     default:
 229         break;
 230     }
 231
 232     /* Network controller */
 233     for (n = 0; n < nb_nics; n++) {
 234         nd = &nd_table[n];
 235         if (!nd->model)
 236             nd->model = g_strdup("dp83932");
 237         if (strcmp(nd->model, "dp83932") == 0) {
 238             dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
 239                          rc4030_opaque, rc4030_dma_memory_rw);
 240             break;
 241         } else if (strcmp(nd->model, "?") == 0) {
 242             fprintf(stderr, "qemu: Supported NICs: dp83932\n");
 243             exit(1);
 244         } else {
 245             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 246             exit(1);
 247         }
 248     }
 249
 250     /* SCSI adapter */
 251     esp_init(0x80002000, 0,
 252              rc4030_dma_read, rc4030_dma_write, dmas[0],
 253              rc4030[5], &esp_reset, &dma_enable);
 254
 255     /* Floppy */
 256     if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
 257         fprintf(stderr, "qemu: too many floppy drives\n");
 258         exit(1);
 259     }
 260     for (n = 0; n < MAX_FD; n++) {
 261         fds[n] = drive_get(IF_FLOPPY, 0, n);
 262     }
 263     fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
 264
 265     /* Real time clock */
 266     rtc_init(isa_bus, 1980, NULL);
 267     memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
 268     memory_region_add_subregion(address_space, 0x80004000, rtc);
 269
 270     /* Keyboard (i8042) */
 271     i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
 272     memory_region_add_subregion(address_space, 0x80005000, i8042);
 273
 274     /* Serial ports */
 275     if (serial_hds[0]) {
 276         serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
 277                        serial_hds[0], DEVICE_NATIVE_ENDIAN);
 278     }
 279     if (serial_hds[1]) {
 280         serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
 281                        serial_hds[1], DEVICE_NATIVE_ENDIAN);
 282     }
 283
 284     /* Parallel port */
 285     if (parallel_hds[0])
 286         parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
 287                          parallel_hds[0]);
 288
 289     /* Sound card */
 290     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 291     audio_init(isa_bus, NULL);
 292
 293     /* NVRAM */
 294     dev = qdev_create(NULL, "ds1225y");
 295     qdev_init_nofail(dev);
 296     sysbus = sysbus_from_qdev(dev);
 297     sysbus_mmio_map(sysbus, 0, 0x80009000);
 298
 299     /* LED indicator */
 300     sysbus_create_simple("jazz-led", 0x8000f000, NULL);
 301 }
 302
 303 static
 304 void mips_magnum_init (ram_addr_t ram_size,
 305                        const char *boot_device,
 306                        const char *kernel_filename, const char *kernel_cmdline,
 307                        const char *initrd_filename, const char *cpu_model)
 308 {
 309         mips_jazz_init(get_system_memory(), get_system_io(),
 310                        ram_size, cpu_model, JAZZ_MAGNUM);
 311 }
 312
 313 static
 314 void mips_pica61_init (ram_addr_t ram_size,
 315                        const char *boot_device,
 316                        const char *kernel_filename, const char *kernel_cmdline,
 317                        const char *initrd_filename, const char *cpu_model)
 318 {
 319     mips_jazz_init(get_system_memory(), get_system_io(),
 320                    ram_size, cpu_model, JAZZ_PICA61);
 321 }
 322
 323 static QEMUMachine mips_magnum_machine = {
 324     .name = "magnum",
 325     .desc = "MIPS Magnum",
 326     .init = mips_magnum_init,
 327     .use_scsi = 1,
 328 };
 329
 330 static QEMUMachine mips_pica61_machine = {
 331     .name = "pica61",
 332     .desc = "Acer Pica 61",
 333     .init = mips_pica61_init,
 334     .use_scsi = 1,
 335 };
 336
 337 static void mips_jazz_machine_init(void)
 338 {
 339     qemu_register_machine(&mips_magnum_machine);
 340     qemu_register_machine(&mips_pica61_machine);
 341 }
 342
 343 machine_init(mips_jazz_machine_init);