hw/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "fdc.h"
  30 #include "sysemu.h"
  31 #include "audio/audio.h"
  32 #include "boards.h"
  33 #include "net.h"
  34 #include "scsi.h"
  35 #include "mips-bios.h"
  36 #include "loader.h"
  37
  38 enum jazz_model_e
  39 {
  40     JAZZ_MAGNUM,
  41     JAZZ_PICA61,
  42 };
  43
  44 static void main_cpu_reset(void *opaque)
  45 {
  46     CPUState *env = opaque;
  47     cpu_reset(env);
  48 }
  49
  50 static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
  51 {
  52     CPUState *env = opaque;
  53     return cpu_inw(env, 0x71);
  54 }
  55
  56 static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  57 {
  58     CPUState *env = opaque;
  59     cpu_outw(env, 0x71, val & 0xff);
  60 }
  61
  62 static CPUReadMemoryFunc * const rtc_read[3] = {
  63     rtc_readb,
  64     rtc_readb,
  65     rtc_readb,
  66 };
  67
  68 static CPUWriteMemoryFunc * const rtc_write[3] = {
  69     rtc_writeb,
  70     rtc_writeb,
  71     rtc_writeb,
  72 };
  73
  74 static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  75 {
  76     /* Nothing to do. That is only to ensure that
  77      * the current DMA acknowledge cycle is completed. */
  78 }
  79
  80 static CPUReadMemoryFunc * const dma_dummy_read[3] = {
  81     NULL,
  82     NULL,
  83     NULL,
  84 };
  85
  86 static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
  87     dma_dummy_writeb,
  88     dma_dummy_writeb,
  89     dma_dummy_writeb,
  90 };
  91
  92 #ifdef HAS_AUDIO
  93 static void audio_init(qemu_irq *pic)
  94 {
  95     struct soundhw *c;
  96     int audio_enabled = 0;
  97
  98     for (c = soundhw; !audio_enabled && c->name; ++c) {
  99         audio_enabled = c->enabled;
 100     }
 101
 102     if (audio_enabled) {
 103         for (c = soundhw; c->name; ++c) {
 104             if (c->enabled) {
 105                 if (c->isa) {
 106                     c->init.init_isa(pic);
 107                 }
 108             }
 109         }
 110     }
 111 }
 112 #endif
 113
 114 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 115 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 116
 117 static
 118 void mips_jazz_init (ram_addr_t ram_size,
 119                      const char *cpu_model,
 120                      enum jazz_model_e jazz_model)
 121 {
 122     char *filename;
 123     int bios_size, n;
 124     CPUState *env;
 125     qemu_irq *rc4030, *i8259;
 126     rc4030_dma *dmas;
 127     void* rc4030_opaque;
 128     int s_rtc, s_dma_dummy;
 129     NICInfo *nd;
 130     PITState *pit;
 131     BlockDriverState *fds[MAX_FD];
 132     qemu_irq esp_reset;
 133     ram_addr_t ram_offset;
 134     ram_addr_t bios_offset;
 135
 136     /* init CPUs */
 137     if (cpu_model == NULL) {
 138 #ifdef TARGET_MIPS64
 139         cpu_model = "R4000";
 140 #else
 141         /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
 142         cpu_model = "24Kf";
 143 #endif
 144     }
 145     env = cpu_init(cpu_model);
 146     if (!env) {
 147         fprintf(stderr, "Unable to find CPU definition\n");
 148         exit(1);
 149     }
 150     qemu_register_reset(main_cpu_reset, env);
 151
 152     /* allocate RAM */
 153     ram_offset = qemu_ram_alloc(ram_size);
 154     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 155
 156     bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
 157     cpu_register_physical_memory(0x1fc00000LL,
 158                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 159     cpu_register_physical_memory(0xfff00000LL,
 160                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 161
 162     /* load the BIOS image. */
 163     if (bios_name == NULL)
 164         bios_name = BIOS_FILENAME;
 165     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 166     if (filename) {
 167         bios_size = load_image_targphys(filename, 0xfff00000LL,
 168                                         MAGNUM_BIOS_SIZE);
 169         qemu_free(filename);
 170     } else {
 171         bios_size = -1;
 172     }
 173     if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
 174         fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
 175                 bios_name);
 176         exit(1);
 177     }
 178
 179     /* Init CPU internal devices */
 180     cpu_mips_irq_init_cpu(env);
 181     cpu_mips_clock_init(env);
 182
 183     /* Chipset */
 184     rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
 185     s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
 186     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 187
 188     /* ISA devices */
 189     i8259 = i8259_init(env->irq[4]);
 190     DMA_init(0);
 191     pit = pit_init(0x40, i8259[0]);
 192     pcspk_init(pit);
 193
 194     /* ISA IO space at 0x90000000 */
 195     isa_mmio_init(0x90000000, 0x01000000);
 196     isa_mem_base = 0x11000000;
 197
 198     /* Video card */
 199     switch (jazz_model) {
 200     case JAZZ_MAGNUM:
 201         g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
 202         break;
 203     case JAZZ_PICA61:
 204         isa_vga_mm_init(0x40000000, 0x60000000, 0);
 205         break;
 206     default:
 207         break;
 208     }
 209
 210     /* Network controller */
 211     for (n = 0; n < nb_nics; n++) {
 212         nd = &nd_table[n];
 213         if (!nd->model)
 214             nd->model = "dp83932";
 215         if (strcmp(nd->model, "dp83932") == 0) {
 216             dp83932_init(nd, 0x80001000, 2, rc4030[4],
 217                          rc4030_opaque, rc4030_dma_memory_rw);
 218             break;
 219         } else if (strcmp(nd->model, "?") == 0) {
 220             fprintf(stderr, "qemu: Supported NICs: dp83932\n");
 221             exit(1);
 222         } else {
 223             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 224             exit(1);
 225         }
 226     }
 227
 228     /* SCSI adapter */
 229     esp_init(0x80002000, 0,
 230              rc4030_dma_read, rc4030_dma_write, dmas[0],
 231              rc4030[5], &esp_reset);
 232
 233     /* Floppy */
 234     if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
 235         fprintf(stderr, "qemu: too many floppy drives\n");
 236         exit(1);
 237     }
 238     for (n = 0; n < MAX_FD; n++) {
 239         DriveInfo *dinfo = drive_get(IF_FLOPPY, 0, n);
 240         fds[n] = dinfo ? dinfo->bdrv : NULL;
 241     }
 242     fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
 243
 244     /* Real time clock */
 245     rtc_init(1980);
 246     s_rtc = cpu_register_io_memory(rtc_read, rtc_write, env);
 247     cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
 248
 249     /* Keyboard (i8042) */
 250     i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
 251
 252     /* Serial ports */
 253     if (serial_hds[0])
 254         serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
 255     if (serial_hds[1])
 256         serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
 257
 258     /* Parallel port */
 259     if (parallel_hds[0])
 260         parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
 261
 262     /* Sound card */
 263     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 264 #ifdef HAS_AUDIO
 265     audio_init(i8259);
 266 #endif
 267
 268     /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
 269     ds1225y_init(0x80009000, "nvram");
 270
 271     /* LED indicator */
 272     jazz_led_init(0x8000f000);
 273 }
 274
 275 static
 276 void mips_magnum_init (ram_addr_t ram_size,
 277                        const char *boot_device,
 278                        const char *kernel_filename, const char *kernel_cmdline,
 279                        const char *initrd_filename, const char *cpu_model)
 280 {
 281     mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
 282 }
 283
 284 static
 285 void mips_pica61_init (ram_addr_t ram_size,
 286                        const char *boot_device,
 287                        const char *kernel_filename, const char *kernel_cmdline,
 288                        const char *initrd_filename, const char *cpu_model)
 289 {
 290     mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
 291 }
 292
 293 static QEMUMachine mips_magnum_machine = {
 294     .name = "magnum",
 295     .desc = "MIPS Magnum",
 296     .init = mips_magnum_init,
 297     .use_scsi = 1,
 298 };
 299
 300 static QEMUMachine mips_pica61_machine = {
 301     .name = "pica61",
 302     .desc = "Acer Pica 61",
 303     .init = mips_pica61_init,
 304     .use_scsi = 1,
 305 };
 306
 307 static void mips_jazz_machine_init(void)
 308 {
 309     qemu_register_machine(&mips_magnum_machine);
 310     qemu_register_machine(&mips_pica61_machine);
 311 }
 312
 313 machine_init(mips_jazz_machine_init);