hw/misc/zynq_slcr.c

   1 /*
   2  * Status and system control registers for Xilinx Zynq Platform
   3  *
   4  * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
   5  * Copyright (c) 2012 PetaLogix Pty Ltd.
   6  * Based on hw/arm_sysctl.c, written by Paul Brook
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include "hw/hw.h"
  18 #include "qemu/timer.h"
  19 #include "hw/sysbus.h"
  20 #include "sysemu/sysemu.h"
  21
  22 #ifdef ZYNQ_ARM_SLCR_ERR_DEBUG
  23 #define DB_PRINT(...) do { \
  24     fprintf(stderr,  ": %s: ", __func__); \
  25     fprintf(stderr, ## __VA_ARGS__); \
  26     } while (0);
  27 #else
  28     #define DB_PRINT(...)
  29 #endif
  30
  31 #define XILINX_LOCK_KEY 0x767b
  32 #define XILINX_UNLOCK_KEY 0xdf0d
  33
  34 typedef enum {
  35   ARM_PLL_CTRL,
  36   DDR_PLL_CTRL,
  37   IO_PLL_CTRL,
  38   PLL_STATUS,
  39   ARM_PPL_CFG,
  40   DDR_PLL_CFG,
  41   IO_PLL_CFG,
  42   PLL_BG_CTRL,
  43   PLL_MAX
  44 } PLLValues;
  45
  46 typedef enum {
  47   ARM_CLK_CTRL,
  48   DDR_CLK_CTRL,
  49   DCI_CLK_CTRL,
  50   APER_CLK_CTRL,
  51   USB0_CLK_CTRL,
  52   USB1_CLK_CTRL,
  53   GEM0_RCLK_CTRL,
  54   GEM1_RCLK_CTRL,
  55   GEM0_CLK_CTRL,
  56   GEM1_CLK_CTRL,
  57   SMC_CLK_CTRL,
  58   LQSPI_CLK_CTRL,
  59   SDIO_CLK_CTRL,
  60   UART_CLK_CTRL,
  61   SPI_CLK_CTRL,
  62   CAN_CLK_CTRL,
  63   CAN_MIOCLK_CTRL,
  64   DBG_CLK_CTRL,
  65   PCAP_CLK_CTRL,
  66   TOPSW_CLK_CTRL,
  67   CLK_MAX
  68 } ClkValues;
  69
  70 typedef enum {
  71   CLK_CTRL,
  72   THR_CTRL,
  73   THR_CNT,
  74   THR_STA,
  75   FPGA_MAX
  76 } FPGAValues;
  77
  78 typedef enum {
  79   SYNC_CTRL,
  80   SYNC_STATUS,
  81   BANDGAP_TRIP,
  82   CC_TEST,
  83   PLL_PREDIVISOR,
  84   CLK_621_TRUE,
  85   PICTURE_DBG,
  86   PICTURE_DBG_UCNT,
  87   PICTURE_DBG_LCNT,
  88   MISC_MAX
  89 } MiscValues;
  90
  91 typedef enum {
  92   PSS,
  93   DDDR,
  94   DMAC = 3,
  95   USB,
  96   GEM,
  97   SDIO,
  98   SPI,
  99   CAN,
 100   I2C,
 101   UART,
 102   GPIO,
 103   LQSPI,
 104   SMC,
 105   OCM,
 106   DEVCI,
 107   FPGA,
 108   A9_CPU,
 109   RS_AWDT,
 110   RST_REASON,
 111   RST_REASON_CLR,
 112   REBOOT_STATUS,
 113   BOOT_MODE,
 114   RESET_MAX
 115 } ResetValues;
 116
 117 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
 118 #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
 119
 120 typedef struct ZynqSLCRState {
 121     SysBusDevice parent_obj;
 122
 123     MemoryRegion iomem;
 124
 125     union {
 126         struct {
 127             uint16_t scl;
 128             uint16_t lockval;
 129             uint32_t pll[PLL_MAX]; /* 0x100 - 0x11C */
 130             uint32_t clk[CLK_MAX]; /* 0x120 - 0x16C */
 131             uint32_t fpga[4][FPGA_MAX]; /* 0x170 - 0x1AC */
 132             uint32_t misc[MISC_MAX]; /* 0x1B0 - 0x1D8 */
 133             uint32_t reset[RESET_MAX]; /* 0x200 - 0x25C */
 134             uint32_t apu_ctrl; /* 0x300 */
 135             uint32_t wdt_clk_sel; /* 0x304 */
 136             uint32_t tz_ocm[3]; /* 0x400 - 0x408 */
 137             uint32_t tz_ddr; /* 0x430 */
 138             uint32_t tz_dma[3]; /* 0x440 - 0x448 */
 139             uint32_t tz_misc[3]; /* 0x450 - 0x458 */
 140             uint32_t tz_fpga[2]; /* 0x484 - 0x488 */
 141             uint32_t dbg_ctrl; /* 0x500 */
 142             uint32_t pss_idcode; /* 0x530 */
 143             uint32_t ddr[8]; /* 0x600 - 0x620 - 0x604-missing */
 144             uint32_t mio[54]; /* 0x700 - 0x7D4 */
 145             uint32_t mio_func[4]; /* 0x800 - 0x810 */
 146             uint32_t sd[2]; /* 0x830 - 0x834 */
 147             uint32_t lvl_shftr_en; /* 0x900 */
 148             uint32_t ocm_cfg; /* 0x910 */
 149             uint32_t cpu_ram[8]; /* 0xA00 - 0xA1C */
 150             uint32_t iou[7]; /* 0xA30 - 0xA48 */
 151             uint32_t dmac_ram; /* 0xA50 */
 152             uint32_t afi[4][3]; /* 0xA60 - 0xA8C */
 153             uint32_t ocm[3]; /* 0xA90 - 0xA98 */
 154             uint32_t devci_ram; /* 0xAA0 */
 155             uint32_t csg_ram; /* 0xAB0 */
 156             uint32_t gpiob[12]; /* 0xB00 - 0xB2C */
 157             uint32_t ddriob[14]; /* 0xB40 - 0xB74 */
 158         };
 159         uint8_t data[0x1000];
 160     };
 161 } ZynqSLCRState;
 162
 163 static void zynq_slcr_reset(DeviceState *d)
 164 {
 165     ZynqSLCRState *s = ZYNQ_SLCR(d);
 166     int i;
 167
 168     DB_PRINT("RESET\n");
 169
 170     s->lockval = 1;
 171     /* 0x100 - 0x11C */
 172     s->pll[ARM_PLL_CTRL] = 0x0001A008;
 173     s->pll[DDR_PLL_CTRL] = 0x0001A008;
 174     s->pll[IO_PLL_CTRL] = 0x0001A008;
 175     s->pll[PLL_STATUS] = 0x0000003F;
 176     s->pll[ARM_PPL_CFG] = 0x00014000;
 177     s->pll[DDR_PLL_CFG] = 0x00014000;
 178     s->pll[IO_PLL_CFG] = 0x00014000;
 179
 180     /* 0x120 - 0x16C */
 181     s->clk[ARM_CLK_CTRL] = 0x1F000400;
 182     s->clk[DDR_CLK_CTRL] = 0x18400003;
 183     s->clk[DCI_CLK_CTRL] = 0x01E03201;
 184     s->clk[APER_CLK_CTRL] = 0x01FFCCCD;
 185     s->clk[USB0_CLK_CTRL] = s->clk[USB1_CLK_CTRL] = 0x00101941;
 186     s->clk[GEM0_RCLK_CTRL] = s->clk[GEM1_RCLK_CTRL] = 0x00000001;
 187     s->clk[GEM0_CLK_CTRL] = s->clk[GEM1_CLK_CTRL] = 0x00003C01;
 188     s->clk[SMC_CLK_CTRL] = 0x00003C01;
 189     s->clk[LQSPI_CLK_CTRL] = 0x00002821;
 190     s->clk[SDIO_CLK_CTRL] = 0x00001E03;
 191     s->clk[UART_CLK_CTRL] = 0x00003F03;
 192     s->clk[SPI_CLK_CTRL] = 0x00003F03;
 193     s->clk[CAN_CLK_CTRL] = 0x00501903;
 194     s->clk[DBG_CLK_CTRL] = 0x00000F03;
 195     s->clk[PCAP_CLK_CTRL] = 0x00000F01;
 196
 197     /* 0x170 - 0x1AC */
 198     s->fpga[0][CLK_CTRL] = s->fpga[1][CLK_CTRL] = s->fpga[2][CLK_CTRL] =
 199             s->fpga[3][CLK_CTRL] = 0x00101800;
 200     s->fpga[0][THR_STA] = s->fpga[1][THR_STA] = s->fpga[2][THR_STA] =
 201             s->fpga[3][THR_STA] = 0x00010000;
 202
 203     /* 0x1B0 - 0x1D8 */
 204     s->misc[BANDGAP_TRIP] = 0x0000001F;
 205     s->misc[PLL_PREDIVISOR] = 0x00000001;
 206     s->misc[CLK_621_TRUE] = 0x00000001;
 207
 208     /* 0x200 - 0x25C */
 209     s->reset[FPGA] = 0x01F33F0F;
 210     s->reset[RST_REASON] = 0x00000040;
 211
 212     /* 0x700 - 0x7D4 */
 213     for (i = 0; i < 54; i++) {
 214         s->mio[i] = 0x00001601;
 215     }
 216     for (i = 2; i <= 8; i++) {
 217         s->mio[i] = 0x00000601;
 218     }
 219
 220     /* MIO_MST_TRI0, MIO_MST_TRI1 */
 221     s->mio_func[2] = s->mio_func[3] = 0xFFFFFFFF;
 222
 223     s->cpu_ram[0] = s->cpu_ram[1] = s->cpu_ram[3] =
 224             s->cpu_ram[4] = s->cpu_ram[7] = 0x00010101;
 225     s->cpu_ram[2] = s->cpu_ram[5] = 0x01010101;
 226     s->cpu_ram[6] = 0x00000001;
 227
 228     s->iou[0] = s->iou[1] = s->iou[2] = s->iou[3] = 0x09090909;
 229     s->iou[4] = s->iou[5] = 0x00090909;
 230     s->iou[6] = 0x00000909;
 231
 232     s->dmac_ram = 0x00000009;
 233
 234     s->afi[0][0] = s->afi[0][1] = 0x09090909;
 235     s->afi[1][0] = s->afi[1][1] = 0x09090909;
 236     s->afi[2][0] = s->afi[2][1] = 0x09090909;
 237     s->afi[3][0] = s->afi[3][1] = 0x09090909;
 238     s->afi[0][2] = s->afi[1][2] = s->afi[2][2] = s->afi[3][2] = 0x00000909;
 239
 240     s->ocm[0] = 0x01010101;
 241     s->ocm[1] = s->ocm[2] = 0x09090909;
 242
 243     s->devci_ram = 0x00000909;
 244     s->csg_ram = 0x00000001;
 245
 246     s->ddriob[0] = s->ddriob[1] = s->ddriob[2] = s->ddriob[3] = 0x00000e00;
 247     s->ddriob[4] = s->ddriob[5] = s->ddriob[6] = 0x00000e00;
 248     s->ddriob[12] = 0x00000021;
 249 }
 250
 251 static inline uint32_t zynq_slcr_read_imp(void *opaque,
 252     hwaddr offset)
 253 {
 254     ZynqSLCRState *s = (ZynqSLCRState *)opaque;
 255
 256     switch (offset) {
 257     case 0x0: /* SCL */
 258         return s->scl;
 259     case 0x4: /* LOCK */
 260     case 0x8: /* UNLOCK */
 261         DB_PRINT("Reading SCLR_LOCK/UNLOCK is not enabled\n");
 262         return 0;
 263     case 0x0C: /* LOCKSTA */
 264         return s->lockval;
 265     case 0x100 ... 0x11C:
 266         return s->pll[(offset - 0x100) / 4];
 267     case 0x120 ... 0x16C:
 268         return s->clk[(offset - 0x120) / 4];
 269     case 0x170 ... 0x1AC:
 270         return s->fpga[0][(offset - 0x170) / 4];
 271     case 0x1B0 ... 0x1D8:
 272         return s->misc[(offset - 0x1B0) / 4];
 273     case 0x200 ... 0x258:
 274         return s->reset[(offset - 0x200) / 4];
 275     case 0x25c:
 276         return 1;
 277     case 0x300:
 278         return s->apu_ctrl;
 279     case 0x304:
 280         return s->wdt_clk_sel;
 281     case 0x400 ... 0x408:
 282         return s->tz_ocm[(offset - 0x400) / 4];
 283     case 0x430:
 284         return s->tz_ddr;
 285     case 0x440 ... 0x448:
 286         return s->tz_dma[(offset - 0x440) / 4];
 287     case 0x450 ... 0x458:
 288         return s->tz_misc[(offset - 0x450) / 4];
 289     case 0x484 ... 0x488:
 290         return s->tz_fpga[(offset - 0x484) / 4];
 291     case 0x500:
 292         return s->dbg_ctrl;
 293     case 0x530:
 294         return s->pss_idcode;
 295     case 0x600 ... 0x620:
 296         if (offset == 0x604) {
 297             goto bad_reg;
 298         }
 299         return s->ddr[(offset - 0x600) / 4];
 300     case 0x700 ... 0x7D4:
 301         return s->mio[(offset - 0x700) / 4];
 302     case 0x800 ... 0x810:
 303         return s->mio_func[(offset - 0x800) / 4];
 304     case 0x830 ... 0x834:
 305         return s->sd[(offset - 0x830) / 4];
 306     case 0x900:
 307         return s->lvl_shftr_en;
 308     case 0x910:
 309         return s->ocm_cfg;
 310     case 0xA00 ... 0xA1C:
 311         return s->cpu_ram[(offset - 0xA00) / 4];
 312     case 0xA30 ... 0xA48:
 313         return s->iou[(offset - 0xA30) / 4];
 314     case 0xA50:
 315         return s->dmac_ram;
 316     case 0xA60 ... 0xA8C:
 317         return s->afi[0][(offset - 0xA60) / 4];
 318     case 0xA90 ... 0xA98:
 319         return s->ocm[(offset - 0xA90) / 4];
 320     case 0xAA0:
 321         return s->devci_ram;
 322     case 0xAB0:
 323         return s->csg_ram;
 324     case 0xB00 ... 0xB2C:
 325         return s->gpiob[(offset - 0xB00) / 4];
 326     case 0xB40 ... 0xB74:
 327         return s->ddriob[(offset - 0xB40) / 4];
 328     default:
 329     bad_reg:
 330         DB_PRINT("Bad register offset 0x%x\n", (int)offset);
 331         return 0;
 332     }
 333 }
 334
 335 static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
 336     unsigned size)
 337 {
 338     uint32_t ret = zynq_slcr_read_imp(opaque, offset);
 339
 340     DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret);
 341     return ret;
 342 }
 343
 344 static void zynq_slcr_write(void *opaque, hwaddr offset,
 345                           uint64_t val, unsigned size)
 346 {
 347     ZynqSLCRState *s = (ZynqSLCRState *)opaque;
 348
 349     DB_PRINT("offset: %08x data: %08x\n", (unsigned)offset, (unsigned)val);
 350
 351     switch (offset) {
 352     case 0x00: /* SCL */
 353         s->scl = val & 0x1;
 354     return;
 355     case 0x4: /* SLCR_LOCK */
 356         if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
 357             DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 358                 (unsigned)val & 0xFFFF);
 359             s->lockval = 1;
 360         } else {
 361             DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 362                 (int)offset, (unsigned)val & 0xFFFF);
 363         }
 364         return;
 365     case 0x8: /* SLCR_UNLOCK */
 366         if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
 367             DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 368                 (unsigned)val & 0xFFFF);
 369             s->lockval = 0;
 370         } else {
 371             DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 372                 (int)offset, (unsigned)val & 0xFFFF);
 373         }
 374         return;
 375     case 0xc: /* LOCKSTA */
 376         DB_PRINT("Writing SCLR_LOCKSTA is not enabled\n");
 377         return;
 378     }
 379
 380     if (!s->lockval) {
 381         switch (offset) {
 382         case 0x100 ... 0x11C:
 383             if (offset == 0x10C) {
 384                 goto bad_reg;
 385             }
 386             s->pll[(offset - 0x100) / 4] = val;
 387             break;
 388         case 0x120 ... 0x16C:
 389             s->clk[(offset - 0x120) / 4] = val;
 390             break;
 391         case 0x170 ... 0x1AC:
 392             s->fpga[0][(offset - 0x170) / 4] = val;
 393             break;
 394         case 0x1B0 ... 0x1D8:
 395             s->misc[(offset - 0x1B0) / 4] = val;
 396             break;
 397         case 0x200 ... 0x25C:
 398             if (offset == 0x250) {
 399                 goto bad_reg;
 400             }
 401             s->reset[(offset - 0x200) / 4] = val;
 402             break;
 403         case 0x300:
 404             s->apu_ctrl = val;
 405             break;
 406         case 0x304:
 407             s->wdt_clk_sel = val;
 408             break;
 409         case 0x400 ... 0x408:
 410             s->tz_ocm[(offset - 0x400) / 4] = val;
 411             break;
 412         case 0x430:
 413             s->tz_ddr = val;
 414             break;
 415         case 0x440 ... 0x448:
 416             s->tz_dma[(offset - 0x440) / 4] = val;
 417             break;
 418         case 0x450 ... 0x458:
 419             s->tz_misc[(offset - 0x450) / 4] = val;
 420             break;
 421         case 0x484 ... 0x488:
 422             s->tz_fpga[(offset - 0x484) / 4] = val;
 423             break;
 424         case 0x500:
 425             s->dbg_ctrl = val;
 426             break;
 427         case 0x530:
 428             s->pss_idcode = val;
 429             break;
 430         case 0x600 ... 0x620:
 431             if (offset == 0x604) {
 432                 goto bad_reg;
 433             }
 434             s->ddr[(offset - 0x600) / 4] = val;
 435             break;
 436         case 0x700 ... 0x7D4:
 437             s->mio[(offset - 0x700) / 4] = val;
 438             break;
 439         case 0x800 ... 0x810:
 440             s->mio_func[(offset - 0x800) / 4] = val;
 441             break;
 442         case 0x830 ... 0x834:
 443             s->sd[(offset - 0x830) / 4] = val;
 444             break;
 445         case 0x900:
 446             s->lvl_shftr_en = val;
 447             break;
 448         case 0x910:
 449             break;
 450         case 0xA00 ... 0xA1C:
 451             s->cpu_ram[(offset - 0xA00) / 4] = val;
 452             break;
 453         case 0xA30 ... 0xA48:
 454             s->iou[(offset - 0xA30) / 4] = val;
 455             break;
 456         case 0xA50:
 457             s->dmac_ram = val;
 458             break;
 459         case 0xA60 ... 0xA8C:
 460             s->afi[0][(offset - 0xA60) / 4] = val;
 461             break;
 462         case 0xA90:
 463             s->ocm[0] = val;
 464             break;
 465         case 0xAA0:
 466             s->devci_ram = val;
 467             break;
 468         case 0xAB0:
 469             s->csg_ram = val;
 470             break;
 471         case 0xB00 ... 0xB2C:
 472             if (offset == 0xB20 || offset == 0xB2C) {
 473                 goto bad_reg;
 474             }
 475             s->gpiob[(offset - 0xB00) / 4] = val;
 476             break;
 477         case 0xB40 ... 0xB74:
 478             s->ddriob[(offset - 0xB40) / 4] = val;
 479             break;
 480         default:
 481         bad_reg:
 482             DB_PRINT("Bad register write %x <= %08x\n", (int)offset,
 483                      (unsigned)val);
 484         }
 485     } else {
 486         DB_PRINT("SCLR registers are locked. Unlock them first\n");
 487     }
 488 }
 489
 490 static const MemoryRegionOps slcr_ops = {
 491     .read = zynq_slcr_read,
 492     .write = zynq_slcr_write,
 493     .endianness = DEVICE_NATIVE_ENDIAN,
 494 };
 495
 496 static int zynq_slcr_init(SysBusDevice *dev)
 497 {
 498     ZynqSLCRState *s = ZYNQ_SLCR(dev);
 499
 500     memory_region_init_io(&s->iomem, OBJECT(s), &slcr_ops, s, "slcr", 0x1000);
 501     sysbus_init_mmio(dev, &s->iomem);
 502
 503     return 0;
 504 }
 505
 506 static const VMStateDescription vmstate_zynq_slcr = {
 507     .name = "zynq_slcr",
 508     .version_id = 1,
 509     .minimum_version_id = 1,
 510     .minimum_version_id_old = 1,
 511     .fields      = (VMStateField[]) {
 512         VMSTATE_UINT8_ARRAY(data, ZynqSLCRState, 0x1000),
 513         VMSTATE_END_OF_LIST()
 514     }
 515 };
 516
 517 static void zynq_slcr_class_init(ObjectClass *klass, void *data)
 518 {
 519     DeviceClass *dc = DEVICE_CLASS(klass);
 520     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 521
 522     sdc->init = zynq_slcr_init;
 523     dc->vmsd = &vmstate_zynq_slcr;
 524     dc->reset = zynq_slcr_reset;
 525 }
 526
 527 static const TypeInfo zynq_slcr_info = {
 528     .class_init = zynq_slcr_class_init,
 529     .name  = TYPE_ZYNQ_SLCR,
 530     .parent = TYPE_SYS_BUS_DEVICE,
 531     .instance_size  = sizeof(ZynqSLCRState),
 532 };
 533
 534 static void zynq_slcr_register_types(void)
 535 {
 536     type_register_static(&zynq_slcr_info);
 537 }
 538
 539 type_init(zynq_slcr_register_types)