hw/mst_fpga.c

   1 /*
   2  * PXA270-based Intel Mainstone platforms.
   3  * FPGA driver
   4  *
   5  * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
   6  *                                    <akuster@mvista.com>
   7  *
   8  * This code is licensed under the GNU GPL v2.
   9  */
  10 #include "hw.h"
  11 #include "sysbus.h"
  12
  13 /* Mainstone FPGA for extern irqs */
  14 #define FPGA_GPIO_PIN   0
  15 #define MST_NUM_IRQS    16
  16 #define MST_LEDDAT1             0x10
  17 #define MST_LEDDAT2             0x14
  18 #define MST_LEDCTRL             0x40
  19 #define MST_GPSWR               0x60
  20 #define MST_MSCWR1              0x80
  21 #define MST_MSCWR2              0x84
  22 #define MST_MSCWR3              0x88
  23 #define MST_MSCRD               0x90
  24 #define MST_INTMSKENA   0xc0
  25 #define MST_INTSETCLR   0xd0
  26 #define MST_PCMCIA0             0xe0
  27 #define MST_PCMCIA1             0xe4
  28
  29 typedef struct mst_irq_state{
  30         SysBusDevice busdev;
  31
  32         qemu_irq parent;
  33
  34         uint32_t prev_level;
  35         uint32_t leddat1;
  36         uint32_t leddat2;
  37         uint32_t ledctrl;
  38         uint32_t gpswr;
  39         uint32_t mscwr1;
  40         uint32_t mscwr2;
  41         uint32_t mscwr3;
  42         uint32_t mscrd;
  43         uint32_t intmskena;
  44         uint32_t intsetclr;
  45         uint32_t pcmcia0;
  46         uint32_t pcmcia1;
  47 }mst_irq_state;
  48
  49 static void
  50 mst_fpga_set_irq(void *opaque, int irq, int level)
  51 {
  52         mst_irq_state *s = (mst_irq_state *)opaque;
  53         uint32_t oldint = s->intsetclr & s->intmskena;
  54
  55         if (level)
  56                 s->prev_level |= 1u << irq;
  57         else
  58                 s->prev_level &= ~(1u << irq);
  59
  60         if ((s->intmskena & (1u << irq)) && level)
  61                 s->intsetclr |= 1u << irq;
  62
  63         if (oldint != (s->intsetclr & s->intmskena))
  64                 qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
  65 }
  66
  67
  68 static uint32_t
  69 mst_fpga_readb(void *opaque, target_phys_addr_t addr)
  70 {
  71         mst_irq_state *s = (mst_irq_state *) opaque;
  72
  73         switch (addr) {
  74         case MST_LEDDAT1:
  75                 return s->leddat1;
  76         case MST_LEDDAT2:
  77                 return s->leddat2;
  78         case MST_LEDCTRL:
  79                 return s->ledctrl;
  80         case MST_GPSWR:
  81                 return s->gpswr;
  82         case MST_MSCWR1:
  83                 return s->mscwr1;
  84         case MST_MSCWR2:
  85                 return s->mscwr2;
  86         case MST_MSCWR3:
  87                 return s->mscwr3;
  88         case MST_MSCRD:
  89                 return s->mscrd;
  90         case MST_INTMSKENA:
  91                 return s->intmskena;
  92         case MST_INTSETCLR:
  93                 return s->intsetclr;
  94         case MST_PCMCIA0:
  95                 return s->pcmcia0;
  96         case MST_PCMCIA1:
  97                 return s->pcmcia1;
  98         default:
  99                 printf("Mainstone - mst_fpga_readb: Bad register offset "
 100                         "0x" TARGET_FMT_plx " \n", addr);
 101         }
 102         return 0;
 103 }
 104
 105 static void
 106 mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
 107 {
 108         mst_irq_state *s = (mst_irq_state *) opaque;
 109         value &= 0xffffffff;
 110
 111         switch (addr) {
 112         case MST_LEDDAT1:
 113                 s->leddat1 = value;
 114                 break;
 115         case MST_LEDDAT2:
 116                 s->leddat2 = value;
 117                 break;
 118         case MST_LEDCTRL:
 119                 s->ledctrl = value;
 120                 break;
 121         case MST_GPSWR:
 122                 s->gpswr = value;
 123                 break;
 124         case MST_MSCWR1:
 125                 s->mscwr1 = value;
 126                 break;
 127         case MST_MSCWR2:
 128                 s->mscwr2 = value;
 129                 break;
 130         case MST_MSCWR3:
 131                 s->mscwr3 = value;
 132                 break;
 133         case MST_MSCRD:
 134                 s->mscrd =  value;
 135                 break;
 136         case MST_INTMSKENA:     /* Mask interupt */
 137                 s->intmskena = (value & 0xFEEFF);
 138                 qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
 139                 break;
 140         case MST_INTSETCLR:     /* clear or set interrupt */
 141                 s->intsetclr = (value & 0xFEEFF);
 142                 qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
 143                 break;
 144         case MST_PCMCIA0:
 145                 s->pcmcia0 = value;
 146                 break;
 147         case MST_PCMCIA1:
 148                 s->pcmcia1 = value;
 149                 break;
 150         default:
 151                 printf("Mainstone - mst_fpga_writeb: Bad register offset "
 152                         "0x" TARGET_FMT_plx " \n", addr);
 153         }
 154 }
 155
 156 static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
 157         mst_fpga_readb,
 158         mst_fpga_readb,
 159         mst_fpga_readb,
 160 };
 161 static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
 162         mst_fpga_writeb,
 163         mst_fpga_writeb,
 164         mst_fpga_writeb,
 165 };
 166
 167
 168 static int mst_fpga_post_load(void *opaque, int version_id)
 169 {
 170         mst_irq_state *s = (mst_irq_state *) opaque;
 171
 172         qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
 173         return 0;
 174 }
 175
 176 static int mst_fpga_init(SysBusDevice *dev)
 177 {
 178         mst_irq_state *s;
 179         int iomemtype;
 180
 181         s = FROM_SYSBUS(mst_irq_state, dev);
 182
 183         sysbus_init_irq(dev, &s->parent);
 184
 185         /* alloc the external 16 irqs */
 186         qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
 187
 188         iomemtype = cpu_register_io_memory(mst_fpga_readfn,
 189                 mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
 190         sysbus_init_mmio(dev, 0x00100000, iomemtype);
 191         return 0;
 192 }
 193
 194 static VMStateDescription vmstate_mst_fpga_regs = {
 195         .name = "mainstone_fpga",
 196         .version_id = 0,
 197         .minimum_version_id = 0,
 198         .minimum_version_id_old = 0,
 199         .post_load = mst_fpga_post_load,
 200         .fields = (VMStateField []) {
 201                 VMSTATE_UINT32(prev_level, mst_irq_state),
 202                 VMSTATE_UINT32(leddat1, mst_irq_state),
 203                 VMSTATE_UINT32(leddat2, mst_irq_state),
 204                 VMSTATE_UINT32(ledctrl, mst_irq_state),
 205                 VMSTATE_UINT32(gpswr, mst_irq_state),
 206                 VMSTATE_UINT32(mscwr1, mst_irq_state),
 207                 VMSTATE_UINT32(mscwr2, mst_irq_state),
 208                 VMSTATE_UINT32(mscwr3, mst_irq_state),
 209                 VMSTATE_UINT32(mscrd, mst_irq_state),
 210                 VMSTATE_UINT32(intmskena, mst_irq_state),
 211                 VMSTATE_UINT32(intsetclr, mst_irq_state),
 212                 VMSTATE_UINT32(pcmcia0, mst_irq_state),
 213                 VMSTATE_UINT32(pcmcia1, mst_irq_state),
 214                 VMSTATE_END_OF_LIST(),
 215         },
 216 };
 217
 218 static SysBusDeviceInfo mst_fpga_info = {
 219         .init = mst_fpga_init,
 220         .qdev.name = "mainstone-fpga",
 221         .qdev.desc = "Mainstone II FPGA",
 222         .qdev.size = sizeof(mst_irq_state),
 223         .qdev.vmsd = &vmstate_mst_fpga_regs,
 224 };
 225
 226 static void mst_fpga_register(void)
 227 {
 228         sysbus_register_withprop(&mst_fpga_info);
 229 }
 230 device_init(mst_fpga_register);