hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "sysbus.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "i2c.h"
  21
  22 #define MP_MISC_BASE            0x80002000
  23 #define MP_MISC_SIZE            0x00001000
  24
  25 #define MP_ETH_BASE             0x80008000
  26 #define MP_ETH_SIZE             0x00001000
  27
  28 #define MP_WLAN_BASE            0x8000C000
  29 #define MP_WLAN_SIZE            0x00000800
  30
  31 #define MP_UART1_BASE           0x8000C840
  32 #define MP_UART2_BASE           0x8000C940
  33
  34 #define MP_GPIO_BASE            0x8000D000
  35 #define MP_GPIO_SIZE            0x00001000
  36
  37 #define MP_FLASHCFG_BASE        0x90006000
  38 #define MP_FLASHCFG_SIZE        0x00001000
  39
  40 #define MP_AUDIO_BASE           0x90007000
  41
  42 #define MP_PIC_BASE             0x90008000
  43 #define MP_PIC_SIZE             0x00001000
  44
  45 #define MP_PIT_BASE             0x90009000
  46 #define MP_PIT_SIZE             0x00001000
  47
  48 #define MP_LCD_BASE             0x9000c000
  49 #define MP_LCD_SIZE             0x00001000
  50
  51 #define MP_SRAM_BASE            0xC0000000
  52 #define MP_SRAM_SIZE            0x00020000
  53
  54 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  55 #define MP_FLASH_SIZE_MAX       32*1024*1024
  56
  57 #define MP_TIMER1_IRQ           4
  58 #define MP_TIMER2_IRQ           5
  59 #define MP_TIMER3_IRQ           6
  60 #define MP_TIMER4_IRQ           7
  61 #define MP_EHCI_IRQ             8
  62 #define MP_ETH_IRQ              9
  63 #define MP_UART1_IRQ            11
  64 #define MP_UART2_IRQ            11
  65 #define MP_GPIO_IRQ             12
  66 #define MP_RTC_IRQ              28
  67 #define MP_AUDIO_IRQ            30
  68
  69 /* Wolfson 8750 I2C address */
  70 #define MP_WM_ADDR              0x34
  71
  72 /* Ethernet register offsets */
  73 #define MP_ETH_SMIR             0x010
  74 #define MP_ETH_PCXR             0x408
  75 #define MP_ETH_SDCMR            0x448
  76 #define MP_ETH_ICR              0x450
  77 #define MP_ETH_IMR              0x458
  78 #define MP_ETH_FRDP0            0x480
  79 #define MP_ETH_FRDP1            0x484
  80 #define MP_ETH_FRDP2            0x488
  81 #define MP_ETH_FRDP3            0x48C
  82 #define MP_ETH_CRDP0            0x4A0
  83 #define MP_ETH_CRDP1            0x4A4
  84 #define MP_ETH_CRDP2            0x4A8
  85 #define MP_ETH_CRDP3            0x4AC
  86 #define MP_ETH_CTDP0            0x4E0
  87 #define MP_ETH_CTDP1            0x4E4
  88 #define MP_ETH_CTDP2            0x4E8
  89 #define MP_ETH_CTDP3            0x4EC
  90
  91 /* MII PHY access */
  92 #define MP_ETH_SMIR_DATA        0x0000FFFF
  93 #define MP_ETH_SMIR_ADDR        0x03FF0000
  94 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
  95 #define MP_ETH_SMIR_RDVALID     (1 << 27)
  96
  97 /* PHY registers */
  98 #define MP_ETH_PHY1_BMSR        0x00210000
  99 #define MP_ETH_PHY1_PHYSID1     0x00410000
 100 #define MP_ETH_PHY1_PHYSID2     0x00610000
 101
 102 #define MP_PHY_BMSR_LINK        0x0004
 103 #define MP_PHY_BMSR_AUTONEG     0x0008
 104
 105 #define MP_PHY_88E3015          0x01410E20
 106
 107 /* TX descriptor status */
 108 #define MP_ETH_TX_OWN           (1 << 31)
 109
 110 /* RX descriptor status */
 111 #define MP_ETH_RX_OWN           (1 << 31)
 112
 113 /* Interrupt cause/mask bits */
 114 #define MP_ETH_IRQ_RX_BIT       0
 115 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 116 #define MP_ETH_IRQ_TXHI_BIT     2
 117 #define MP_ETH_IRQ_TXLO_BIT     3
 118
 119 /* Port config bits */
 120 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 121
 122 /* SDMA command bits */
 123 #define MP_ETH_CMD_TXHI         (1 << 23)
 124 #define MP_ETH_CMD_TXLO         (1 << 22)
 125
 126 typedef struct mv88w8618_tx_desc {
 127     uint32_t cmdstat;
 128     uint16_t res;
 129     uint16_t bytes;
 130     uint32_t buffer;
 131     uint32_t next;
 132 } mv88w8618_tx_desc;
 133
 134 typedef struct mv88w8618_rx_desc {
 135     uint32_t cmdstat;
 136     uint16_t bytes;
 137     uint16_t buffer_size;
 138     uint32_t buffer;
 139     uint32_t next;
 140 } mv88w8618_rx_desc;
 141
 142 typedef struct mv88w8618_eth_state {
 143     SysBusDevice busdev;
 144     qemu_irq irq;
 145     uint32_t smir;
 146     uint32_t icr;
 147     uint32_t imr;
 148     int mmio_index;
 149     int vlan_header;
 150     uint32_t tx_queue[2];
 151     uint32_t rx_queue[4];
 152     uint32_t frx_queue[4];
 153     uint32_t cur_rx[4];
 154     VLANClientState *vc;
 155 } mv88w8618_eth_state;
 156
 157 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 158 {
 159     cpu_to_le32s(&desc->cmdstat);
 160     cpu_to_le16s(&desc->bytes);
 161     cpu_to_le16s(&desc->buffer_size);
 162     cpu_to_le32s(&desc->buffer);
 163     cpu_to_le32s(&desc->next);
 164     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 165 }
 166
 167 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 168 {
 169     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 170     le32_to_cpus(&desc->cmdstat);
 171     le16_to_cpus(&desc->bytes);
 172     le16_to_cpus(&desc->buffer_size);
 173     le32_to_cpus(&desc->buffer);
 174     le32_to_cpus(&desc->next);
 175 }
 176
 177 static int eth_can_receive(VLANClientState *vc)
 178 {
 179     return 1;
 180 }
 181
 182 static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
 183 {
 184     mv88w8618_eth_state *s = vc->opaque;
 185     uint32_t desc_addr;
 186     mv88w8618_rx_desc desc;
 187     int i;
 188
 189     for (i = 0; i < 4; i++) {
 190         desc_addr = s->cur_rx[i];
 191         if (!desc_addr) {
 192             continue;
 193         }
 194         do {
 195             eth_rx_desc_get(desc_addr, &desc);
 196             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 197                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 198                                           buf, size);
 199                 desc.bytes = size + s->vlan_header;
 200                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 201                 s->cur_rx[i] = desc.next;
 202
 203                 s->icr |= MP_ETH_IRQ_RX;
 204                 if (s->icr & s->imr) {
 205                     qemu_irq_raise(s->irq);
 206                 }
 207                 eth_rx_desc_put(desc_addr, &desc);
 208                 return size;
 209             }
 210             desc_addr = desc.next;
 211         } while (desc_addr != s->rx_queue[i]);
 212     }
 213     return size;
 214 }
 215
 216 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 217 {
 218     cpu_to_le32s(&desc->cmdstat);
 219     cpu_to_le16s(&desc->res);
 220     cpu_to_le16s(&desc->bytes);
 221     cpu_to_le32s(&desc->buffer);
 222     cpu_to_le32s(&desc->next);
 223     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 224 }
 225
 226 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 227 {
 228     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 229     le32_to_cpus(&desc->cmdstat);
 230     le16_to_cpus(&desc->res);
 231     le16_to_cpus(&desc->bytes);
 232     le32_to_cpus(&desc->buffer);
 233     le32_to_cpus(&desc->next);
 234 }
 235
 236 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 237 {
 238     uint32_t desc_addr = s->tx_queue[queue_index];
 239     mv88w8618_tx_desc desc;
 240     uint8_t buf[2048];
 241     int len;
 242
 243     if (!desc_addr) {
 244         return;
 245     }
 246     do {
 247         eth_tx_desc_get(desc_addr, &desc);
 248         if (desc.cmdstat & MP_ETH_TX_OWN) {
 249             len = desc.bytes;
 250             if (len < 2048) {
 251                 cpu_physical_memory_read(desc.buffer, buf, len);
 252                 qemu_send_packet(s->vc, buf, len);
 253             }
 254             desc.cmdstat &= ~MP_ETH_TX_OWN;
 255             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 256             eth_tx_desc_put(desc_addr, &desc);
 257         }
 258         desc_addr = desc.next;
 259     } while (desc_addr != s->tx_queue[queue_index]);
 260 }
 261
 262 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 263 {
 264     mv88w8618_eth_state *s = opaque;
 265
 266     switch (offset) {
 267     case MP_ETH_SMIR:
 268         if (s->smir & MP_ETH_SMIR_OPCODE) {
 269             switch (s->smir & MP_ETH_SMIR_ADDR) {
 270             case MP_ETH_PHY1_BMSR:
 271                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 272                        MP_ETH_SMIR_RDVALID;
 273             case MP_ETH_PHY1_PHYSID1:
 274                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 275             case MP_ETH_PHY1_PHYSID2:
 276                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 277             default:
 278                 return MP_ETH_SMIR_RDVALID;
 279             }
 280         }
 281         return 0;
 282
 283     case MP_ETH_ICR:
 284         return s->icr;
 285
 286     case MP_ETH_IMR:
 287         return s->imr;
 288
 289     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 290         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 291
 292     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 293         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 294
 295     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 296         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 297
 298     default:
 299         return 0;
 300     }
 301 }
 302
 303 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 304                                 uint32_t value)
 305 {
 306     mv88w8618_eth_state *s = opaque;
 307
 308     switch (offset) {
 309     case MP_ETH_SMIR:
 310         s->smir = value;
 311         break;
 312
 313     case MP_ETH_PCXR:
 314         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 315         break;
 316
 317     case MP_ETH_SDCMR:
 318         if (value & MP_ETH_CMD_TXHI) {
 319             eth_send(s, 1);
 320         }
 321         if (value & MP_ETH_CMD_TXLO) {
 322             eth_send(s, 0);
 323         }
 324         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 325             qemu_irq_raise(s->irq);
 326         }
 327         break;
 328
 329     case MP_ETH_ICR:
 330         s->icr &= value;
 331         break;
 332
 333     case MP_ETH_IMR:
 334         s->imr = value;
 335         if (s->icr & s->imr) {
 336             qemu_irq_raise(s->irq);
 337         }
 338         break;
 339
 340     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 341         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 342         break;
 343
 344     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 345         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 346             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 347         break;
 348
 349     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 350         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 351         break;
 352     }
 353 }
 354
 355 static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
 356     mv88w8618_eth_read,
 357     mv88w8618_eth_read,
 358     mv88w8618_eth_read
 359 };
 360
 361 static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
 362     mv88w8618_eth_write,
 363     mv88w8618_eth_write,
 364     mv88w8618_eth_write
 365 };
 366
 367 static void eth_cleanup(VLANClientState *vc)
 368 {
 369     mv88w8618_eth_state *s = vc->opaque;
 370
 371     cpu_unregister_io_memory(s->mmio_index);
 372
 373     qemu_free(s);
 374 }
 375
 376 static int mv88w8618_eth_init(SysBusDevice *dev)
 377 {
 378     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 379
 380     sysbus_init_irq(dev, &s->irq);
 381     s->vc = qdev_get_vlan_client(&dev->qdev,
 382                                  eth_can_receive, eth_receive, NULL,
 383                                  eth_cleanup, s);
 384     s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
 385                                            mv88w8618_eth_writefn, s);
 386     sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
 387     return 0;
 388 }
 389
 390 /* LCD register offsets */
 391 #define MP_LCD_IRQCTRL          0x180
 392 #define MP_LCD_IRQSTAT          0x184
 393 #define MP_LCD_SPICTRL          0x1ac
 394 #define MP_LCD_INST             0x1bc
 395 #define MP_LCD_DATA             0x1c0
 396
 397 /* Mode magics */
 398 #define MP_LCD_SPI_DATA         0x00100011
 399 #define MP_LCD_SPI_CMD          0x00104011
 400 #define MP_LCD_SPI_INVALID      0x00000000
 401
 402 /* Commmands */
 403 #define MP_LCD_INST_SETPAGE0    0xB0
 404 /* ... */
 405 #define MP_LCD_INST_SETPAGE7    0xB7
 406
 407 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 408
 409 typedef struct musicpal_lcd_state {
 410     SysBusDevice busdev;
 411     uint32_t brightness;
 412     uint32_t mode;
 413     uint32_t irqctrl;
 414     int page;
 415     int page_off;
 416     DisplayState *ds;
 417     uint8_t video_ram[128*64/8];
 418 } musicpal_lcd_state;
 419
 420 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 421 {
 422     switch (s->brightness) {
 423     case 7:
 424         return col;
 425     case 0:
 426         return 0;
 427     default:
 428         return (col * s->brightness) / 7;
 429     }
 430 }
 431
 432 #define SET_LCD_PIXEL(depth, type) \
 433 static inline void glue(set_lcd_pixel, depth) \
 434         (musicpal_lcd_state *s, int x, int y, type col) \
 435 { \
 436     int dx, dy; \
 437     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 438 \
 439     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 440         for (dx = 0; dx < 3; dx++, pixel++) \
 441             *pixel = col; \
 442 }
 443 SET_LCD_PIXEL(8, uint8_t)
 444 SET_LCD_PIXEL(16, uint16_t)
 445 SET_LCD_PIXEL(32, uint32_t)
 446
 447 #include "pixel_ops.h"
 448
 449 static void lcd_refresh(void *opaque)
 450 {
 451     musicpal_lcd_state *s = opaque;
 452     int x, y, col;
 453
 454     switch (ds_get_bits_per_pixel(s->ds)) {
 455     case 0:
 456         return;
 457 #define LCD_REFRESH(depth, func) \
 458     case depth: \
 459         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 460                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 461                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 462         for (x = 0; x < 128; x++) { \
 463             for (y = 0; y < 64; y++) { \
 464                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 465                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 466                 } else { \
 467                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 468                 } \
 469             } \
 470         } \
 471         break;
 472     LCD_REFRESH(8, rgb_to_pixel8)
 473     LCD_REFRESH(16, rgb_to_pixel16)
 474     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 475                      rgb_to_pixel32bgr : rgb_to_pixel32))
 476     default:
 477         hw_error("unsupported colour depth %i\n",
 478                   ds_get_bits_per_pixel(s->ds));
 479     }
 480
 481     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 482 }
 483
 484 static void lcd_invalidate(void *opaque)
 485 {
 486 }
 487
 488 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 489 {
 490     musicpal_lcd_state *s = opaque;
 491     s->brightness &= ~(1 << irq);
 492     s->brightness |= level << irq;
 493 }
 494
 495 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 496 {
 497     musicpal_lcd_state *s = opaque;
 498
 499     switch (offset) {
 500     case MP_LCD_IRQCTRL:
 501         return s->irqctrl;
 502
 503     default:
 504         return 0;
 505     }
 506 }
 507
 508 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 509                                uint32_t value)
 510 {
 511     musicpal_lcd_state *s = opaque;
 512
 513     switch (offset) {
 514     case MP_LCD_IRQCTRL:
 515         s->irqctrl = value;
 516         break;
 517
 518     case MP_LCD_SPICTRL:
 519         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 520             s->mode = value;
 521         } else {
 522             s->mode = MP_LCD_SPI_INVALID;
 523         }
 524         break;
 525
 526     case MP_LCD_INST:
 527         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 528             s->page = value - MP_LCD_INST_SETPAGE0;
 529             s->page_off = 0;
 530         }
 531         break;
 532
 533     case MP_LCD_DATA:
 534         if (s->mode == MP_LCD_SPI_CMD) {
 535             if (value >= MP_LCD_INST_SETPAGE0 &&
 536                 value <= MP_LCD_INST_SETPAGE7) {
 537                 s->page = value - MP_LCD_INST_SETPAGE0;
 538                 s->page_off = 0;
 539             }
 540         } else if (s->mode == MP_LCD_SPI_DATA) {
 541             s->video_ram[s->page*128 + s->page_off] = value;
 542             s->page_off = (s->page_off + 1) & 127;
 543         }
 544         break;
 545     }
 546 }
 547
 548 static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
 549     musicpal_lcd_read,
 550     musicpal_lcd_read,
 551     musicpal_lcd_read
 552 };
 553
 554 static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
 555     musicpal_lcd_write,
 556     musicpal_lcd_write,
 557     musicpal_lcd_write
 558 };
 559
 560 static int musicpal_lcd_init(SysBusDevice *dev)
 561 {
 562     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 563     int iomemtype;
 564
 565     s->brightness = 7;
 566
 567     iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
 568                                        musicpal_lcd_writefn, s);
 569     sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
 570
 571     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 572                                  NULL, NULL, s);
 573     qemu_console_resize(s->ds, 128*3, 64*3);
 574
 575     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 576
 577     return 0;
 578 }
 579
 580 /* PIC register offsets */
 581 #define MP_PIC_STATUS           0x00
 582 #define MP_PIC_ENABLE_SET       0x08
 583 #define MP_PIC_ENABLE_CLR       0x0C
 584
 585 typedef struct mv88w8618_pic_state
 586 {
 587     SysBusDevice busdev;
 588     uint32_t level;
 589     uint32_t enabled;
 590     qemu_irq parent_irq;
 591 } mv88w8618_pic_state;
 592
 593 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 594 {
 595     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 596 }
 597
 598 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 599 {
 600     mv88w8618_pic_state *s = opaque;
 601
 602     if (level) {
 603         s->level |= 1 << irq;
 604     } else {
 605         s->level &= ~(1 << irq);
 606     }
 607     mv88w8618_pic_update(s);
 608 }
 609
 610 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 611 {
 612     mv88w8618_pic_state *s = opaque;
 613
 614     switch (offset) {
 615     case MP_PIC_STATUS:
 616         return s->level & s->enabled;
 617
 618     default:
 619         return 0;
 620     }
 621 }
 622
 623 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 624                                 uint32_t value)
 625 {
 626     mv88w8618_pic_state *s = opaque;
 627
 628     switch (offset) {
 629     case MP_PIC_ENABLE_SET:
 630         s->enabled |= value;
 631         break;
 632
 633     case MP_PIC_ENABLE_CLR:
 634         s->enabled &= ~value;
 635         s->level &= ~value;
 636         break;
 637     }
 638     mv88w8618_pic_update(s);
 639 }
 640
 641 static void mv88w8618_pic_reset(void *opaque)
 642 {
 643     mv88w8618_pic_state *s = opaque;
 644
 645     s->level = 0;
 646     s->enabled = 0;
 647 }
 648
 649 static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
 650     mv88w8618_pic_read,
 651     mv88w8618_pic_read,
 652     mv88w8618_pic_read
 653 };
 654
 655 static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
 656     mv88w8618_pic_write,
 657     mv88w8618_pic_write,
 658     mv88w8618_pic_write
 659 };
 660
 661 static int mv88w8618_pic_init(SysBusDevice *dev)
 662 {
 663     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 664     int iomemtype;
 665
 666     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 667     sysbus_init_irq(dev, &s->parent_irq);
 668     iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
 669                                        mv88w8618_pic_writefn, s);
 670     sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
 671
 672     qemu_register_reset(mv88w8618_pic_reset, s);
 673     return 0;
 674 }
 675
 676 /* PIT register offsets */
 677 #define MP_PIT_TIMER1_LENGTH    0x00
 678 /* ... */
 679 #define MP_PIT_TIMER4_LENGTH    0x0C
 680 #define MP_PIT_CONTROL          0x10
 681 #define MP_PIT_TIMER1_VALUE     0x14
 682 /* ... */
 683 #define MP_PIT_TIMER4_VALUE     0x20
 684 #define MP_BOARD_RESET          0x34
 685
 686 /* Magic board reset value (probably some watchdog behind it) */
 687 #define MP_BOARD_RESET_MAGIC    0x10000
 688
 689 typedef struct mv88w8618_timer_state {
 690     ptimer_state *ptimer;
 691     uint32_t limit;
 692     int freq;
 693     qemu_irq irq;
 694 } mv88w8618_timer_state;
 695
 696 typedef struct mv88w8618_pit_state {
 697     SysBusDevice busdev;
 698     mv88w8618_timer_state timer[4];
 699 } mv88w8618_pit_state;
 700
 701 static void mv88w8618_timer_tick(void *opaque)
 702 {
 703     mv88w8618_timer_state *s = opaque;
 704
 705     qemu_irq_raise(s->irq);
 706 }
 707
 708 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 709                                  uint32_t freq)
 710 {
 711     QEMUBH *bh;
 712
 713     sysbus_init_irq(dev, &s->irq);
 714     s->freq = freq;
 715
 716     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 717     s->ptimer = ptimer_init(bh);
 718 }
 719
 720 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
 721 {
 722     mv88w8618_pit_state *s = opaque;
 723     mv88w8618_timer_state *t;
 724
 725     switch (offset) {
 726     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 727         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 728         return ptimer_get_count(t->ptimer);
 729
 730     default:
 731         return 0;
 732     }
 733 }
 734
 735 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 736                                 uint32_t value)
 737 {
 738     mv88w8618_pit_state *s = opaque;
 739     mv88w8618_timer_state *t;
 740     int i;
 741
 742     switch (offset) {
 743     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 744         t = &s->timer[offset >> 2];
 745         t->limit = value;
 746         if (t->limit > 0) {
 747             ptimer_set_limit(t->ptimer, t->limit, 1);
 748         } else {
 749             ptimer_stop(t->ptimer);
 750         }
 751         break;
 752
 753     case MP_PIT_CONTROL:
 754         for (i = 0; i < 4; i++) {
 755             t = &s->timer[i];
 756             if (value & 0xf && t->limit > 0) {
 757                 ptimer_set_limit(t->ptimer, t->limit, 0);
 758                 ptimer_set_freq(t->ptimer, t->freq);
 759                 ptimer_run(t->ptimer, 0);
 760             } else {
 761                 ptimer_stop(t->ptimer);
 762             }
 763             value >>= 4;
 764         }
 765         break;
 766
 767     case MP_BOARD_RESET:
 768         if (value == MP_BOARD_RESET_MAGIC) {
 769             qemu_system_reset_request();
 770         }
 771         break;
 772     }
 773 }
 774
 775 static void mv88w8618_pit_reset(void *opaque)
 776 {
 777     mv88w8618_pit_state *s = opaque;
 778     int i;
 779
 780     for (i = 0; i < 4; i++) {
 781         ptimer_stop(s->timer[i].ptimer);
 782         s->timer[i].limit = 0;
 783     }
 784 }
 785
 786 static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
 787     mv88w8618_pit_read,
 788     mv88w8618_pit_read,
 789     mv88w8618_pit_read
 790 };
 791
 792 static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
 793     mv88w8618_pit_write,
 794     mv88w8618_pit_write,
 795     mv88w8618_pit_write
 796 };
 797
 798 static int mv88w8618_pit_init(SysBusDevice *dev)
 799 {
 800     int iomemtype;
 801     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 802     int i;
 803
 804     /* Letting them all run at 1 MHz is likely just a pragmatic
 805      * simplification. */
 806     for (i = 0; i < 4; i++) {
 807         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 808     }
 809
 810     iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
 811                                        mv88w8618_pit_writefn, s);
 812     sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
 813     return 0;
 814 }
 815
 816 static SysBusDeviceInfo mv88w8618_pit_info = {
 817     .init = mv88w8618_pit_init,
 818     .qdev.name  = "mv88w8618_pit",
 819     .qdev.size  = sizeof(mv88w8618_pit_state),
 820     .qdev.reset = mv88w8618_pit_reset,
 821 };
 822
 823 /* Flash config register offsets */
 824 #define MP_FLASHCFG_CFGR0    0x04
 825
 826 typedef struct mv88w8618_flashcfg_state {
 827     SysBusDevice busdev;
 828     uint32_t cfgr0;
 829 } mv88w8618_flashcfg_state;
 830
 831 static uint32_t mv88w8618_flashcfg_read(void *opaque,
 832                                         target_phys_addr_t offset)
 833 {
 834     mv88w8618_flashcfg_state *s = opaque;
 835
 836     switch (offset) {
 837     case MP_FLASHCFG_CFGR0:
 838         return s->cfgr0;
 839
 840     default:
 841         return 0;
 842     }
 843 }
 844
 845 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 846                                      uint32_t value)
 847 {
 848     mv88w8618_flashcfg_state *s = opaque;
 849
 850     switch (offset) {
 851     case MP_FLASHCFG_CFGR0:
 852         s->cfgr0 = value;
 853         break;
 854     }
 855 }
 856
 857 static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
 858     mv88w8618_flashcfg_read,
 859     mv88w8618_flashcfg_read,
 860     mv88w8618_flashcfg_read
 861 };
 862
 863 static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
 864     mv88w8618_flashcfg_write,
 865     mv88w8618_flashcfg_write,
 866     mv88w8618_flashcfg_write
 867 };
 868
 869 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 870 {
 871     int iomemtype;
 872     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 873
 874     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 875     iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
 876                                        mv88w8618_flashcfg_writefn, s);
 877     sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
 878     return 0;
 879 }
 880
 881 /* Misc register offsets */
 882 #define MP_MISC_BOARD_REVISION  0x18
 883
 884 #define MP_BOARD_REVISION       0x31
 885
 886 static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
 887 {
 888     switch (offset) {
 889     case MP_MISC_BOARD_REVISION:
 890         return MP_BOARD_REVISION;
 891
 892     default:
 893         return 0;
 894     }
 895 }
 896
 897 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
 898                                 uint32_t value)
 899 {
 900 }
 901
 902 static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
 903     musicpal_misc_read,
 904     musicpal_misc_read,
 905     musicpal_misc_read,
 906 };
 907
 908 static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
 909     musicpal_misc_write,
 910     musicpal_misc_write,
 911     musicpal_misc_write,
 912 };
 913
 914 static void musicpal_misc_init(void)
 915 {
 916     int iomemtype;
 917
 918     iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
 919                                        musicpal_misc_writefn, NULL);
 920     cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
 921 }
 922
 923 /* WLAN register offsets */
 924 #define MP_WLAN_MAGIC1          0x11c
 925 #define MP_WLAN_MAGIC2          0x124
 926
 927 static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
 928 {
 929     switch (offset) {
 930     /* Workaround to allow loading the binary-only wlandrv.ko crap
 931      * from the original Freecom firmware. */
 932     case MP_WLAN_MAGIC1:
 933         return ~3;
 934     case MP_WLAN_MAGIC2:
 935         return -1;
 936
 937     default:
 938         return 0;
 939     }
 940 }
 941
 942 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
 943                                  uint32_t value)
 944 {
 945 }
 946
 947 static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
 948     mv88w8618_wlan_read,
 949     mv88w8618_wlan_read,
 950     mv88w8618_wlan_read,
 951 };
 952
 953 static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
 954     mv88w8618_wlan_write,
 955     mv88w8618_wlan_write,
 956     mv88w8618_wlan_write,
 957 };
 958
 959 static int mv88w8618_wlan_init(SysBusDevice *dev)
 960 {
 961     int iomemtype;
 962
 963     iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
 964                                        mv88w8618_wlan_writefn, NULL);
 965     sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
 966     return 0;
 967 }
 968
 969 /* GPIO register offsets */
 970 #define MP_GPIO_OE_LO           0x008
 971 #define MP_GPIO_OUT_LO          0x00c
 972 #define MP_GPIO_IN_LO           0x010
 973 #define MP_GPIO_IER_LO          0x014
 974 #define MP_GPIO_IMR_LO          0x018
 975 #define MP_GPIO_ISR_LO          0x020
 976 #define MP_GPIO_OE_HI           0x508
 977 #define MP_GPIO_OUT_HI          0x50c
 978 #define MP_GPIO_IN_HI           0x510
 979 #define MP_GPIO_IER_HI          0x514
 980 #define MP_GPIO_IMR_HI          0x518
 981 #define MP_GPIO_ISR_HI          0x520
 982
 983 /* GPIO bits & masks */
 984 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
 985 #define MP_GPIO_I2C_DATA_BIT    29
 986 #define MP_GPIO_I2C_CLOCK_BIT   30
 987
 988 /* LCD brightness bits in GPIO_OE_HI */
 989 #define MP_OE_LCD_BRIGHTNESS    0x0007
 990
 991 typedef struct musicpal_gpio_state {
 992     SysBusDevice busdev;
 993     uint32_t lcd_brightness;
 994     uint32_t out_state;
 995     uint32_t in_state;
 996     uint32_t ier;
 997     uint32_t imr;
 998     uint32_t isr;
 999     qemu_irq irq;
1000     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1001 } musicpal_gpio_state;
1002
1003 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1004     int i;
1005     uint32_t brightness;
1006
1007     /* compute brightness ratio */
1008     switch (s->lcd_brightness) {
1009     case 0x00000007:
1010         brightness = 0;
1011         break;
1012
1013     case 0x00020000:
1014         brightness = 1;
1015         break;
1016
1017     case 0x00020001:
1018         brightness = 2;
1019         break;
1020
1021     case 0x00040000:
1022         brightness = 3;
1023         break;
1024
1025     case 0x00010006:
1026         brightness = 4;
1027         break;
1028
1029     case 0x00020005:
1030         brightness = 5;
1031         break;
1032
1033     case 0x00040003:
1034         brightness = 6;
1035         break;
1036
1037     case 0x00030004:
1038     default:
1039         brightness = 7;
1040     }
1041
1042     /* set lcd brightness GPIOs  */
1043     for (i = 0; i <= 2; i++) {
1044         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1045     }
1046 }
1047
1048 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1049 {
1050     musicpal_gpio_state *s = opaque;
1051     uint32_t mask = 1 << pin;
1052     uint32_t delta = level << pin;
1053     uint32_t old = s->in_state & mask;
1054
1055     s->in_state &= ~mask;
1056     s->in_state |= delta;
1057
1058     if ((old ^ delta) &&
1059         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1060         s->isr = mask;
1061         qemu_irq_raise(s->irq);
1062     }
1063 }
1064
1065 static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
1066 {
1067     musicpal_gpio_state *s = opaque;
1068
1069     switch (offset) {
1070     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1071         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1072
1073     case MP_GPIO_OUT_LO:
1074         return s->out_state & 0xFFFF;
1075     case MP_GPIO_OUT_HI:
1076         return s->out_state >> 16;
1077
1078     case MP_GPIO_IN_LO:
1079         return s->in_state & 0xFFFF;
1080     case MP_GPIO_IN_HI:
1081         return s->in_state >> 16;
1082
1083     case MP_GPIO_IER_LO:
1084         return s->ier & 0xFFFF;
1085     case MP_GPIO_IER_HI:
1086         return s->ier >> 16;
1087
1088     case MP_GPIO_IMR_LO:
1089         return s->imr & 0xFFFF;
1090     case MP_GPIO_IMR_HI:
1091         return s->imr >> 16;
1092
1093     case MP_GPIO_ISR_LO:
1094         return s->isr & 0xFFFF;
1095     case MP_GPIO_ISR_HI:
1096         return s->isr >> 16;
1097
1098     default:
1099         return 0;
1100     }
1101 }
1102
1103 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1104                                 uint32_t value)
1105 {
1106     musicpal_gpio_state *s = opaque;
1107     switch (offset) {
1108     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1109         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1110                          (value & MP_OE_LCD_BRIGHTNESS);
1111         musicpal_gpio_brightness_update(s);
1112         break;
1113
1114     case MP_GPIO_OUT_LO:
1115         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1116         break;
1117     case MP_GPIO_OUT_HI:
1118         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1119         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1120                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1121         musicpal_gpio_brightness_update(s);
1122         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1123         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1124         break;
1125
1126     case MP_GPIO_IER_LO:
1127         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1128         break;
1129     case MP_GPIO_IER_HI:
1130         s->ier = (s->ier & 0xFFFF) | (value << 16);
1131         break;
1132
1133     case MP_GPIO_IMR_LO:
1134         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1135         break;
1136     case MP_GPIO_IMR_HI:
1137         s->imr = (s->imr & 0xFFFF) | (value << 16);
1138         break;
1139     }
1140 }
1141
1142 static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
1143     musicpal_gpio_read,
1144     musicpal_gpio_read,
1145     musicpal_gpio_read,
1146 };
1147
1148 static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
1149     musicpal_gpio_write,
1150     musicpal_gpio_write,
1151     musicpal_gpio_write,
1152 };
1153
1154 static void musicpal_gpio_reset(void *opaque)
1155 {
1156     musicpal_gpio_state *s = opaque;
1157
1158     s->lcd_brightness = 0;
1159     s->out_state = 0;
1160     s->in_state = 0xffffffff;
1161     s->ier = 0;
1162     s->imr = 0;
1163     s->isr = 0;
1164 }
1165
1166 static int musicpal_gpio_init(SysBusDevice *dev)
1167 {
1168     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1169     int iomemtype;
1170
1171     sysbus_init_irq(dev, &s->irq);
1172
1173     iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
1174                                        musicpal_gpio_writefn, s);
1175     sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
1176
1177     qemu_register_reset(musicpal_gpio_reset, s);
1178     musicpal_gpio_reset(s);
1179
1180     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1181
1182     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1183
1184     return 0;
1185 }
1186
1187 static SysBusDeviceInfo musicpal_gpio_info = {
1188     .init = musicpal_gpio_init,
1189     .qdev.name  = "musicpal_gpio",
1190     .qdev.size  = sizeof(musicpal_gpio_state),
1191     .qdev.reset = musicpal_gpio_reset,
1192 };
1193
1194 /* Keyboard codes & masks */
1195 #define KEY_RELEASED            0x80
1196 #define KEY_CODE                0x7f
1197
1198 #define KEYCODE_TAB             0x0f
1199 #define KEYCODE_ENTER           0x1c
1200 #define KEYCODE_F               0x21
1201 #define KEYCODE_M               0x32
1202
1203 #define KEYCODE_EXTENDED        0xe0
1204 #define KEYCODE_UP              0x48
1205 #define KEYCODE_DOWN            0x50
1206 #define KEYCODE_LEFT            0x4b
1207 #define KEYCODE_RIGHT           0x4d
1208
1209 #define MP_KEY_WHEEL_VOL       (1 << 0)
1210 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1211 #define MP_KEY_WHEEL_NAV       (1 << 2)
1212 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1213 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1214 #define MP_KEY_BTN_MENU        (1 << 5)
1215 #define MP_KEY_BTN_VOLUME      (1 << 6)
1216 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1217
1218 typedef struct musicpal_key_state {
1219     SysBusDevice busdev;
1220     uint32_t kbd_extended;
1221     uint32_t pressed_keys;
1222     qemu_irq out[8];
1223 } musicpal_key_state;
1224
1225 static void musicpal_key_event(void *opaque, int keycode)
1226 {
1227     musicpal_key_state *s = opaque;
1228     uint32_t event = 0;
1229     int i;
1230
1231     if (keycode == KEYCODE_EXTENDED) {
1232         s->kbd_extended = 1;
1233         return;
1234     }
1235
1236     if (s->kbd_extended) {
1237         switch (keycode & KEY_CODE) {
1238         case KEYCODE_UP:
1239             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1240             break;
1241
1242         case KEYCODE_DOWN:
1243             event = MP_KEY_WHEEL_NAV;
1244             break;
1245
1246         case KEYCODE_LEFT:
1247             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1248             break;
1249
1250         case KEYCODE_RIGHT:
1251             event = MP_KEY_WHEEL_VOL;
1252             break;
1253         }
1254     } else {
1255         switch (keycode & KEY_CODE) {
1256         case KEYCODE_F:
1257             event = MP_KEY_BTN_FAVORITS;
1258             break;
1259
1260         case KEYCODE_TAB:
1261             event = MP_KEY_BTN_VOLUME;
1262             break;
1263
1264         case KEYCODE_ENTER:
1265             event = MP_KEY_BTN_NAVIGATION;
1266             break;
1267
1268         case KEYCODE_M:
1269             event = MP_KEY_BTN_MENU;
1270             break;
1271         }
1272         /* Do not repeat already pressed buttons */
1273         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1274             event = 0;
1275         }
1276     }
1277
1278     if (event) {
1279         /* Raise GPIO pin first if repeating a key */
1280         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1281             for (i = 0; i <= 7; i++) {
1282                 if (event & (1 << i)) {
1283                     qemu_set_irq(s->out[i], 1);
1284                 }
1285             }
1286         }
1287         for (i = 0; i <= 7; i++) {
1288             if (event & (1 << i)) {
1289                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1290             }
1291         }
1292         if (keycode & KEY_RELEASED) {
1293             s->pressed_keys &= ~event;
1294         } else {
1295             s->pressed_keys |= event;
1296         }
1297     }
1298
1299     s->kbd_extended = 0;
1300 }
1301
1302 static int musicpal_key_init(SysBusDevice *dev)
1303 {
1304     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1305
1306     sysbus_init_mmio(dev, 0x0, 0);
1307
1308     s->kbd_extended = 0;
1309     s->pressed_keys = 0;
1310
1311     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1312
1313     qemu_add_kbd_event_handler(musicpal_key_event, s);
1314
1315     return 0;
1316 }
1317
1318 static struct arm_boot_info musicpal_binfo = {
1319     .loader_start = 0x0,
1320     .board_id = 0x20e,
1321 };
1322
1323 static void musicpal_init(ram_addr_t ram_size,
1324                const char *boot_device,
1325                const char *kernel_filename, const char *kernel_cmdline,
1326                const char *initrd_filename, const char *cpu_model)
1327 {
1328     CPUState *env;
1329     qemu_irq *cpu_pic;
1330     qemu_irq pic[32];
1331     DeviceState *dev;
1332     DeviceState *i2c_dev;
1333     DeviceState *lcd_dev;
1334     DeviceState *key_dev;
1335 #ifdef HAS_AUDIO
1336     DeviceState *wm8750_dev;
1337     SysBusDevice *s;
1338 #endif
1339     i2c_bus *i2c;
1340     int i;
1341     unsigned long flash_size;
1342     DriveInfo *dinfo;
1343     ram_addr_t sram_off;
1344
1345     if (!cpu_model) {
1346         cpu_model = "arm926";
1347     }
1348     env = cpu_init(cpu_model);
1349     if (!env) {
1350         fprintf(stderr, "Unable to find CPU definition\n");
1351         exit(1);
1352     }
1353     cpu_pic = arm_pic_init_cpu(env);
1354
1355     /* For now we use a fixed - the original - RAM size */
1356     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1357                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1358
1359     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1360     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1361
1362     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1363                                cpu_pic[ARM_PIC_CPU_IRQ]);
1364     for (i = 0; i < 32; i++) {
1365         pic[i] = qdev_get_gpio_in(dev, i);
1366     }
1367     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1368                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1369                           pic[MP_TIMER4_IRQ], NULL);
1370
1371     if (serial_hds[0]) {
1372         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1373                    serial_hds[0], 1);
1374     }
1375     if (serial_hds[1]) {
1376         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1377                    serial_hds[1], 1);
1378     }
1379
1380     /* Register flash */
1381     dinfo = drive_get(IF_PFLASH, 0, 0);
1382     if (dinfo) {
1383         flash_size = bdrv_getlength(dinfo->bdrv);
1384         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1385             flash_size != 32*1024*1024) {
1386             fprintf(stderr, "Invalid flash image size\n");
1387             exit(1);
1388         }
1389
1390         /*
1391          * The original U-Boot accesses the flash at 0xFE000000 instead of
1392          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1393          * image is smaller than 32 MB.
1394          */
1395         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1396                               dinfo->bdrv, 0x10000,
1397                               (flash_size + 0xffff) >> 16,
1398                               MP_FLASH_SIZE_MAX / flash_size,
1399                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1400                               0x5555, 0x2AAA);
1401     }
1402     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1403
1404     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1405     dev = qdev_create(NULL, "mv88w8618_eth");
1406     dev->nd = &nd_table[0];
1407     qdev_init(dev);
1408     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1409     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1410
1411     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1412
1413     musicpal_misc_init();
1414
1415     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1416     i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL);
1417     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1418
1419     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1420     key_dev = sysbus_create_simple("musicpal_key", 0, NULL);
1421
1422     /* I2C read data */
1423     qdev_connect_gpio_out(i2c_dev, 0,
1424                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1425     /* I2C data */
1426     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1427     /* I2C clock */
1428     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1429
1430     for (i = 0; i < 3; i++) {
1431         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1432     }
1433     for (i = 0; i < 4; i++) {
1434         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1435     }
1436     for (i = 4; i < 8; i++) {
1437         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1438     }
1439
1440 #ifdef HAS_AUDIO
1441     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1442     dev = qdev_create(NULL, "mv88w8618_audio");
1443     s = sysbus_from_qdev(dev);
1444     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1445     qdev_init(dev);
1446     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1447     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1448 #endif
1449
1450     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1451     musicpal_binfo.kernel_filename = kernel_filename;
1452     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1453     musicpal_binfo.initrd_filename = initrd_filename;
1454     arm_load_kernel(env, &musicpal_binfo);
1455 }
1456
1457 static QEMUMachine musicpal_machine = {
1458     .name = "musicpal",
1459     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1460     .init = musicpal_init,
1461 };
1462
1463 static void musicpal_machine_init(void)
1464 {
1465     qemu_register_machine(&musicpal_machine);
1466 }
1467
1468 machine_init(musicpal_machine_init);
1469
1470 static void musicpal_register_devices(void)
1471 {
1472     sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state),
1473                         mv88w8618_pic_init);
1474     sysbus_register_withprop(&mv88w8618_pit_info);
1475     sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state),
1476                         mv88w8618_flashcfg_init);
1477     sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state),
1478                         mv88w8618_eth_init);
1479     sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1480                         mv88w8618_wlan_init);
1481     sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state),
1482                         musicpal_lcd_init);
1483     sysbus_register_withprop(&musicpal_gpio_info);
1484     sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state),
1485                         musicpal_key_init);
1486 }
1487
1488 device_init(musicpal_register_devices)