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[qemu.git] / hw / ne2000.c
1 /*
2 * QEMU NE2000 emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25
26 /* debug NE2000 card */
27 //#define DEBUG_NE2000
28
29 #define MAX_ETH_FRAME_SIZE 1514
30
31 #define E8390_CMD 0x00 /* The command register (for all pages) */
32 /* Page 0 register offsets. */
33 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
34 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
35 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
36 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
37 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
38 #define EN0_TSR 0x04 /* Transmit status reg RD */
39 #define EN0_TPSR 0x04 /* Transmit starting page WR */
40 #define EN0_NCR 0x05 /* Number of collision reg RD */
41 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
42 #define EN0_FIFO 0x06 /* FIFO RD */
43 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
44 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
45 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
46 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
47 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
48 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
49 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
50 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
51 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
52 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
53 #define EN0_RSR 0x0c /* rx status reg RD */
54 #define EN0_RXCR 0x0c /* RX configuration reg WR */
55 #define EN0_TXCR 0x0d /* TX configuration reg WR */
56 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
57 #define EN0_DCFG 0x0e /* Data configuration reg WR */
58 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
59 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
60 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
61
62 #define EN1_PHYS 0x11
63 #define EN1_CURPAG 0x17
64 #define EN1_MULT 0x18
65
66 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
67 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
68
69 #define EN3_CONFIG0 0x33
70 #define EN3_CONFIG1 0x34
71 #define EN3_CONFIG2 0x35
72 #define EN3_CONFIG3 0x36
73
74 /* Register accessed at EN_CMD, the 8390 base addr. */
75 #define E8390_STOP 0x01 /* Stop and reset the chip */
76 #define E8390_START 0x02 /* Start the chip, clear reset */
77 #define E8390_TRANS 0x04 /* Transmit a frame */
78 #define E8390_RREAD 0x08 /* Remote read */
79 #define E8390_RWRITE 0x10 /* Remote write */
80 #define E8390_NODMA 0x20 /* Remote DMA */
81 #define E8390_PAGE0 0x00 /* Select page chip registers */
82 #define E8390_PAGE1 0x40 /* using the two high-order bits */
83 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
84
85 /* Bits in EN0_ISR - Interrupt status register */
86 #define ENISR_RX 0x01 /* Receiver, no error */
87 #define ENISR_TX 0x02 /* Transmitter, no error */
88 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
89 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
90 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
91 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
92 #define ENISR_RDC 0x40 /* remote dma complete */
93 #define ENISR_RESET 0x80 /* Reset completed */
94 #define ENISR_ALL 0x3f /* Interrupts we will enable */
95
96 /* Bits in received packet status byte and EN0_RSR*/
97 #define ENRSR_RXOK 0x01 /* Received a good packet */
98 #define ENRSR_CRC 0x02 /* CRC error */
99 #define ENRSR_FAE 0x04 /* frame alignment error */
100 #define ENRSR_FO 0x08 /* FIFO overrun */
101 #define ENRSR_MPA 0x10 /* missed pkt */
102 #define ENRSR_PHY 0x20 /* physical/multicast address */
103 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
104 #define ENRSR_DEF 0x80 /* deferring */
105
106 /* Transmitted packet status, EN0_TSR. */
107 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
108 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
109 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
110 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
111 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
112 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
113 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
114 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
115
116 #define NE2000_PMEM_SIZE (32*1024)
117 #define NE2000_PMEM_START (16*1024)
118 #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
119 #define NE2000_MEM_SIZE NE2000_PMEM_END
120
121 typedef struct NE2000State {
122 uint8_t cmd;
123 uint32_t start;
124 uint32_t stop;
125 uint8_t boundary;
126 uint8_t tsr;
127 uint8_t tpsr;
128 uint16_t tcnt;
129 uint16_t rcnt;
130 uint32_t rsar;
131 uint8_t rsr;
132 uint8_t rxcr;
133 uint8_t isr;
134 uint8_t dcfg;
135 uint8_t imr;
136 uint8_t phys[6]; /* mac address */
137 uint8_t curpag;
138 uint8_t mult[8]; /* multicast mask array */
139 qemu_irq irq;
140 PCIDevice *pci_dev;
141 VLANClientState *vc;
142 uint8_t macaddr[6];
143 uint8_t mem[NE2000_MEM_SIZE];
144 } NE2000State;
145
146 static void ne2000_reset(NE2000State *s)
147 {
148 int i;
149
150 s->isr = ENISR_RESET;
151 memcpy(s->mem, s->macaddr, 6);
152 s->mem[14] = 0x57;
153 s->mem[15] = 0x57;
154
155 /* duplicate prom data */
156 for(i = 15;i >= 0; i--) {
157 s->mem[2 * i] = s->mem[i];
158 s->mem[2 * i + 1] = s->mem[i];
159 }
160 }
161
162 static void ne2000_update_irq(NE2000State *s)
163 {
164 int isr;
165 isr = (s->isr & s->imr) & 0x7f;
166 #if defined(DEBUG_NE2000)
167 printf("NE2000: Set IRQ to %d (%02x %02x)\n",
168 isr ? 1 : 0, s->isr, s->imr);
169 #endif
170 qemu_set_irq(s->irq, (isr != 0));
171 }
172
173 #define POLYNOMIAL 0x04c11db6
174
175 /* From FreeBSD */
176 /* XXX: optimize */
177 static int compute_mcast_idx(const uint8_t *ep)
178 {
179 uint32_t crc;
180 int carry, i, j;
181 uint8_t b;
182
183 crc = 0xffffffff;
184 for (i = 0; i < 6; i++) {
185 b = *ep++;
186 for (j = 0; j < 8; j++) {
187 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
188 crc <<= 1;
189 b >>= 1;
190 if (carry)
191 crc = ((crc ^ POLYNOMIAL) | carry);
192 }
193 }
194 return (crc >> 26);
195 }
196
197 static int ne2000_buffer_full(NE2000State *s)
198 {
199 int avail, index, boundary;
200
201 index = s->curpag << 8;
202 boundary = s->boundary << 8;
203 if (index < boundary)
204 avail = boundary - index;
205 else
206 avail = (s->stop - s->start) - (index - boundary);
207 if (avail < (MAX_ETH_FRAME_SIZE + 4))
208 return 1;
209 return 0;
210 }
211
212 static int ne2000_can_receive(void *opaque)
213 {
214 NE2000State *s = opaque;
215
216 if (s->cmd & E8390_STOP)
217 return 1;
218 return !ne2000_buffer_full(s);
219 }
220
221 #define MIN_BUF_SIZE 60
222
223 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
224 {
225 NE2000State *s = opaque;
226 uint8_t *p;
227 int total_len, next, avail, len, index, mcast_idx;
228 uint8_t buf1[60];
229 static const uint8_t broadcast_macaddr[6] =
230 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
231
232 #if defined(DEBUG_NE2000)
233 printf("NE2000: received len=%d\n", size);
234 #endif
235
236 if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
237 return;
238
239 /* XXX: check this */
240 if (s->rxcr & 0x10) {
241 /* promiscuous: receive all */
242 } else {
243 if (!memcmp(buf, broadcast_macaddr, 6)) {
244 /* broadcast address */
245 if (!(s->rxcr & 0x04))
246 return;
247 } else if (buf[0] & 0x01) {
248 /* multicast */
249 if (!(s->rxcr & 0x08))
250 return;
251 mcast_idx = compute_mcast_idx(buf);
252 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
253 return;
254 } else if (s->mem[0] == buf[0] &&
255 s->mem[2] == buf[1] &&
256 s->mem[4] == buf[2] &&
257 s->mem[6] == buf[3] &&
258 s->mem[8] == buf[4] &&
259 s->mem[10] == buf[5]) {
260 /* match */
261 } else {
262 return;
263 }
264 }
265
266
267 /* if too small buffer, then expand it */
268 if (size < MIN_BUF_SIZE) {
269 memcpy(buf1, buf, size);
270 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
271 buf = buf1;
272 size = MIN_BUF_SIZE;
273 }
274
275 index = s->curpag << 8;
276 /* 4 bytes for header */
277 total_len = size + 4;
278 /* address for next packet (4 bytes for CRC) */
279 next = index + ((total_len + 4 + 255) & ~0xff);
280 if (next >= s->stop)
281 next -= (s->stop - s->start);
282 /* prepare packet header */
283 p = s->mem + index;
284 s->rsr = ENRSR_RXOK; /* receive status */
285 /* XXX: check this */
286 if (buf[0] & 0x01)
287 s->rsr |= ENRSR_PHY;
288 p[0] = s->rsr;
289 p[1] = next >> 8;
290 p[2] = total_len;
291 p[3] = total_len >> 8;
292 index += 4;
293
294 /* write packet data */
295 while (size > 0) {
296 avail = s->stop - index;
297 len = size;
298 if (len > avail)
299 len = avail;
300 memcpy(s->mem + index, buf, len);
301 buf += len;
302 index += len;
303 if (index == s->stop)
304 index = s->start;
305 size -= len;
306 }
307 s->curpag = next >> 8;
308
309 /* now we can signal we have received something */
310 s->isr |= ENISR_RX;
311 ne2000_update_irq(s);
312 }
313
314 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
315 {
316 NE2000State *s = opaque;
317 int offset, page, index;
318
319 addr &= 0xf;
320 #ifdef DEBUG_NE2000
321 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
322 #endif
323 if (addr == E8390_CMD) {
324 /* control register */
325 s->cmd = val;
326 if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
327 s->isr &= ~ENISR_RESET;
328 /* test specific case: zero length transfer */
329 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
330 s->rcnt == 0) {
331 s->isr |= ENISR_RDC;
332 ne2000_update_irq(s);
333 }
334 if (val & E8390_TRANS) {
335 index = (s->tpsr << 8);
336 /* XXX: next 2 lines are a hack to make netware 3.11 work */
337 if (index >= NE2000_PMEM_END)
338 index -= NE2000_PMEM_SIZE;
339 /* fail safe: check range on the transmitted length */
340 if (index + s->tcnt <= NE2000_PMEM_END) {
341 qemu_send_packet(s->vc, s->mem + index, s->tcnt);
342 }
343 /* signal end of transfer */
344 s->tsr = ENTSR_PTX;
345 s->isr |= ENISR_TX;
346 s->cmd &= ~E8390_TRANS;
347 ne2000_update_irq(s);
348 }
349 }
350 } else {
351 page = s->cmd >> 6;
352 offset = addr | (page << 4);
353 switch(offset) {
354 case EN0_STARTPG:
355 s->start = val << 8;
356 break;
357 case EN0_STOPPG:
358 s->stop = val << 8;
359 break;
360 case EN0_BOUNDARY:
361 s->boundary = val;
362 break;
363 case EN0_IMR:
364 s->imr = val;
365 ne2000_update_irq(s);
366 break;
367 case EN0_TPSR:
368 s->tpsr = val;
369 break;
370 case EN0_TCNTLO:
371 s->tcnt = (s->tcnt & 0xff00) | val;
372 break;
373 case EN0_TCNTHI:
374 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
375 break;
376 case EN0_RSARLO:
377 s->rsar = (s->rsar & 0xff00) | val;
378 break;
379 case EN0_RSARHI:
380 s->rsar = (s->rsar & 0x00ff) | (val << 8);
381 break;
382 case EN0_RCNTLO:
383 s->rcnt = (s->rcnt & 0xff00) | val;
384 break;
385 case EN0_RCNTHI:
386 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
387 break;
388 case EN0_RXCR:
389 s->rxcr = val;
390 break;
391 case EN0_DCFG:
392 s->dcfg = val;
393 break;
394 case EN0_ISR:
395 s->isr &= ~(val & 0x7f);
396 ne2000_update_irq(s);
397 break;
398 case EN1_PHYS ... EN1_PHYS + 5:
399 s->phys[offset - EN1_PHYS] = val;
400 break;
401 case EN1_CURPAG:
402 s->curpag = val;
403 break;
404 case EN1_MULT ... EN1_MULT + 7:
405 s->mult[offset - EN1_MULT] = val;
406 break;
407 }
408 }
409 }
410
411 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
412 {
413 NE2000State *s = opaque;
414 int offset, page, ret;
415
416 addr &= 0xf;
417 if (addr == E8390_CMD) {
418 ret = s->cmd;
419 } else {
420 page = s->cmd >> 6;
421 offset = addr | (page << 4);
422 switch(offset) {
423 case EN0_TSR:
424 ret = s->tsr;
425 break;
426 case EN0_BOUNDARY:
427 ret = s->boundary;
428 break;
429 case EN0_ISR:
430 ret = s->isr;
431 break;
432 case EN0_RSARLO:
433 ret = s->rsar & 0x00ff;
434 break;
435 case EN0_RSARHI:
436 ret = s->rsar >> 8;
437 break;
438 case EN1_PHYS ... EN1_PHYS + 5:
439 ret = s->phys[offset - EN1_PHYS];
440 break;
441 case EN1_CURPAG:
442 ret = s->curpag;
443 break;
444 case EN1_MULT ... EN1_MULT + 7:
445 ret = s->mult[offset - EN1_MULT];
446 break;
447 case EN0_RSR:
448 ret = s->rsr;
449 break;
450 case EN2_STARTPG:
451 ret = s->start >> 8;
452 break;
453 case EN2_STOPPG:
454 ret = s->stop >> 8;
455 break;
456 case EN0_RTL8029ID0:
457 ret = 0x50;
458 break;
459 case EN0_RTL8029ID1:
460 ret = 0x43;
461 break;
462 case EN3_CONFIG0:
463 ret = 0; /* 10baseT media */
464 break;
465 case EN3_CONFIG2:
466 ret = 0x40; /* 10baseT active */
467 break;
468 case EN3_CONFIG3:
469 ret = 0x40; /* Full duplex */
470 break;
471 default:
472 ret = 0x00;
473 break;
474 }
475 }
476 #ifdef DEBUG_NE2000
477 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
478 #endif
479 return ret;
480 }
481
482 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
483 uint32_t val)
484 {
485 if (addr < 32 ||
486 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
487 s->mem[addr] = val;
488 }
489 }
490
491 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
492 uint32_t val)
493 {
494 addr &= ~1; /* XXX: check exact behaviour if not even */
495 if (addr < 32 ||
496 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
497 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
498 }
499 }
500
501 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
502 uint32_t val)
503 {
504 addr &= ~1; /* XXX: check exact behaviour if not even */
505 if (addr < 32 ||
506 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
507 cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
508 }
509 }
510
511 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
512 {
513 if (addr < 32 ||
514 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
515 return s->mem[addr];
516 } else {
517 return 0xff;
518 }
519 }
520
521 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
522 {
523 addr &= ~1; /* XXX: check exact behaviour if not even */
524 if (addr < 32 ||
525 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
526 return le16_to_cpu(*(uint16_t *)(s->mem + addr));
527 } else {
528 return 0xffff;
529 }
530 }
531
532 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
533 {
534 addr &= ~1; /* XXX: check exact behaviour if not even */
535 if (addr < 32 ||
536 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
537 return le32_to_cpupu((uint32_t *)(s->mem + addr));
538 } else {
539 return 0xffffffff;
540 }
541 }
542
543 static inline void ne2000_dma_update(NE2000State *s, int len)
544 {
545 s->rsar += len;
546 /* wrap */
547 /* XXX: check what to do if rsar > stop */
548 if (s->rsar == s->stop)
549 s->rsar = s->start;
550
551 if (s->rcnt <= len) {
552 s->rcnt = 0;
553 /* signal end of transfer */
554 s->isr |= ENISR_RDC;
555 ne2000_update_irq(s);
556 } else {
557 s->rcnt -= len;
558 }
559 }
560
561 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
562 {
563 NE2000State *s = opaque;
564
565 #ifdef DEBUG_NE2000
566 printf("NE2000: asic write val=0x%04x\n", val);
567 #endif
568 if (s->rcnt == 0)
569 return;
570 if (s->dcfg & 0x01) {
571 /* 16 bit access */
572 ne2000_mem_writew(s, s->rsar, val);
573 ne2000_dma_update(s, 2);
574 } else {
575 /* 8 bit access */
576 ne2000_mem_writeb(s, s->rsar, val);
577 ne2000_dma_update(s, 1);
578 }
579 }
580
581 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
582 {
583 NE2000State *s = opaque;
584 int ret;
585
586 if (s->dcfg & 0x01) {
587 /* 16 bit access */
588 ret = ne2000_mem_readw(s, s->rsar);
589 ne2000_dma_update(s, 2);
590 } else {
591 /* 8 bit access */
592 ret = ne2000_mem_readb(s, s->rsar);
593 ne2000_dma_update(s, 1);
594 }
595 #ifdef DEBUG_NE2000
596 printf("NE2000: asic read val=0x%04x\n", ret);
597 #endif
598 return ret;
599 }
600
601 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
602 {
603 NE2000State *s = opaque;
604
605 #ifdef DEBUG_NE2000
606 printf("NE2000: asic writel val=0x%04x\n", val);
607 #endif
608 if (s->rcnt == 0)
609 return;
610 /* 32 bit access */
611 ne2000_mem_writel(s, s->rsar, val);
612 ne2000_dma_update(s, 4);
613 }
614
615 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
616 {
617 NE2000State *s = opaque;
618 int ret;
619
620 /* 32 bit access */
621 ret = ne2000_mem_readl(s, s->rsar);
622 ne2000_dma_update(s, 4);
623 #ifdef DEBUG_NE2000
624 printf("NE2000: asic readl val=0x%04x\n", ret);
625 #endif
626 return ret;
627 }
628
629 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
630 {
631 /* nothing to do (end of reset pulse) */
632 }
633
634 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
635 {
636 NE2000State *s = opaque;
637 ne2000_reset(s);
638 return 0;
639 }
640
641 static void ne2000_save(QEMUFile* f,void* opaque)
642 {
643 NE2000State* s=(NE2000State*)opaque;
644 int tmp;
645
646 if (s->pci_dev)
647 pci_device_save(s->pci_dev, f);
648
649 qemu_put_8s(f, &s->rxcr);
650
651 qemu_put_8s(f, &s->cmd);
652 qemu_put_be32s(f, &s->start);
653 qemu_put_be32s(f, &s->stop);
654 qemu_put_8s(f, &s->boundary);
655 qemu_put_8s(f, &s->tsr);
656 qemu_put_8s(f, &s->tpsr);
657 qemu_put_be16s(f, &s->tcnt);
658 qemu_put_be16s(f, &s->rcnt);
659 qemu_put_be32s(f, &s->rsar);
660 qemu_put_8s(f, &s->rsr);
661 qemu_put_8s(f, &s->isr);
662 qemu_put_8s(f, &s->dcfg);
663 qemu_put_8s(f, &s->imr);
664 qemu_put_buffer(f, s->phys, 6);
665 qemu_put_8s(f, &s->curpag);
666 qemu_put_buffer(f, s->mult, 8);
667 tmp = 0;
668 qemu_put_be32s(f, &tmp); /* ignored, was irq */
669 qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
670 }
671
672 static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
673 {
674 NE2000State* s=(NE2000State*)opaque;
675 int ret;
676 int tmp;
677
678 if (version_id > 3)
679 return -EINVAL;
680
681 if (s->pci_dev && version_id >= 3) {
682 ret = pci_device_load(s->pci_dev, f);
683 if (ret < 0)
684 return ret;
685 }
686
687 if (version_id >= 2) {
688 qemu_get_8s(f, &s->rxcr);
689 } else {
690 s->rxcr = 0x0c;
691 }
692
693 qemu_get_8s(f, &s->cmd);
694 qemu_get_be32s(f, &s->start);
695 qemu_get_be32s(f, &s->stop);
696 qemu_get_8s(f, &s->boundary);
697 qemu_get_8s(f, &s->tsr);
698 qemu_get_8s(f, &s->tpsr);
699 qemu_get_be16s(f, &s->tcnt);
700 qemu_get_be16s(f, &s->rcnt);
701 qemu_get_be32s(f, &s->rsar);
702 qemu_get_8s(f, &s->rsr);
703 qemu_get_8s(f, &s->isr);
704 qemu_get_8s(f, &s->dcfg);
705 qemu_get_8s(f, &s->imr);
706 qemu_get_buffer(f, s->phys, 6);
707 qemu_get_8s(f, &s->curpag);
708 qemu_get_buffer(f, s->mult, 8);
709 qemu_get_be32s(f, &tmp); /* ignored */
710 qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
711
712 return 0;
713 }
714
715 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
716 {
717 NE2000State *s;
718
719 s = qemu_mallocz(sizeof(NE2000State));
720 if (!s)
721 return;
722
723 register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
724 register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
725
726 register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
727 register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
728 register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
729 register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
730
731 register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
732 register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
733 s->irq = irq;
734 memcpy(s->macaddr, nd->macaddr, 6);
735
736 ne2000_reset(s);
737
738 s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive,
739 ne2000_can_receive, s);
740
741 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
742 "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
743 s->macaddr[0],
744 s->macaddr[1],
745 s->macaddr[2],
746 s->macaddr[3],
747 s->macaddr[4],
748 s->macaddr[5]);
749
750 register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
751 }
752
753 /***********************************************************/
754 /* PCI NE2000 definitions */
755
756 typedef struct PCINE2000State {
757 PCIDevice dev;
758 NE2000State ne2000;
759 } PCINE2000State;
760
761 static void ne2000_map(PCIDevice *pci_dev, int region_num,
762 uint32_t addr, uint32_t size, int type)
763 {
764 PCINE2000State *d = (PCINE2000State *)pci_dev;
765 NE2000State *s = &d->ne2000;
766
767 register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
768 register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
769
770 register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
771 register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
772 register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
773 register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
774 register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
775 register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
776
777 register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
778 register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
779 }
780
781 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
782 {
783 PCINE2000State *d;
784 NE2000State *s;
785 uint8_t *pci_conf;
786
787 d = (PCINE2000State *)pci_register_device(bus,
788 "NE2000", sizeof(PCINE2000State),
789 devfn,
790 NULL, NULL);
791 pci_conf = d->dev.config;
792 pci_conf[0x00] = 0xec; // Realtek 8029
793 pci_conf[0x01] = 0x10;
794 pci_conf[0x02] = 0x29;
795 pci_conf[0x03] = 0x80;
796 pci_conf[0x0a] = 0x00; // ethernet network controller
797 pci_conf[0x0b] = 0x02;
798 pci_conf[0x0e] = 0x00; // header_type
799 pci_conf[0x3d] = 1; // interrupt pin 0
800
801 pci_register_io_region(&d->dev, 0, 0x100,
802 PCI_ADDRESS_SPACE_IO, ne2000_map);
803 s = &d->ne2000;
804 s->irq = d->dev.irq[0];
805 s->pci_dev = (PCIDevice *)d;
806 memcpy(s->macaddr, nd->macaddr, 6);
807 ne2000_reset(s);
808 s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive,
809 ne2000_can_receive, s);
810
811 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
812 "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
813 s->macaddr[0],
814 s->macaddr[1],
815 s->macaddr[2],
816 s->macaddr[3],
817 s->macaddr[4],
818 s->macaddr[5]);
819
820 /* XXX: instance number ? */
821 register_savevm("ne2000", 0, 3, ne2000_save, ne2000_load, s);
822 }
Qemu copy for testing