2 * QEMU NE2000 emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* debug NE2000 card */
27 //#define DEBUG_NE2000
29 #define MAX_ETH_FRAME_SIZE 1514
31 #define E8390_CMD 0x00 /* The command register (for all pages) */
32 /* Page 0 register offsets. */
33 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
34 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
35 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
36 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
37 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
38 #define EN0_TSR 0x04 /* Transmit status reg RD */
39 #define EN0_TPSR 0x04 /* Transmit starting page WR */
40 #define EN0_NCR 0x05 /* Number of collision reg RD */
41 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
42 #define EN0_FIFO 0x06 /* FIFO RD */
43 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
44 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
45 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
46 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
47 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
48 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
49 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
50 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
51 #define EN0_RSR 0x0c /* rx status reg RD */
52 #define EN0_RXCR 0x0c /* RX configuration reg WR */
53 #define EN0_TXCR 0x0d /* TX configuration reg WR */
54 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
55 #define EN0_DCFG 0x0e /* Data configuration reg WR */
56 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
57 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
58 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
61 #define EN1_CURPAG 0x17
64 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
65 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
67 /* Register accessed at EN_CMD, the 8390 base addr. */
68 #define E8390_STOP 0x01 /* Stop and reset the chip */
69 #define E8390_START 0x02 /* Start the chip, clear reset */
70 #define E8390_TRANS 0x04 /* Transmit a frame */
71 #define E8390_RREAD 0x08 /* Remote read */
72 #define E8390_RWRITE 0x10 /* Remote write */
73 #define E8390_NODMA 0x20 /* Remote DMA */
74 #define E8390_PAGE0 0x00 /* Select page chip registers */
75 #define E8390_PAGE1 0x40 /* using the two high-order bits */
76 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
78 /* Bits in EN0_ISR - Interrupt status register */
79 #define ENISR_RX 0x01 /* Receiver, no error */
80 #define ENISR_TX 0x02 /* Transmitter, no error */
81 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
82 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
83 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
84 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
85 #define ENISR_RDC 0x40 /* remote dma complete */
86 #define ENISR_RESET 0x80 /* Reset completed */
87 #define ENISR_ALL 0x3f /* Interrupts we will enable */
89 /* Bits in received packet status byte and EN0_RSR*/
90 #define ENRSR_RXOK 0x01 /* Received a good packet */
91 #define ENRSR_CRC 0x02 /* CRC error */
92 #define ENRSR_FAE 0x04 /* frame alignment error */
93 #define ENRSR_FO 0x08 /* FIFO overrun */
94 #define ENRSR_MPA 0x10 /* missed pkt */
95 #define ENRSR_PHY 0x20 /* physical/multicast address */
96 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
97 #define ENRSR_DEF 0x80 /* deferring */
99 /* Transmitted packet status, EN0_TSR. */
100 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
101 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
102 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
103 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
104 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
105 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
106 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
107 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
109 #define NE2000_PMEM_SIZE (32*1024)
110 #define NE2000_PMEM_START (16*1024)
111 #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
112 #define NE2000_MEM_SIZE NE2000_PMEM_END
114 typedef struct NE2000State
{
129 uint8_t phys
[6]; /* mac address */
131 uint8_t mult
[8]; /* multicast mask array */
136 uint8_t mem
[NE2000_MEM_SIZE
];
139 static void ne2000_reset(NE2000State
*s
)
143 s
->isr
= ENISR_RESET
;
144 memcpy(s
->mem
, s
->macaddr
, 6);
148 /* duplicate prom data */
149 for(i
= 15;i
>= 0; i
--) {
150 s
->mem
[2 * i
] = s
->mem
[i
];
151 s
->mem
[2 * i
+ 1] = s
->mem
[i
];
155 static void ne2000_update_irq(NE2000State
*s
)
158 isr
= (s
->isr
& s
->imr
) & 0x7f;
159 #if defined(DEBUG_NE2000)
160 printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
161 s
->irq
, isr
? 1 : 0, s
->isr
, s
->imr
);
165 pci_set_irq(s
->pci_dev
, 0, (isr
!= 0));
168 pic_set_irq(s
->irq
, (isr
!= 0));
172 #define POLYNOMIAL 0x04c11db6
176 static int compute_mcast_idx(const uint8_t *ep
)
183 for (i
= 0; i
< 6; i
++) {
185 for (j
= 0; j
< 8; j
++) {
186 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
190 crc
= ((crc
^ POLYNOMIAL
) | carry
);
196 /* return the max buffer size if the NE2000 can receive more data */
197 static int ne2000_can_receive(void *opaque
)
199 NE2000State
*s
= opaque
;
200 int avail
, index
, boundary
;
202 if (s
->cmd
& E8390_STOP
)
204 index
= s
->curpag
<< 8;
205 boundary
= s
->boundary
<< 8;
206 if (index
< boundary
)
207 avail
= boundary
- index
;
209 avail
= (s
->stop
- s
->start
) - (index
- boundary
);
210 if (avail
< (MAX_ETH_FRAME_SIZE
+ 4))
212 return MAX_ETH_FRAME_SIZE
;
215 #define MIN_BUF_SIZE 60
217 static void ne2000_receive(void *opaque
, const uint8_t *buf
, int size
)
219 NE2000State
*s
= opaque
;
221 int total_len
, next
, avail
, len
, index
, mcast_idx
;
223 static const uint8_t broadcast_macaddr
[6] =
224 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
226 #if defined(DEBUG_NE2000)
227 printf("NE2000: received len=%d\n", size
);
230 if (!ne2000_can_receive(s
))
233 /* XXX: check this */
234 if (s
->rxcr
& 0x10) {
235 /* promiscuous: receive all */
237 if (!memcmp(buf
, broadcast_macaddr
, 6)) {
238 /* broadcast address */
239 if (!(s
->rxcr
& 0x04))
241 } else if (buf
[0] & 0x01) {
243 if (!(s
->rxcr
& 0x08))
245 mcast_idx
= compute_mcast_idx(buf
);
246 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7))))
248 } else if (s
->mem
[0] == buf
[0] &&
249 s
->mem
[2] == buf
[1] &&
250 s
->mem
[4] == buf
[2] &&
251 s
->mem
[6] == buf
[3] &&
252 s
->mem
[8] == buf
[4] &&
253 s
->mem
[10] == buf
[5]) {
261 /* if too small buffer, then expand it */
262 if (size
< MIN_BUF_SIZE
) {
263 memcpy(buf1
, buf
, size
);
264 memset(buf1
+ size
, 0, MIN_BUF_SIZE
- size
);
269 index
= s
->curpag
<< 8;
270 /* 4 bytes for header */
271 total_len
= size
+ 4;
272 /* address for next packet (4 bytes for CRC) */
273 next
= index
+ ((total_len
+ 4 + 255) & ~0xff);
275 next
-= (s
->stop
- s
->start
);
276 /* prepare packet header */
278 s
->rsr
= ENRSR_RXOK
; /* receive status */
279 /* XXX: check this */
285 p
[3] = total_len
>> 8;
288 /* write packet data */
290 avail
= s
->stop
- index
;
294 memcpy(s
->mem
+ index
, buf
, len
);
297 if (index
== s
->stop
)
301 s
->curpag
= next
>> 8;
303 /* now we can signal we have receive something */
305 ne2000_update_irq(s
);
308 static void ne2000_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
310 NE2000State
*s
= opaque
;
311 int offset
, page
, index
;
315 printf("NE2000: write addr=0x%x val=0x%02x\n", addr
, val
);
317 if (addr
== E8390_CMD
) {
318 /* control register */
320 if (!(val
& E8390_STOP
)) { /* START bit makes no sense on RTL8029... */
321 s
->isr
&= ~ENISR_RESET
;
322 /* test specific case: zero length transfert */
323 if ((val
& (E8390_RREAD
| E8390_RWRITE
)) &&
326 ne2000_update_irq(s
);
328 if (val
& E8390_TRANS
) {
329 index
= (s
->tpsr
<< 8);
330 /* XXX: next 2 lines are a hack to make netware 3.11 work */
331 if (index
>= NE2000_PMEM_END
)
332 index
-= NE2000_PMEM_SIZE
;
333 /* fail safe: check range on the transmitted length */
334 if (index
+ s
->tcnt
<= NE2000_PMEM_END
) {
335 qemu_send_packet(s
->vc
, s
->mem
+ index
, s
->tcnt
);
337 /* signal end of transfert */
340 s
->cmd
&= ~E8390_TRANS
;
341 ne2000_update_irq(s
);
346 offset
= addr
| (page
<< 4);
359 ne2000_update_irq(s
);
365 s
->tcnt
= (s
->tcnt
& 0xff00) | val
;
368 s
->tcnt
= (s
->tcnt
& 0x00ff) | (val
<< 8);
371 s
->rsar
= (s
->rsar
& 0xff00) | val
;
374 s
->rsar
= (s
->rsar
& 0x00ff) | (val
<< 8);
377 s
->rcnt
= (s
->rcnt
& 0xff00) | val
;
380 s
->rcnt
= (s
->rcnt
& 0x00ff) | (val
<< 8);
389 s
->isr
&= ~(val
& 0x7f);
390 ne2000_update_irq(s
);
392 case EN1_PHYS
... EN1_PHYS
+ 5:
393 s
->phys
[offset
- EN1_PHYS
] = val
;
398 case EN1_MULT
... EN1_MULT
+ 7:
399 s
->mult
[offset
- EN1_MULT
] = val
;
405 static uint32_t ne2000_ioport_read(void *opaque
, uint32_t addr
)
407 NE2000State
*s
= opaque
;
408 int offset
, page
, ret
;
411 if (addr
== E8390_CMD
) {
415 offset
= addr
| (page
<< 4);
427 ret
= s
->rsar
& 0x00ff;
432 case EN1_PHYS
... EN1_PHYS
+ 5:
433 ret
= s
->phys
[offset
- EN1_PHYS
];
438 case EN1_MULT
... EN1_MULT
+ 7:
439 ret
= s
->mult
[offset
- EN1_MULT
];
456 printf("NE2000: read addr=0x%x val=%02x\n", addr
, ret
);
461 static inline void ne2000_mem_writeb(NE2000State
*s
, uint32_t addr
,
465 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
470 static inline void ne2000_mem_writew(NE2000State
*s
, uint32_t addr
,
473 addr
&= ~1; /* XXX: check exact behaviour if not even */
475 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
476 *(uint16_t *)(s
->mem
+ addr
) = cpu_to_le16(val
);
480 static inline void ne2000_mem_writel(NE2000State
*s
, uint32_t addr
,
483 addr
&= ~1; /* XXX: check exact behaviour if not even */
485 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
486 cpu_to_le32wu((uint32_t *)(s
->mem
+ addr
), val
);
490 static inline uint32_t ne2000_mem_readb(NE2000State
*s
, uint32_t addr
)
493 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
500 static inline uint32_t ne2000_mem_readw(NE2000State
*s
, uint32_t addr
)
502 addr
&= ~1; /* XXX: check exact behaviour if not even */
504 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
505 return le16_to_cpu(*(uint16_t *)(s
->mem
+ addr
));
511 static inline uint32_t ne2000_mem_readl(NE2000State
*s
, uint32_t addr
)
513 addr
&= ~1; /* XXX: check exact behaviour if not even */
515 (addr
>= NE2000_PMEM_START
&& addr
< NE2000_MEM_SIZE
)) {
516 return le32_to_cpupu((uint32_t *)(s
->mem
+ addr
));
522 static inline void ne2000_dma_update(NE2000State
*s
, int len
)
526 /* XXX: check what to do if rsar > stop */
527 if (s
->rsar
== s
->stop
)
530 if (s
->rcnt
<= len
) {
532 /* signal end of transfert */
534 ne2000_update_irq(s
);
540 static void ne2000_asic_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
542 NE2000State
*s
= opaque
;
545 printf("NE2000: asic write val=0x%04x\n", val
);
549 if (s
->dcfg
& 0x01) {
551 ne2000_mem_writew(s
, s
->rsar
, val
);
552 ne2000_dma_update(s
, 2);
555 ne2000_mem_writeb(s
, s
->rsar
, val
);
556 ne2000_dma_update(s
, 1);
560 static uint32_t ne2000_asic_ioport_read(void *opaque
, uint32_t addr
)
562 NE2000State
*s
= opaque
;
565 if (s
->dcfg
& 0x01) {
567 ret
= ne2000_mem_readw(s
, s
->rsar
);
568 ne2000_dma_update(s
, 2);
571 ret
= ne2000_mem_readb(s
, s
->rsar
);
572 ne2000_dma_update(s
, 1);
575 printf("NE2000: asic read val=0x%04x\n", ret
);
580 static void ne2000_asic_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
582 NE2000State
*s
= opaque
;
585 printf("NE2000: asic writel val=0x%04x\n", val
);
590 ne2000_mem_writel(s
, s
->rsar
, val
);
591 ne2000_dma_update(s
, 4);
594 static uint32_t ne2000_asic_ioport_readl(void *opaque
, uint32_t addr
)
596 NE2000State
*s
= opaque
;
600 ret
= ne2000_mem_readl(s
, s
->rsar
);
601 ne2000_dma_update(s
, 4);
603 printf("NE2000: asic readl val=0x%04x\n", ret
);
608 static void ne2000_reset_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
610 /* nothing to do (end of reset pulse) */
613 static uint32_t ne2000_reset_ioport_read(void *opaque
, uint32_t addr
)
615 NE2000State
*s
= opaque
;
620 static void ne2000_save(QEMUFile
* f
,void* opaque
)
622 NE2000State
* s
=(NE2000State
*)opaque
;
624 qemu_put_8s(f
, &s
->cmd
);
625 qemu_put_be32s(f
, &s
->start
);
626 qemu_put_be32s(f
, &s
->stop
);
627 qemu_put_8s(f
, &s
->boundary
);
628 qemu_put_8s(f
, &s
->tsr
);
629 qemu_put_8s(f
, &s
->tpsr
);
630 qemu_put_be16s(f
, &s
->tcnt
);
631 qemu_put_be16s(f
, &s
->rcnt
);
632 qemu_put_be32s(f
, &s
->rsar
);
633 qemu_put_8s(f
, &s
->rsr
);
634 qemu_put_8s(f
, &s
->isr
);
635 qemu_put_8s(f
, &s
->dcfg
);
636 qemu_put_8s(f
, &s
->imr
);
637 qemu_put_buffer(f
, s
->phys
, 6);
638 qemu_put_8s(f
, &s
->curpag
);
639 qemu_put_buffer(f
, s
->mult
, 8);
640 qemu_put_be32s(f
, &s
->irq
);
641 qemu_put_buffer(f
, s
->mem
, NE2000_MEM_SIZE
);
644 static int ne2000_load(QEMUFile
* f
,void* opaque
,int version_id
)
646 NE2000State
* s
=(NE2000State
*)opaque
;
651 qemu_get_8s(f
, &s
->cmd
);
652 qemu_get_be32s(f
, &s
->start
);
653 qemu_get_be32s(f
, &s
->stop
);
654 qemu_get_8s(f
, &s
->boundary
);
655 qemu_get_8s(f
, &s
->tsr
);
656 qemu_get_8s(f
, &s
->tpsr
);
657 qemu_get_be16s(f
, &s
->tcnt
);
658 qemu_get_be16s(f
, &s
->rcnt
);
659 qemu_get_be32s(f
, &s
->rsar
);
660 qemu_get_8s(f
, &s
->rsr
);
661 qemu_get_8s(f
, &s
->isr
);
662 qemu_get_8s(f
, &s
->dcfg
);
663 qemu_get_8s(f
, &s
->imr
);
664 qemu_get_buffer(f
, s
->phys
, 6);
665 qemu_get_8s(f
, &s
->curpag
);
666 qemu_get_buffer(f
, s
->mult
, 8);
667 qemu_get_be32s(f
, &s
->irq
);
668 qemu_get_buffer(f
, s
->mem
, NE2000_MEM_SIZE
);
673 void isa_ne2000_init(int base
, int irq
, NICInfo
*nd
)
677 s
= qemu_mallocz(sizeof(NE2000State
));
681 register_ioport_write(base
, 16, 1, ne2000_ioport_write
, s
);
682 register_ioport_read(base
, 16, 1, ne2000_ioport_read
, s
);
684 register_ioport_write(base
+ 0x10, 1, 1, ne2000_asic_ioport_write
, s
);
685 register_ioport_read(base
+ 0x10, 1, 1, ne2000_asic_ioport_read
, s
);
686 register_ioport_write(base
+ 0x10, 2, 2, ne2000_asic_ioport_write
, s
);
687 register_ioport_read(base
+ 0x10, 2, 2, ne2000_asic_ioport_read
, s
);
689 register_ioport_write(base
+ 0x1f, 1, 1, ne2000_reset_ioport_write
, s
);
690 register_ioport_read(base
+ 0x1f, 1, 1, ne2000_reset_ioport_read
, s
);
692 memcpy(s
->macaddr
, nd
->macaddr
, 6);
696 s
->vc
= qemu_new_vlan_client(nd
->vlan
, ne2000_receive
, s
);
698 snprintf(s
->vc
->info_str
, sizeof(s
->vc
->info_str
),
699 "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
707 register_savevm("ne2000", 0, 1, ne2000_save
, ne2000_load
, s
);
710 /***********************************************************/
711 /* PCI NE2000 definitions */
713 typedef struct PCINE2000State
{
718 static void ne2000_map(PCIDevice
*pci_dev
, int region_num
,
719 uint32_t addr
, uint32_t size
, int type
)
721 PCINE2000State
*d
= (PCINE2000State
*)pci_dev
;
722 NE2000State
*s
= &d
->ne2000
;
724 register_ioport_write(addr
, 16, 1, ne2000_ioport_write
, s
);
725 register_ioport_read(addr
, 16, 1, ne2000_ioport_read
, s
);
727 register_ioport_write(addr
+ 0x10, 1, 1, ne2000_asic_ioport_write
, s
);
728 register_ioport_read(addr
+ 0x10, 1, 1, ne2000_asic_ioport_read
, s
);
729 register_ioport_write(addr
+ 0x10, 2, 2, ne2000_asic_ioport_write
, s
);
730 register_ioport_read(addr
+ 0x10, 2, 2, ne2000_asic_ioport_read
, s
);
731 register_ioport_write(addr
+ 0x10, 4, 4, ne2000_asic_ioport_writel
, s
);
732 register_ioport_read(addr
+ 0x10, 4, 4, ne2000_asic_ioport_readl
, s
);
734 register_ioport_write(addr
+ 0x1f, 1, 1, ne2000_reset_ioport_write
, s
);
735 register_ioport_read(addr
+ 0x1f, 1, 1, ne2000_reset_ioport_read
, s
);
738 void pci_ne2000_init(PCIBus
*bus
, NICInfo
*nd
)
744 d
= (PCINE2000State
*)pci_register_device(bus
,
745 "NE2000", sizeof(PCINE2000State
),
748 pci_conf
= d
->dev
.config
;
749 pci_conf
[0x00] = 0xec; // Realtek 8029
750 pci_conf
[0x01] = 0x10;
751 pci_conf
[0x02] = 0x29;
752 pci_conf
[0x03] = 0x80;
753 pci_conf
[0x0a] = 0x00; // ethernet network controller
754 pci_conf
[0x0b] = 0x02;
755 pci_conf
[0x0e] = 0x00; // header_type
756 pci_conf
[0x3d] = 1; // interrupt pin 0
758 pci_register_io_region(&d
->dev
, 0, 0x100,
759 PCI_ADDRESS_SPACE_IO
, ne2000_map
);
761 s
->irq
= 16; // PCI interrupt
762 s
->pci_dev
= (PCIDevice
*)d
;
763 memcpy(s
->macaddr
, nd
->macaddr
, 6);
765 s
->vc
= qemu_new_vlan_client(nd
->vlan
, ne2000_receive
, s
);
767 snprintf(s
->vc
->info_str
, sizeof(s
->vc
->info_str
),
768 "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
776 /* XXX: instance number ? */
777 register_savevm("ne2000", 0, 1, ne2000_save
, ne2000_load
, s
);
778 register_savevm("ne2000_pci", 0, 1, generic_pci_save
, generic_pci_load
,