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Merge branch 'omap-for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm...
[qemu.git] / hw / nseries.c
1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "sysemu.h"
23 #include "omap.h"
24 #include "arm-misc.h"
25 #include "irq.h"
26 #include "console.h"
27 #include "boards.h"
28 #include "i2c.h"
29 #include "devices.h"
30 #include "flash.h"
31 #include "hw.h"
32 #include "bt.h"
33 #include "loader.h"
34 #include "blockdev.h"
35 #include "tusb6010.h"
36 #include "sysbus.h"
37
38 /* Nokia N8x0 support */
39 struct n800_s {
40 struct omap_mpu_state_s *cpu;
41
42 struct rfbi_chip_s blizzard;
43 struct {
44 void *opaque;
45 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
46 uWireSlave *chip;
47 } ts;
48 i2c_bus *i2c;
49
50 int keymap[0x80];
51 DeviceState *kbd;
52
53 TUSBState *usb;
54 void *retu;
55 void *tahvo;
56 DeviceState *nand;
57 };
58
59 /* GPIO pins */
60 #define N8X0_TUSB_ENABLE_GPIO 0
61 #define N800_MMC2_WP_GPIO 8
62 #define N800_UNKNOWN_GPIO0 9 /* out */
63 #define N810_MMC2_VIOSD_GPIO 9
64 #define N810_HEADSET_AMP_GPIO 10
65 #define N800_CAM_TURN_GPIO 12
66 #define N810_GPS_RESET_GPIO 12
67 #define N800_BLIZZARD_POWERDOWN_GPIO 15
68 #define N800_MMC1_WP_GPIO 23
69 #define N810_MMC2_VSD_GPIO 23
70 #define N8X0_ONENAND_GPIO 26
71 #define N810_BLIZZARD_RESET_GPIO 30
72 #define N800_UNKNOWN_GPIO2 53 /* out */
73 #define N8X0_TUSB_INT_GPIO 58
74 #define N8X0_BT_WKUP_GPIO 61
75 #define N8X0_STI_GPIO 62
76 #define N8X0_CBUS_SEL_GPIO 64
77 #define N8X0_CBUS_DAT_GPIO 65
78 #define N8X0_CBUS_CLK_GPIO 66
79 #define N8X0_WLAN_IRQ_GPIO 87
80 #define N8X0_BT_RESET_GPIO 92
81 #define N8X0_TEA5761_CS_GPIO 93
82 #define N800_UNKNOWN_GPIO 94
83 #define N810_TSC_RESET_GPIO 94
84 #define N800_CAM_ACT_GPIO 95
85 #define N810_GPS_WAKEUP_GPIO 95
86 #define N8X0_MMC_CS_GPIO 96
87 #define N8X0_WLAN_PWR_GPIO 97
88 #define N8X0_BT_HOST_WKUP_GPIO 98
89 #define N810_SPEAKER_AMP_GPIO 101
90 #define N810_KB_LOCK_GPIO 102
91 #define N800_TSC_TS_GPIO 103
92 #define N810_TSC_TS_GPIO 106
93 #define N8X0_HEADPHONE_GPIO 107
94 #define N8X0_RETU_GPIO 108
95 #define N800_TSC_KP_IRQ_GPIO 109
96 #define N810_KEYBOARD_GPIO 109
97 #define N800_BAT_COVER_GPIO 110
98 #define N810_SLIDE_GPIO 110
99 #define N8X0_TAHVO_GPIO 111
100 #define N800_UNKNOWN_GPIO4 112 /* out */
101 #define N810_SLEEPX_LED_GPIO 112
102 #define N800_TSC_RESET_GPIO 118 /* ? */
103 #define N810_AIC33_RESET_GPIO 118
104 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
105 #define N8X0_TMP105_GPIO 125
106
107 /* Config */
108 #define BT_UART 0
109 #define XLDR_LL_UART 1
110
111 /* Addresses on the I2C bus 0 */
112 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
113 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
114 #define N810_LP5521_ADDR 0x32 /* LEDs */
115 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
116 #define N810_LM8323_ADDR 0x45 /* Keyboard */
117 /* Addresses on the I2C bus 1 */
118 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
119 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
120
121 /* Chipselects on GPMC NOR interface */
122 #define N8X0_ONENAND_CS 0
123 #define N8X0_USB_ASYNC_CS 1
124 #define N8X0_USB_SYNC_CS 4
125
126 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
127
128 static void n800_mmc_cs_cb(void *opaque, int line, int level)
129 {
130 /* TODO: this seems to actually be connected to the menelaus, to
131 * which also both MMC slots connect. */
132 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
133
134 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
135 }
136
137 static void n8x0_gpio_setup(struct n800_s *s)
138 {
139 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
140 qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
141
142 qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO));
143 }
144
145 #define MAEMO_CAL_HEADER(...) \
146 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
147 __VA_ARGS__, \
148 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
149
150 static const uint8_t n8x0_cal_wlan_mac[] = {
151 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
152 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
153 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
154 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
155 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
156 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
157 };
158
159 static const uint8_t n8x0_cal_bt_id[] = {
160 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
161 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
162 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
163 N8X0_BD_ADDR,
164 };
165
166 static void n8x0_nand_setup(struct n800_s *s)
167 {
168 char *otp_region;
169 DriveInfo *dinfo;
170
171 s->nand = qdev_create(NULL, "onenand");
172 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
173 /* Either 0x40 or 0x48 are OK for the device ID */
174 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
175 qdev_prop_set_uint16(s->nand, "version_id", 0);
176 qdev_prop_set_int32(s->nand, "shift", 1);
177 dinfo = drive_get(IF_MTD, 0, 0);
178 if (dinfo && dinfo->bdrv) {
179 qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv);
180 }
181 qdev_init_nofail(s->nand);
182 sysbus_connect_irq(sysbus_from_qdev(s->nand), 0,
183 qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
184 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS,
185 sysbus_mmio_get_region(sysbus_from_qdev(s->nand), 0));
186 otp_region = onenand_raw_otp(s->nand);
187
188 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
189 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
190 /* XXX: in theory should also update the OOB for both pages */
191 }
192
193 static void n8x0_i2c_setup(struct n800_s *s)
194 {
195 DeviceState *dev;
196 qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
197
198 /* Attach the CPU on one end of our I2C bus. */
199 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
200
201 /* Attach a menelaus PM chip */
202 dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
203 qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
204
205 /* Attach a TMP105 PM chip (A0 wired to ground) */
206 dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
207 qdev_connect_gpio_out(dev, 0, tmp_irq);
208 }
209
210 /* Touchscreen and keypad controller */
211 static MouseTransformInfo n800_pointercal = {
212 .x = 800,
213 .y = 480,
214 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
215 };
216
217 static MouseTransformInfo n810_pointercal = {
218 .x = 800,
219 .y = 480,
220 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
221 };
222
223 #define RETU_KEYCODE 61 /* F3 */
224
225 static void n800_key_event(void *opaque, int keycode)
226 {
227 struct n800_s *s = (struct n800_s *) opaque;
228 int code = s->keymap[keycode & 0x7f];
229
230 if (code == -1) {
231 if ((keycode & 0x7f) == RETU_KEYCODE)
232 retu_key_event(s->retu, !(keycode & 0x80));
233 return;
234 }
235
236 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
237 }
238
239 static const int n800_keys[16] = {
240 -1,
241 72, /* Up */
242 63, /* Home (F5) */
243 -1,
244 75, /* Left */
245 28, /* Enter */
246 77, /* Right */
247 -1,
248 1, /* Cycle (ESC) */
249 80, /* Down */
250 62, /* Menu (F4) */
251 -1,
252 66, /* Zoom- (F8) */
253 64, /* FullScreen (F6) */
254 65, /* Zoom+ (F7) */
255 -1,
256 };
257
258 static void n800_tsc_kbd_setup(struct n800_s *s)
259 {
260 int i;
261
262 /* XXX: are the three pins inverted inside the chip between the
263 * tsc and the cpu (N4111)? */
264 qemu_irq penirq = NULL; /* NC */
265 qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO);
266 qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO);
267
268 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
269 s->ts.opaque = s->ts.chip->opaque;
270 s->ts.txrx = tsc210x_txrx;
271
272 for (i = 0; i < 0x80; i ++)
273 s->keymap[i] = -1;
274 for (i = 0; i < 0x10; i ++)
275 if (n800_keys[i] >= 0)
276 s->keymap[n800_keys[i]] = i;
277
278 qemu_add_kbd_event_handler(n800_key_event, s);
279
280 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
281 }
282
283 static void n810_tsc_setup(struct n800_s *s)
284 {
285 qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO);
286
287 s->ts.opaque = tsc2005_init(pintdav);
288 s->ts.txrx = tsc2005_txrx;
289
290 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
291 }
292
293 /* N810 Keyboard controller */
294 static void n810_key_event(void *opaque, int keycode)
295 {
296 struct n800_s *s = (struct n800_s *) opaque;
297 int code = s->keymap[keycode & 0x7f];
298
299 if (code == -1) {
300 if ((keycode & 0x7f) == RETU_KEYCODE)
301 retu_key_event(s->retu, !(keycode & 0x80));
302 return;
303 }
304
305 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
306 }
307
308 #define M 0
309
310 static int n810_keys[0x80] = {
311 [0x01] = 16, /* Q */
312 [0x02] = 37, /* K */
313 [0x03] = 24, /* O */
314 [0x04] = 25, /* P */
315 [0x05] = 14, /* Backspace */
316 [0x06] = 30, /* A */
317 [0x07] = 31, /* S */
318 [0x08] = 32, /* D */
319 [0x09] = 33, /* F */
320 [0x0a] = 34, /* G */
321 [0x0b] = 35, /* H */
322 [0x0c] = 36, /* J */
323
324 [0x11] = 17, /* W */
325 [0x12] = 62, /* Menu (F4) */
326 [0x13] = 38, /* L */
327 [0x14] = 40, /* ' (Apostrophe) */
328 [0x16] = 44, /* Z */
329 [0x17] = 45, /* X */
330 [0x18] = 46, /* C */
331 [0x19] = 47, /* V */
332 [0x1a] = 48, /* B */
333 [0x1b] = 49, /* N */
334 [0x1c] = 42, /* Shift (Left shift) */
335 [0x1f] = 65, /* Zoom+ (F7) */
336
337 [0x21] = 18, /* E */
338 [0x22] = 39, /* ; (Semicolon) */
339 [0x23] = 12, /* - (Minus) */
340 [0x24] = 13, /* = (Equal) */
341 [0x2b] = 56, /* Fn (Left Alt) */
342 [0x2c] = 50, /* M */
343 [0x2f] = 66, /* Zoom- (F8) */
344
345 [0x31] = 19, /* R */
346 [0x32] = 29 | M, /* Right Ctrl */
347 [0x34] = 57, /* Space */
348 [0x35] = 51, /* , (Comma) */
349 [0x37] = 72 | M, /* Up */
350 [0x3c] = 82 | M, /* Compose (Insert) */
351 [0x3f] = 64, /* FullScreen (F6) */
352
353 [0x41] = 20, /* T */
354 [0x44] = 52, /* . (Dot) */
355 [0x46] = 77 | M, /* Right */
356 [0x4f] = 63, /* Home (F5) */
357 [0x51] = 21, /* Y */
358 [0x53] = 80 | M, /* Down */
359 [0x55] = 28, /* Enter */
360 [0x5f] = 1, /* Cycle (ESC) */
361
362 [0x61] = 22, /* U */
363 [0x64] = 75 | M, /* Left */
364
365 [0x71] = 23, /* I */
366 #if 0
367 [0x75] = 28 | M, /* KP Enter (KP Enter) */
368 #else
369 [0x75] = 15, /* KP Enter (Tab) */
370 #endif
371 };
372
373 #undef M
374
375 static void n810_kbd_setup(struct n800_s *s)
376 {
377 qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO);
378 int i;
379
380 for (i = 0; i < 0x80; i ++)
381 s->keymap[i] = -1;
382 for (i = 0; i < 0x80; i ++)
383 if (n810_keys[i] > 0)
384 s->keymap[n810_keys[i]] = i;
385
386 qemu_add_kbd_event_handler(n810_key_event, s);
387
388 /* Attach the LM8322 keyboard to the I2C bus,
389 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
390 s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
391 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
392 }
393
394 /* LCD MIPI DBI-C controller (URAL) */
395 struct mipid_s {
396 int resp[4];
397 int param[4];
398 int p;
399 int pm;
400 int cmd;
401
402 int sleep;
403 int booster;
404 int te;
405 int selfcheck;
406 int partial;
407 int normal;
408 int vscr;
409 int invert;
410 int onoff;
411 int gamma;
412 uint32_t id;
413 };
414
415 static void mipid_reset(struct mipid_s *s)
416 {
417 if (!s->sleep)
418 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
419
420 s->pm = 0;
421 s->cmd = 0;
422
423 s->sleep = 1;
424 s->booster = 0;
425 s->selfcheck =
426 (1 << 7) | /* Register loading OK. */
427 (1 << 5) | /* The chip is attached. */
428 (1 << 4); /* Display glass still in one piece. */
429 s->te = 0;
430 s->partial = 0;
431 s->normal = 1;
432 s->vscr = 0;
433 s->invert = 0;
434 s->onoff = 1;
435 s->gamma = 0;
436 }
437
438 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
439 {
440 struct mipid_s *s = (struct mipid_s *) opaque;
441 uint8_t ret;
442
443 if (len > 9)
444 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
445
446 if (s->p >= ARRAY_SIZE(s->resp))
447 ret = 0;
448 else
449 ret = s->resp[s->p ++];
450 if (s->pm --> 0)
451 s->param[s->pm] = cmd;
452 else
453 s->cmd = cmd;
454
455 switch (s->cmd) {
456 case 0x00: /* NOP */
457 break;
458
459 case 0x01: /* SWRESET */
460 mipid_reset(s);
461 break;
462
463 case 0x02: /* BSTROFF */
464 s->booster = 0;
465 break;
466 case 0x03: /* BSTRON */
467 s->booster = 1;
468 break;
469
470 case 0x04: /* RDDID */
471 s->p = 0;
472 s->resp[0] = (s->id >> 16) & 0xff;
473 s->resp[1] = (s->id >> 8) & 0xff;
474 s->resp[2] = (s->id >> 0) & 0xff;
475 break;
476
477 case 0x06: /* RD_RED */
478 case 0x07: /* RD_GREEN */
479 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
480 * for the bootloader one needs to change this. */
481 case 0x08: /* RD_BLUE */
482 s->p = 0;
483 /* TODO: return first pixel components */
484 s->resp[0] = 0x01;
485 break;
486
487 case 0x09: /* RDDST */
488 s->p = 0;
489 s->resp[0] = s->booster << 7;
490 s->resp[1] = (5 << 4) | (s->partial << 2) |
491 (s->sleep << 1) | s->normal;
492 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
493 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
494 s->resp[3] = s->gamma << 6;
495 break;
496
497 case 0x0a: /* RDDPM */
498 s->p = 0;
499 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
500 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
501 break;
502 case 0x0b: /* RDDMADCTR */
503 s->p = 0;
504 s->resp[0] = 0;
505 break;
506 case 0x0c: /* RDDCOLMOD */
507 s->p = 0;
508 s->resp[0] = 5; /* 65K colours */
509 break;
510 case 0x0d: /* RDDIM */
511 s->p = 0;
512 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
513 break;
514 case 0x0e: /* RDDSM */
515 s->p = 0;
516 s->resp[0] = s->te << 7;
517 break;
518 case 0x0f: /* RDDSDR */
519 s->p = 0;
520 s->resp[0] = s->selfcheck;
521 break;
522
523 case 0x10: /* SLPIN */
524 s->sleep = 1;
525 break;
526 case 0x11: /* SLPOUT */
527 s->sleep = 0;
528 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
529 break;
530
531 case 0x12: /* PTLON */
532 s->partial = 1;
533 s->normal = 0;
534 s->vscr = 0;
535 break;
536 case 0x13: /* NORON */
537 s->partial = 0;
538 s->normal = 1;
539 s->vscr = 0;
540 break;
541
542 case 0x20: /* INVOFF */
543 s->invert = 0;
544 break;
545 case 0x21: /* INVON */
546 s->invert = 1;
547 break;
548
549 case 0x22: /* APOFF */
550 case 0x23: /* APON */
551 goto bad_cmd;
552
553 case 0x25: /* WRCNTR */
554 if (s->pm < 0)
555 s->pm = 1;
556 goto bad_cmd;
557
558 case 0x26: /* GAMSET */
559 if (!s->pm)
560 s->gamma = ffs(s->param[0] & 0xf) - 1;
561 else if (s->pm < 0)
562 s->pm = 1;
563 break;
564
565 case 0x28: /* DISPOFF */
566 s->onoff = 0;
567 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
568 break;
569 case 0x29: /* DISPON */
570 s->onoff = 1;
571 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
572 break;
573
574 case 0x2a: /* CASET */
575 case 0x2b: /* RASET */
576 case 0x2c: /* RAMWR */
577 case 0x2d: /* RGBSET */
578 case 0x2e: /* RAMRD */
579 case 0x30: /* PTLAR */
580 case 0x33: /* SCRLAR */
581 goto bad_cmd;
582
583 case 0x34: /* TEOFF */
584 s->te = 0;
585 break;
586 case 0x35: /* TEON */
587 if (!s->pm)
588 s->te = 1;
589 else if (s->pm < 0)
590 s->pm = 1;
591 break;
592
593 case 0x36: /* MADCTR */
594 goto bad_cmd;
595
596 case 0x37: /* VSCSAD */
597 s->partial = 0;
598 s->normal = 0;
599 s->vscr = 1;
600 break;
601
602 case 0x38: /* IDMOFF */
603 case 0x39: /* IDMON */
604 case 0x3a: /* COLMOD */
605 goto bad_cmd;
606
607 case 0xb0: /* CLKINT / DISCTL */
608 case 0xb1: /* CLKEXT */
609 if (s->pm < 0)
610 s->pm = 2;
611 break;
612
613 case 0xb4: /* FRMSEL */
614 break;
615
616 case 0xb5: /* FRM8SEL */
617 case 0xb6: /* TMPRNG / INIESC */
618 case 0xb7: /* TMPHIS / NOP2 */
619 case 0xb8: /* TMPREAD / MADCTL */
620 case 0xba: /* DISTCTR */
621 case 0xbb: /* EPVOL */
622 goto bad_cmd;
623
624 case 0xbd: /* Unknown */
625 s->p = 0;
626 s->resp[0] = 0;
627 s->resp[1] = 1;
628 break;
629
630 case 0xc2: /* IFMOD */
631 if (s->pm < 0)
632 s->pm = 2;
633 break;
634
635 case 0xc6: /* PWRCTL */
636 case 0xc7: /* PPWRCTL */
637 case 0xd0: /* EPWROUT */
638 case 0xd1: /* EPWRIN */
639 case 0xd4: /* RDEV */
640 case 0xd5: /* RDRR */
641 goto bad_cmd;
642
643 case 0xda: /* RDID1 */
644 s->p = 0;
645 s->resp[0] = (s->id >> 16) & 0xff;
646 break;
647 case 0xdb: /* RDID2 */
648 s->p = 0;
649 s->resp[0] = (s->id >> 8) & 0xff;
650 break;
651 case 0xdc: /* RDID3 */
652 s->p = 0;
653 s->resp[0] = (s->id >> 0) & 0xff;
654 break;
655
656 default:
657 bad_cmd:
658 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
659 break;
660 }
661
662 return ret;
663 }
664
665 static void *mipid_init(void)
666 {
667 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
668
669 s->id = 0x838f03;
670 mipid_reset(s);
671
672 return s;
673 }
674
675 static void n8x0_spi_setup(struct n800_s *s)
676 {
677 void *tsc = s->ts.opaque;
678 void *mipid = mipid_init();
679
680 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
681 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
682 }
683
684 /* This task is normally performed by the bootloader. If we're loading
685 * a kernel directly, we need to enable the Blizzard ourselves. */
686 static void n800_dss_init(struct rfbi_chip_s *chip)
687 {
688 uint8_t *fb_blank;
689
690 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
691 chip->write(chip->opaque, 1, 0x64);
692 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
693 chip->write(chip->opaque, 1, 0x1e);
694 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
695 chip->write(chip->opaque, 1, 0xe0);
696 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
697 chip->write(chip->opaque, 1, 0x01);
698 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
699 chip->write(chip->opaque, 1, 0x06);
700 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
701 chip->write(chip->opaque, 1, 1); /* Enable bit */
702
703 chip->write(chip->opaque, 0, 0x6c);
704 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
705 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
706 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
707 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
708 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
709 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
710 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
711 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
712 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
713 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
714 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
715 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
716 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
717 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
718 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
719 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
720 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
721 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
722
723 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
724 /* Display Memory Data Port */
725 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
726 g_free(fb_blank);
727 }
728
729 static void n8x0_dss_setup(struct n800_s *s)
730 {
731 s->blizzard.opaque = s1d13745_init(NULL);
732 s->blizzard.block = s1d13745_write_block;
733 s->blizzard.write = s1d13745_write;
734 s->blizzard.read = s1d13745_read;
735
736 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
737 }
738
739 static void n8x0_cbus_setup(struct n800_s *s)
740 {
741 qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO);
742 qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO);
743 qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO);
744
745 CBus *cbus = cbus_init(dat_out);
746
747 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
748 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
749 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
750
751 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
752 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
753 }
754
755 static void n8x0_uart_setup(struct n800_s *s)
756 {
757 CharDriverState *radio = uart_hci_init(
758 qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
759
760 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO,
761 csrhci_pins_get(radio)[csrhci_pin_reset]);
762 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO,
763 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
764
765 omap_uart_attach(s->cpu->uart[BT_UART], radio);
766 }
767
768 static void n8x0_usb_power_cb(void *opaque, int line, int level)
769 {
770 struct n800_s *s = opaque;
771
772 tusb6010_power(s->usb, level);
773 }
774
775 static void n8x0_usb_setup(struct n800_s *s)
776 {
777 qemu_irq tusb_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO);
778 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
779 TUSBState *tusb = tusb6010_init(tusb_irq);
780
781 /* Using the NOR interface */
782 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS, tusb6010_async_io(tusb));
783 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS, tusb6010_sync_io(tusb));
784
785 s->usb = tusb;
786 qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
787 }
788
789 /* Setup done before the main bootloader starts by some early setup code
790 * - used when we want to run the main bootloader in emulation. This
791 * isn't documented. */
792 static uint32_t n800_pinout[104] = {
793 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
794 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
795 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
796 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
797 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
798 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
799 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
800 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
801 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
802 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
803 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
804 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
805 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
806 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
807 0x00000000, 0x00000038, 0x00340000, 0x00000000,
808 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
809 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
810 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
811 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
812 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
813 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
814 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
815 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
816 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
817 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
818 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
819 };
820
821 static void n800_setup_nolo_tags(void *sram_base)
822 {
823 int i;
824 uint32_t *p = sram_base + 0x8000;
825 uint32_t *v = sram_base + 0xa000;
826
827 memset(p, 0, 0x3000);
828
829 strcpy((void *) (p + 0), "QEMU N800");
830
831 strcpy((void *) (p + 8), "F5");
832
833 stl_raw(p + 10, 0x04f70000);
834 strcpy((void *) (p + 9), "RX-34");
835
836 /* RAM size in MB? */
837 stl_raw(p + 12, 0x80);
838
839 /* Pointer to the list of tags */
840 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
841
842 /* The NOLO tags start here */
843 p = sram_base + 0x9000;
844 #define ADD_TAG(tag, len) \
845 stw_raw((uint16_t *) p + 0, tag); \
846 stw_raw((uint16_t *) p + 1, len); p ++; \
847 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
848
849 /* OMAP STI console? Pin out settings? */
850 ADD_TAG(0x6e01, 414);
851 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
852 stl_raw(v ++, n800_pinout[i]);
853
854 /* Kernel memsize? */
855 ADD_TAG(0x6e05, 1);
856 stl_raw(v ++, 2);
857
858 /* NOLO serial console */
859 ADD_TAG(0x6e02, 4);
860 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
861
862 #if 0
863 /* CBUS settings (Retu/AVilma) */
864 ADD_TAG(0x6e03, 6);
865 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
866 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
867 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
868 v += 2;
869 #endif
870
871 /* Nokia ASIC BB5 (Retu/Tahvo) */
872 ADD_TAG(0x6e0a, 4);
873 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
874 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
875 v ++;
876
877 /* LCD console? */
878 ADD_TAG(0x6e04, 4);
879 stw_raw((uint16_t *) v + 0, 30); /* ??? */
880 stw_raw((uint16_t *) v + 1, 24); /* ??? */
881 v ++;
882
883 #if 0
884 /* LCD settings */
885 ADD_TAG(0x6e06, 2);
886 stw_raw((uint16_t *) (v ++), 15); /* ??? */
887 #endif
888
889 /* I^2C (Menelaus) */
890 ADD_TAG(0x6e07, 4);
891 stl_raw(v ++, 0x00720000); /* ??? */
892
893 /* Unknown */
894 ADD_TAG(0x6e0b, 6);
895 stw_raw((uint16_t *) v + 0, 94); /* ??? */
896 stw_raw((uint16_t *) v + 1, 23); /* ??? */
897 stw_raw((uint16_t *) v + 2, 0); /* ??? */
898 v += 2;
899
900 /* OMAP gpio switch info */
901 ADD_TAG(0x6e0c, 80);
902 strcpy((void *) v, "bat_cover"); v += 3;
903 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
904 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
905 v += 2;
906 strcpy((void *) v, "cam_act"); v += 3;
907 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
908 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
909 v += 2;
910 strcpy((void *) v, "cam_turn"); v += 3;
911 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
912 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
913 v += 2;
914 strcpy((void *) v, "headphone"); v += 3;
915 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
916 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
917 v += 2;
918
919 /* Bluetooth */
920 ADD_TAG(0x6e0e, 12);
921 stl_raw(v ++, 0x5c623d01); /* ??? */
922 stl_raw(v ++, 0x00000201); /* ??? */
923 stl_raw(v ++, 0x00000000); /* ??? */
924
925 /* CX3110x WLAN settings */
926 ADD_TAG(0x6e0f, 8);
927 stl_raw(v ++, 0x00610025); /* ??? */
928 stl_raw(v ++, 0xffff0057); /* ??? */
929
930 /* MMC host settings */
931 ADD_TAG(0x6e10, 12);
932 stl_raw(v ++, 0xffff000f); /* ??? */
933 stl_raw(v ++, 0xffffffff); /* ??? */
934 stl_raw(v ++, 0x00000060); /* ??? */
935
936 /* OneNAND chip select */
937 ADD_TAG(0x6e11, 10);
938 stl_raw(v ++, 0x00000401); /* ??? */
939 stl_raw(v ++, 0x0002003a); /* ??? */
940 stl_raw(v ++, 0x00000002); /* ??? */
941
942 /* TEA5761 sensor settings */
943 ADD_TAG(0x6e12, 2);
944 stl_raw(v ++, 93); /* GPIO num ??? */
945
946 #if 0
947 /* Unknown tag */
948 ADD_TAG(6e09, 0);
949
950 /* Kernel UART / console */
951 ADD_TAG(6e12, 0);
952 #endif
953
954 /* End of the list */
955 stl_raw(p ++, 0x00000000);
956 stl_raw(p ++, 0x00000000);
957 }
958
959 /* This task is normally performed by the bootloader. If we're loading
960 * a kernel directly, we need to set up GPMC mappings ourselves. */
961 static void n800_gpmc_init(struct n800_s *s)
962 {
963 uint32_t config7 =
964 (0xf << 8) | /* MASKADDRESS */
965 (1 << 6) | /* CSVALID */
966 (4 << 0); /* BASEADDRESS */
967
968 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
969 (void *) &config7, sizeof(config7));
970 }
971
972 /* Setup sequence done by the bootloader */
973 static void n8x0_boot_init(void *opaque)
974 {
975 struct n800_s *s = (struct n800_s *) opaque;
976 uint32_t buf;
977
978 /* PRCM setup */
979 #define omap_writel(addr, val) \
980 buf = (val); \
981 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
982
983 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
984 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
985 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
986 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
987 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
988 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
989 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
990 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
991 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
992 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
993 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
994 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
995 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
996 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
997 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
998 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
999 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1000 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1001 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1002 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1003 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1004 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1005 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1006 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1007 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1008 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1009 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1010 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1011 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1012 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1013 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1014 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1015 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1016 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1017 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1018 (0x78 << 12) | (6 << 8));
1019 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1020
1021 /* GPMC setup */
1022 n800_gpmc_init(s);
1023
1024 /* Video setup */
1025 n800_dss_init(&s->blizzard);
1026
1027 /* CPU setup */
1028 s->cpu->env->GE = 0x5;
1029
1030 /* If the machine has a slided keyboard, open it */
1031 if (s->kbd)
1032 qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO));
1033 }
1034
1035 #define OMAP_TAG_NOKIA_BT 0x4e01
1036 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1037 #define OMAP_TAG_CBUS 0x4e03
1038 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1039
1040 static struct omap_gpiosw_info_s {
1041 const char *name;
1042 int line;
1043 int type;
1044 } n800_gpiosw_info[] = {
1045 {
1046 "bat_cover", N800_BAT_COVER_GPIO,
1047 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1048 }, {
1049 "cam_act", N800_CAM_ACT_GPIO,
1050 OMAP_GPIOSW_TYPE_ACTIVITY,
1051 }, {
1052 "cam_turn", N800_CAM_TURN_GPIO,
1053 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1054 }, {
1055 "headphone", N8X0_HEADPHONE_GPIO,
1056 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1057 },
1058 { NULL }
1059 }, n810_gpiosw_info[] = {
1060 {
1061 "gps_reset", N810_GPS_RESET_GPIO,
1062 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1063 }, {
1064 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1065 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1066 }, {
1067 "headphone", N8X0_HEADPHONE_GPIO,
1068 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1069 }, {
1070 "kb_lock", N810_KB_LOCK_GPIO,
1071 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1072 }, {
1073 "sleepx_led", N810_SLEEPX_LED_GPIO,
1074 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1075 }, {
1076 "slide", N810_SLIDE_GPIO,
1077 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1078 },
1079 { NULL }
1080 };
1081
1082 static struct omap_partition_info_s {
1083 uint32_t offset;
1084 uint32_t size;
1085 int mask;
1086 const char *name;
1087 } n800_part_info[] = {
1088 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1089 { 0x00020000, 0x00060000, 0x0, "config" },
1090 { 0x00080000, 0x00200000, 0x0, "kernel" },
1091 { 0x00280000, 0x00200000, 0x3, "initfs" },
1092 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1093
1094 { 0, 0, 0, NULL }
1095 }, n810_part_info[] = {
1096 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1097 { 0x00020000, 0x00060000, 0x0, "config" },
1098 { 0x00080000, 0x00220000, 0x0, "kernel" },
1099 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1100 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1101
1102 { 0, 0, 0, NULL }
1103 };
1104
1105 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1106
1107 static int n8x0_atag_setup(void *p, int model)
1108 {
1109 uint8_t *b;
1110 uint16_t *w;
1111 uint32_t *l;
1112 struct omap_gpiosw_info_s *gpiosw;
1113 struct omap_partition_info_s *partition;
1114 const char *tag;
1115
1116 w = p;
1117
1118 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1119 stw_raw(w ++, 4); /* u16 len */
1120 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1121 w ++;
1122
1123 #if 0
1124 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1125 stw_raw(w ++, 4); /* u16 len */
1126 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1127 stw_raw(w ++, 115200); /* u32 console_speed */
1128 #endif
1129
1130 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1131 stw_raw(w ++, 36); /* u16 len */
1132 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1133 w += 8;
1134 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1135 w += 8;
1136 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1137 stw_raw(w ++, 24); /* u8 data_lines */
1138
1139 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1140 stw_raw(w ++, 8); /* u16 len */
1141 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1142 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1143 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1144 w ++;
1145
1146 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1147 stw_raw(w ++, 4); /* u16 len */
1148 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1149 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1150
1151 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1152 for (; gpiosw->name; gpiosw ++) {
1153 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1154 stw_raw(w ++, 20); /* u16 len */
1155 strcpy((void *) w, gpiosw->name); /* char name[12] */
1156 w += 6;
1157 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1158 stw_raw(w ++, gpiosw->type);
1159 stw_raw(w ++, 0);
1160 stw_raw(w ++, 0);
1161 }
1162
1163 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1164 stw_raw(w ++, 12); /* u16 len */
1165 b = (void *) w;
1166 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1167 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1168 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1169 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1170 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1171 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1172 b += 6;
1173 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1174 w = (void *) b;
1175
1176 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1177 stw_raw(w ++, 8); /* u16 len */
1178 stw_raw(w ++, 0x25); /* u8 chip_type */
1179 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1180 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1181 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1182
1183 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1184 stw_raw(w ++, 16); /* u16 len */
1185 if (model == 810) {
1186 stw_raw(w ++, 0x23f); /* unsigned flags */
1187 stw_raw(w ++, -1); /* s16 power_pin */
1188 stw_raw(w ++, -1); /* s16 switch_pin */
1189 stw_raw(w ++, -1); /* s16 wp_pin */
1190 stw_raw(w ++, 0x240); /* unsigned flags */
1191 stw_raw(w ++, 0xc000); /* s16 power_pin */
1192 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1193 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1194 } else {
1195 stw_raw(w ++, 0xf); /* unsigned flags */
1196 stw_raw(w ++, -1); /* s16 power_pin */
1197 stw_raw(w ++, -1); /* s16 switch_pin */
1198 stw_raw(w ++, -1); /* s16 wp_pin */
1199 stw_raw(w ++, 0); /* unsigned flags */
1200 stw_raw(w ++, 0); /* s16 power_pin */
1201 stw_raw(w ++, 0); /* s16 switch_pin */
1202 stw_raw(w ++, 0); /* s16 wp_pin */
1203 }
1204
1205 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1206 stw_raw(w ++, 4); /* u16 len */
1207 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1208 w ++;
1209
1210 partition = (model == 810) ? n810_part_info : n800_part_info;
1211 for (; partition->name; partition ++) {
1212 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1213 stw_raw(w ++, 28); /* u16 len */
1214 strcpy((void *) w, partition->name); /* char name[16] */
1215 l = (void *) (w + 8);
1216 stl_raw(l ++, partition->size); /* unsigned int size */
1217 stl_raw(l ++, partition->offset); /* unsigned int offset */
1218 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1219 w = (void *) l;
1220 }
1221
1222 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1223 stw_raw(w ++, 12); /* u16 len */
1224 #if 0
1225 strcpy((void *) w, "por"); /* char reason_str[12] */
1226 strcpy((void *) w, "charger"); /* char reason_str[12] */
1227 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1228 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1229 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1230 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1231 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1232 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1233 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1234 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1235 #else
1236 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1237 #endif
1238 w += 6;
1239
1240 tag = (model == 810) ? "RX-44" : "RX-34";
1241 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1242 stw_raw(w ++, 24); /* u16 len */
1243 strcpy((void *) w, "product"); /* char component[12] */
1244 w += 6;
1245 strcpy((void *) w, tag); /* char version[12] */
1246 w += 6;
1247
1248 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1249 stw_raw(w ++, 24); /* u16 len */
1250 strcpy((void *) w, "hw-build"); /* char component[12] */
1251 w += 6;
1252 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
1253 w += 6;
1254
1255 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1256 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1257 stw_raw(w ++, 24); /* u16 len */
1258 strcpy((void *) w, "nolo"); /* char component[12] */
1259 w += 6;
1260 strcpy((void *) w, tag); /* char version[12] */
1261 w += 6;
1262
1263 return (void *) w - p;
1264 }
1265
1266 static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1267 {
1268 return n8x0_atag_setup(p, 800);
1269 }
1270
1271 static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1272 {
1273 return n8x0_atag_setup(p, 810);
1274 }
1275
1276 static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1277 const char *kernel_filename,
1278 const char *kernel_cmdline, const char *initrd_filename,
1279 const char *cpu_model, struct arm_boot_info *binfo, int model)
1280 {
1281 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1282 int sdram_size = binfo->ram_size;
1283 DisplayState *ds;
1284
1285 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
1286
1287 /* Setup peripherals
1288 *
1289 * Believed external peripherals layout in the N810:
1290 * (spi bus 1)
1291 * tsc2005
1292 * lcd_mipid
1293 * (spi bus 2)
1294 * Conexant cx3110x (WLAN)
1295 * optional: pc2400m (WiMAX)
1296 * (i2c bus 0)
1297 * TLV320AIC33 (audio codec)
1298 * TCM825x (camera by Toshiba)
1299 * lp5521 (clever LEDs)
1300 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1301 * lm8323 (keypad, manf 00, rev 04)
1302 * (i2c bus 1)
1303 * tmp105 (temperature sensor, hwmon)
1304 * menelaus (pm)
1305 * (somewhere on i2c - maybe N800-only)
1306 * tea5761 (FM tuner)
1307 * (serial 0)
1308 * GPS
1309 * (some serial port)
1310 * csr41814 (Bluetooth)
1311 */
1312 n8x0_gpio_setup(s);
1313 n8x0_nand_setup(s);
1314 n8x0_i2c_setup(s);
1315 if (model == 800)
1316 n800_tsc_kbd_setup(s);
1317 else if (model == 810) {
1318 n810_tsc_setup(s);
1319 n810_kbd_setup(s);
1320 }
1321 n8x0_spi_setup(s);
1322 n8x0_dss_setup(s);
1323 n8x0_cbus_setup(s);
1324 n8x0_uart_setup(s);
1325 if (usb_enabled)
1326 n8x0_usb_setup(s);
1327
1328 if (kernel_filename) {
1329 /* Or at the linux loader. */
1330 binfo->kernel_filename = kernel_filename;
1331 binfo->kernel_cmdline = kernel_cmdline;
1332 binfo->initrd_filename = initrd_filename;
1333 arm_load_kernel(s->cpu->env, binfo);
1334
1335 qemu_register_reset(n8x0_boot_init, s);
1336 }
1337
1338 if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) {
1339 int rom_size;
1340 uint8_t nolo_tags[0x10000];
1341 /* No, wait, better start at the ROM. */
1342 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1343
1344 /* This is intended for loading the `secondary.bin' program from
1345 * Nokia images (the NOLO bootloader). The entry point seems
1346 * to be at OMAP2_Q2_BASE + 0x400000.
1347 *
1348 * The `2nd.bin' files contain some kind of earlier boot code and
1349 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1350 *
1351 * The code above is for loading the `zImage' file from Nokia
1352 * images. */
1353 rom_size = load_image_targphys(option_rom[0].name,
1354 OMAP2_Q2_BASE + 0x400000,
1355 sdram_size - 0x400000);
1356 printf("%i bytes of image loaded\n", rom_size);
1357
1358 n800_setup_nolo_tags(nolo_tags);
1359 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1360 }
1361 /* FIXME: We shouldn't really be doing this here. The LCD controller
1362 will set the size once configured, so this just sets an initial
1363 size until the guest activates the display. */
1364 ds = get_displaystate();
1365 ds->surface = qemu_resize_displaysurface(ds, 800, 480);
1366 dpy_resize(ds);
1367 }
1368
1369 static struct arm_boot_info n800_binfo = {
1370 .loader_start = OMAP2_Q2_BASE,
1371 /* Actually two chips of 0x4000000 bytes each */
1372 .ram_size = 0x08000000,
1373 .board_id = 0x4f7,
1374 .atag_board = n800_atag_setup,
1375 };
1376
1377 static struct arm_boot_info n810_binfo = {
1378 .loader_start = OMAP2_Q2_BASE,
1379 /* Actually two chips of 0x4000000 bytes each */
1380 .ram_size = 0x08000000,
1381 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1382 * used by some older versions of the bootloader and 5555 is used
1383 * instead (including versions that shipped with many devices). */
1384 .board_id = 0x60c,
1385 .atag_board = n810_atag_setup,
1386 };
1387
1388 static void n800_init(ram_addr_t ram_size,
1389 const char *boot_device,
1390 const char *kernel_filename, const char *kernel_cmdline,
1391 const char *initrd_filename, const char *cpu_model)
1392 {
1393 return n8x0_init(ram_size, boot_device,
1394 kernel_filename, kernel_cmdline, initrd_filename,
1395 cpu_model, &n800_binfo, 800);
1396 }
1397
1398 static void n810_init(ram_addr_t ram_size,
1399 const char *boot_device,
1400 const char *kernel_filename, const char *kernel_cmdline,
1401 const char *initrd_filename, const char *cpu_model)
1402 {
1403 return n8x0_init(ram_size, boot_device,
1404 kernel_filename, kernel_cmdline, initrd_filename,
1405 cpu_model, &n810_binfo, 810);
1406 }
1407
1408 static QEMUMachine n800_machine = {
1409 .name = "n800",
1410 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1411 .init = n800_init,
1412 };
1413
1414 static QEMUMachine n810_machine = {
1415 .name = "n810",
1416 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1417 .init = n810_init,
1418 };
1419
1420 static void nseries_machine_init(void)
1421 {
1422 qemu_register_machine(&n800_machine);
1423 qemu_register_machine(&n810_machine);
1424 }
1425
1426 machine_init(nseries_machine_init);
Qemu copy for testing