2 * Texas Instruments OMAP processors.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 # define hw_omap_h "omap.h"
22 # define OMAP_EMIFS_BASE 0x00000000
23 # define OMAP2_Q0_BASE 0x00000000
24 # define OMAP_CS0_BASE 0x00000000
25 # define OMAP_CS1_BASE 0x04000000
26 # define OMAP_CS2_BASE 0x08000000
27 # define OMAP_CS3_BASE 0x0c000000
28 # define OMAP_EMIFF_BASE 0x10000000
29 # define OMAP_IMIF_BASE 0x20000000
30 # define OMAP_LOCALBUS_BASE 0x30000000
31 # define OMAP2_Q1_BASE 0x40000000
32 # define OMAP2_L4_BASE 0x48000000
33 # define OMAP2_SRAM_BASE 0x40200000
34 # define OMAP2_L3_BASE 0x68000000
35 # define OMAP2_Q2_BASE 0x80000000
36 # define OMAP2_Q3_BASE 0xc0000000
37 # define OMAP_MPUI_BASE 0xe1000000
39 # define OMAP730_SRAM_SIZE 0x00032000
40 # define OMAP15XX_SRAM_SIZE 0x00030000
41 # define OMAP16XX_SRAM_SIZE 0x00004000
42 # define OMAP1611_SRAM_SIZE 0x0003e800
43 # define OMAP242X_SRAM_SIZE 0x000a0000
44 # define OMAP243X_SRAM_SIZE 0x00010000
45 # define OMAP_CS0_SIZE 0x04000000
46 # define OMAP_CS1_SIZE 0x04000000
47 # define OMAP_CS2_SIZE 0x04000000
48 # define OMAP_CS3_SIZE 0x04000000
51 struct omap_mpu_state_s
;
52 typedef struct clk
*omap_clk
;
53 omap_clk
omap_findclk(struct omap_mpu_state_s
*mpu
, const char *name
);
54 void omap_clk_init(struct omap_mpu_state_s
*mpu
);
55 void omap_clk_adduser(struct clk
*clk
, qemu_irq user
);
56 void omap_clk_get(omap_clk clk
);
57 void omap_clk_put(omap_clk clk
);
58 void omap_clk_onoff(omap_clk clk
, int on
);
59 void omap_clk_canidle(omap_clk clk
, int can
);
60 void omap_clk_setrate(omap_clk clk
, int divide
, int multiply
);
61 int64_t omap_clk_getrate(omap_clk clk
);
62 void omap_clk_reparent(omap_clk clk
, omap_clk parent
);
64 /* OMAP2 l4 Interconnect */
66 struct omap_l4_region_s
{
67 target_phys_addr_t offset
;
71 struct omap_l4_agent_info_s
{
77 struct omap_target_agent_s
{
78 struct omap_l4_s
*bus
;
80 const struct omap_l4_region_s
*start
;
81 target_phys_addr_t base
;
86 struct omap_l4_s
*omap_l4_init(target_phys_addr_t base
, int ta_num
);
88 struct omap_target_agent_s
;
89 struct omap_target_agent_s
*omap_l4ta_get(
90 struct omap_l4_s
*bus
,
91 const struct omap_l4_region_s
*regions
,
92 const struct omap_l4_agent_info_s
*agents
,
94 target_phys_addr_t
omap_l4_attach(struct omap_target_agent_s
*ta
, int region
,
96 int l4_register_io_memory(CPUReadMemoryFunc
* const *mem_read
,
97 CPUWriteMemoryFunc
* const *mem_write
, void *opaque
);
99 /* OMAP interrupt controller */
100 struct omap_intr_handler_s
;
101 struct omap_intr_handler_s
*omap_inth_init(target_phys_addr_t base
,
102 unsigned long size
, unsigned char nbanks
, qemu_irq
**pins
,
103 qemu_irq parent_irq
, qemu_irq parent_fiq
, omap_clk clk
);
104 struct omap_intr_handler_s
*omap2_inth_init(target_phys_addr_t base
,
105 int size
, int nbanks
, qemu_irq
**pins
,
106 qemu_irq parent_irq
, qemu_irq parent_fiq
,
107 omap_clk fclk
, omap_clk iclk
);
108 void omap_inth_reset(struct omap_intr_handler_s
*s
);
109 qemu_irq
omap_inth_get_pin(struct omap_intr_handler_s
*s
, int n
);
112 struct omap_prcm_s
*omap_prcm_init(struct omap_target_agent_s
*ta
,
113 qemu_irq mpu_int
, qemu_irq dsp_int
, qemu_irq iva_int
,
114 struct omap_mpu_state_s
*mpu
);
116 struct omap_sysctl_s
;
117 struct omap_sysctl_s
*omap_sysctl_init(struct omap_target_agent_s
*ta
,
118 omap_clk iclk
, struct omap_mpu_state_s
*mpu
);
120 /* OMAP2 SDRAM controller */
122 struct omap_sdrc_s
*omap_sdrc_init(target_phys_addr_t base
);
123 void omap_sdrc_reset(struct omap_sdrc_s
*s
);
125 /* OMAP2 general purpose memory controller */
127 struct omap_gpmc_s
*omap_gpmc_init(target_phys_addr_t base
, qemu_irq irq
);
128 void omap_gpmc_reset(struct omap_gpmc_s
*s
);
129 void omap_gpmc_attach(struct omap_gpmc_s
*s
, int cs
, int iomemtype
,
130 void (*base_upd
)(void *opaque
, target_phys_addr_t
new),
131 void (*unmap
)(void *opaque
), void *opaque
);
134 * Common IRQ numbers for level 1 interrupt handler
135 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
137 # define OMAP_INT_CAMERA 1
138 # define OMAP_INT_FIQ 3
139 # define OMAP_INT_RTDX 6
140 # define OMAP_INT_DSP_MMU_ABORT 7
141 # define OMAP_INT_HOST 8
142 # define OMAP_INT_ABORT 9
143 # define OMAP_INT_BRIDGE_PRIV 13
144 # define OMAP_INT_GPIO_BANK1 14
145 # define OMAP_INT_UART3 15
146 # define OMAP_INT_TIMER3 16
147 # define OMAP_INT_DMA_CH0_6 19
148 # define OMAP_INT_DMA_CH1_7 20
149 # define OMAP_INT_DMA_CH2_8 21
150 # define OMAP_INT_DMA_CH3 22
151 # define OMAP_INT_DMA_CH4 23
152 # define OMAP_INT_DMA_CH5 24
153 # define OMAP_INT_DMA_LCD 25
154 # define OMAP_INT_TIMER1 26
155 # define OMAP_INT_WD_TIMER 27
156 # define OMAP_INT_BRIDGE_PUB 28
157 # define OMAP_INT_TIMER2 30
158 # define OMAP_INT_LCD_CTRL 31
161 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
163 # define OMAP_INT_15XX_IH2_IRQ 0
164 # define OMAP_INT_15XX_LB_MMU 17
165 # define OMAP_INT_15XX_LOCAL_BUS 29
168 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
170 # define OMAP_INT_1510_SPI_TX 4
171 # define OMAP_INT_1510_SPI_RX 5
172 # define OMAP_INT_1510_DSP_MAILBOX1 10
173 # define OMAP_INT_1510_DSP_MAILBOX2 11
176 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
178 # define OMAP_INT_310_McBSP2_TX 4
179 # define OMAP_INT_310_McBSP2_RX 5
180 # define OMAP_INT_310_HSB_MAILBOX1 12
181 # define OMAP_INT_310_HSAB_MMU 18
184 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
186 # define OMAP_INT_1610_IH2_IRQ 0
187 # define OMAP_INT_1610_IH2_FIQ 2
188 # define OMAP_INT_1610_McBSP2_TX 4
189 # define OMAP_INT_1610_McBSP2_RX 5
190 # define OMAP_INT_1610_DSP_MAILBOX1 10
191 # define OMAP_INT_1610_DSP_MAILBOX2 11
192 # define OMAP_INT_1610_LCD_LINE 12
193 # define OMAP_INT_1610_GPTIMER1 17
194 # define OMAP_INT_1610_GPTIMER2 18
195 # define OMAP_INT_1610_SSR_FIFO_0 29
198 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
200 # define OMAP_INT_730_IH2_FIQ 0
201 # define OMAP_INT_730_IH2_IRQ 1
202 # define OMAP_INT_730_USB_NON_ISO 2
203 # define OMAP_INT_730_USB_ISO 3
204 # define OMAP_INT_730_ICR 4
205 # define OMAP_INT_730_EAC 5
206 # define OMAP_INT_730_GPIO_BANK1 6
207 # define OMAP_INT_730_GPIO_BANK2 7
208 # define OMAP_INT_730_GPIO_BANK3 8
209 # define OMAP_INT_730_McBSP2TX 10
210 # define OMAP_INT_730_McBSP2RX 11
211 # define OMAP_INT_730_McBSP2RX_OVF 12
212 # define OMAP_INT_730_LCD_LINE 14
213 # define OMAP_INT_730_GSM_PROTECT 15
214 # define OMAP_INT_730_TIMER3 16
215 # define OMAP_INT_730_GPIO_BANK5 17
216 # define OMAP_INT_730_GPIO_BANK6 18
217 # define OMAP_INT_730_SPGIO_WR 29
220 * Common IRQ numbers for level 2 interrupt handler
222 # define OMAP_INT_KEYBOARD 1
223 # define OMAP_INT_uWireTX 2
224 # define OMAP_INT_uWireRX 3
225 # define OMAP_INT_I2C 4
226 # define OMAP_INT_MPUIO 5
227 # define OMAP_INT_USB_HHC_1 6
228 # define OMAP_INT_McBSP3TX 10
229 # define OMAP_INT_McBSP3RX 11
230 # define OMAP_INT_McBSP1TX 12
231 # define OMAP_INT_McBSP1RX 13
232 # define OMAP_INT_UART1 14
233 # define OMAP_INT_UART2 15
234 # define OMAP_INT_USB_W2FC 20
235 # define OMAP_INT_1WIRE 21
236 # define OMAP_INT_OS_TIMER 22
237 # define OMAP_INT_OQN 23
238 # define OMAP_INT_GAUGE_32K 24
239 # define OMAP_INT_RTC_TIMER 25
240 # define OMAP_INT_RTC_ALARM 26
241 # define OMAP_INT_DSP_MMU 28
244 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
246 # define OMAP_INT_1510_BT_MCSI1TX 16
247 # define OMAP_INT_1510_BT_MCSI1RX 17
248 # define OMAP_INT_1510_SoSSI_MATCH 19
249 # define OMAP_INT_1510_MEM_STICK 27
250 # define OMAP_INT_1510_COM_SPI_RO 31
253 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
255 # define OMAP_INT_310_FAC 0
256 # define OMAP_INT_310_USB_HHC_2 7
257 # define OMAP_INT_310_MCSI1_FE 16
258 # define OMAP_INT_310_MCSI2_FE 17
259 # define OMAP_INT_310_USB_W2FC_ISO 29
260 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
261 # define OMAP_INT_310_McBSP2RX_OF 31
264 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
266 # define OMAP_INT_1610_FAC 0
267 # define OMAP_INT_1610_USB_HHC_2 7
268 # define OMAP_INT_1610_USB_OTG 8
269 # define OMAP_INT_1610_SoSSI 9
270 # define OMAP_INT_1610_BT_MCSI1TX 16
271 # define OMAP_INT_1610_BT_MCSI1RX 17
272 # define OMAP_INT_1610_SoSSI_MATCH 19
273 # define OMAP_INT_1610_MEM_STICK 27
274 # define OMAP_INT_1610_McBSP2RX_OF 31
275 # define OMAP_INT_1610_STI 32
276 # define OMAP_INT_1610_STI_WAKEUP 33
277 # define OMAP_INT_1610_GPTIMER3 34
278 # define OMAP_INT_1610_GPTIMER4 35
279 # define OMAP_INT_1610_GPTIMER5 36
280 # define OMAP_INT_1610_GPTIMER6 37
281 # define OMAP_INT_1610_GPTIMER7 38
282 # define OMAP_INT_1610_GPTIMER8 39
283 # define OMAP_INT_1610_GPIO_BANK2 40
284 # define OMAP_INT_1610_GPIO_BANK3 41
285 # define OMAP_INT_1610_MMC2 42
286 # define OMAP_INT_1610_CF 43
287 # define OMAP_INT_1610_WAKE_UP_REQ 46
288 # define OMAP_INT_1610_GPIO_BANK4 48
289 # define OMAP_INT_1610_SPI 49
290 # define OMAP_INT_1610_DMA_CH6 53
291 # define OMAP_INT_1610_DMA_CH7 54
292 # define OMAP_INT_1610_DMA_CH8 55
293 # define OMAP_INT_1610_DMA_CH9 56
294 # define OMAP_INT_1610_DMA_CH10 57
295 # define OMAP_INT_1610_DMA_CH11 58
296 # define OMAP_INT_1610_DMA_CH12 59
297 # define OMAP_INT_1610_DMA_CH13 60
298 # define OMAP_INT_1610_DMA_CH14 61
299 # define OMAP_INT_1610_DMA_CH15 62
300 # define OMAP_INT_1610_NAND 63
303 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
305 # define OMAP_INT_730_HW_ERRORS 0
306 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
307 # define OMAP_INT_730_CFCD 2
308 # define OMAP_INT_730_CFIREQ 3
309 # define OMAP_INT_730_I2C 4
310 # define OMAP_INT_730_PCC 5
311 # define OMAP_INT_730_MPU_EXT_NIRQ 6
312 # define OMAP_INT_730_SPI_100K_1 7
313 # define OMAP_INT_730_SYREN_SPI 8
314 # define OMAP_INT_730_VLYNQ 9
315 # define OMAP_INT_730_GPIO_BANK4 10
316 # define OMAP_INT_730_McBSP1TX 11
317 # define OMAP_INT_730_McBSP1RX 12
318 # define OMAP_INT_730_McBSP1RX_OF 13
319 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
320 # define OMAP_INT_730_UART_MODEM_1 15
321 # define OMAP_INT_730_MCSI 16
322 # define OMAP_INT_730_uWireTX 17
323 # define OMAP_INT_730_uWireRX 18
324 # define OMAP_INT_730_SMC_CD 19
325 # define OMAP_INT_730_SMC_IREQ 20
326 # define OMAP_INT_730_HDQ_1WIRE 21
327 # define OMAP_INT_730_TIMER32K 22
328 # define OMAP_INT_730_MMC_SDIO 23
329 # define OMAP_INT_730_UPLD 24
330 # define OMAP_INT_730_USB_HHC_1 27
331 # define OMAP_INT_730_USB_HHC_2 28
332 # define OMAP_INT_730_USB_GENI 29
333 # define OMAP_INT_730_USB_OTG 30
334 # define OMAP_INT_730_CAMERA_IF 31
335 # define OMAP_INT_730_RNG 32
336 # define OMAP_INT_730_DUAL_MODE_TIMER 33
337 # define OMAP_INT_730_DBB_RF_EN 34
338 # define OMAP_INT_730_MPUIO_KEYPAD 35
339 # define OMAP_INT_730_SHA1_MD5 36
340 # define OMAP_INT_730_SPI_100K_2 37
341 # define OMAP_INT_730_RNG_IDLE 38
342 # define OMAP_INT_730_MPUIO 39
343 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
344 # define OMAP_INT_730_LLPC_OE_FALLING 41
345 # define OMAP_INT_730_LLPC_OE_RISING 42
346 # define OMAP_INT_730_LLPC_VSYNC 43
347 # define OMAP_INT_730_WAKE_UP_REQ 46
348 # define OMAP_INT_730_DMA_CH6 53
349 # define OMAP_INT_730_DMA_CH7 54
350 # define OMAP_INT_730_DMA_CH8 55
351 # define OMAP_INT_730_DMA_CH9 56
352 # define OMAP_INT_730_DMA_CH10 57
353 # define OMAP_INT_730_DMA_CH11 58
354 # define OMAP_INT_730_DMA_CH12 59
355 # define OMAP_INT_730_DMA_CH13 60
356 # define OMAP_INT_730_DMA_CH14 61
357 # define OMAP_INT_730_DMA_CH15 62
358 # define OMAP_INT_730_NAND 63
361 * OMAP-24xx common IRQ numbers
363 # define OMAP_INT_24XX_STI 4
364 # define OMAP_INT_24XX_SYS_NIRQ 7
365 # define OMAP_INT_24XX_L3_IRQ 10
366 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
367 # define OMAP_INT_24XX_SDMA_IRQ0 12
368 # define OMAP_INT_24XX_SDMA_IRQ1 13
369 # define OMAP_INT_24XX_SDMA_IRQ2 14
370 # define OMAP_INT_24XX_SDMA_IRQ3 15
371 # define OMAP_INT_243X_MCBSP2_IRQ 16
372 # define OMAP_INT_243X_MCBSP3_IRQ 17
373 # define OMAP_INT_243X_MCBSP4_IRQ 18
374 # define OMAP_INT_243X_MCBSP5_IRQ 19
375 # define OMAP_INT_24XX_GPMC_IRQ 20
376 # define OMAP_INT_24XX_GUFFAW_IRQ 21
377 # define OMAP_INT_24XX_IVA_IRQ 22
378 # define OMAP_INT_24XX_EAC_IRQ 23
379 # define OMAP_INT_24XX_CAM_IRQ 24
380 # define OMAP_INT_24XX_DSS_IRQ 25
381 # define OMAP_INT_24XX_MAIL_U0_MPU 26
382 # define OMAP_INT_24XX_DSP_UMA 27
383 # define OMAP_INT_24XX_DSP_MMU 28
384 # define OMAP_INT_24XX_GPIO_BANK1 29
385 # define OMAP_INT_24XX_GPIO_BANK2 30
386 # define OMAP_INT_24XX_GPIO_BANK3 31
387 # define OMAP_INT_24XX_GPIO_BANK4 32
388 # define OMAP_INT_243X_GPIO_BANK5 33
389 # define OMAP_INT_24XX_MAIL_U3_MPU 34
390 # define OMAP_INT_24XX_WDT3 35
391 # define OMAP_INT_24XX_WDT4 36
392 # define OMAP_INT_24XX_GPTIMER1 37
393 # define OMAP_INT_24XX_GPTIMER2 38
394 # define OMAP_INT_24XX_GPTIMER3 39
395 # define OMAP_INT_24XX_GPTIMER4 40
396 # define OMAP_INT_24XX_GPTIMER5 41
397 # define OMAP_INT_24XX_GPTIMER6 42
398 # define OMAP_INT_24XX_GPTIMER7 43
399 # define OMAP_INT_24XX_GPTIMER8 44
400 # define OMAP_INT_24XX_GPTIMER9 45
401 # define OMAP_INT_24XX_GPTIMER10 46
402 # define OMAP_INT_24XX_GPTIMER11 47
403 # define OMAP_INT_24XX_GPTIMER12 48
404 # define OMAP_INT_24XX_PKA_IRQ 50
405 # define OMAP_INT_24XX_SHA1MD5_IRQ 51
406 # define OMAP_INT_24XX_RNG_IRQ 52
407 # define OMAP_INT_24XX_MG_IRQ 53
408 # define OMAP_INT_24XX_I2C1_IRQ 56
409 # define OMAP_INT_24XX_I2C2_IRQ 57
410 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
411 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
412 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
413 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
414 # define OMAP_INT_243X_MCBSP1_IRQ 64
415 # define OMAP_INT_24XX_MCSPI1_IRQ 65
416 # define OMAP_INT_24XX_MCSPI2_IRQ 66
417 # define OMAP_INT_24XX_SSI1_IRQ0 67
418 # define OMAP_INT_24XX_SSI1_IRQ1 68
419 # define OMAP_INT_24XX_SSI2_IRQ0 69
420 # define OMAP_INT_24XX_SSI2_IRQ1 70
421 # define OMAP_INT_24XX_SSI_GDD_IRQ 71
422 # define OMAP_INT_24XX_UART1_IRQ 72
423 # define OMAP_INT_24XX_UART2_IRQ 73
424 # define OMAP_INT_24XX_UART3_IRQ 74
425 # define OMAP_INT_24XX_USB_IRQ_GEN 75
426 # define OMAP_INT_24XX_USB_IRQ_NISO 76
427 # define OMAP_INT_24XX_USB_IRQ_ISO 77
428 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
429 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
430 # define OMAP_INT_24XX_USB_IRQ_OTG 80
431 # define OMAP_INT_24XX_VLYNQ_IRQ 81
432 # define OMAP_INT_24XX_MMC_IRQ 83
433 # define OMAP_INT_24XX_MS_IRQ 84
434 # define OMAP_INT_24XX_FAC_IRQ 85
435 # define OMAP_INT_24XX_MCSPI3_IRQ 91
436 # define OMAP_INT_243X_HS_USB_MC 92
437 # define OMAP_INT_243X_HS_USB_DMA 93
438 # define OMAP_INT_243X_CARKIT 94
439 # define OMAP_INT_34XX_GPTIMER12 95
442 enum omap_dma_model
{
450 struct soc_dma_s
*omap_dma_init(target_phys_addr_t base
, qemu_irq
*irqs
,
451 qemu_irq lcd_irq
, struct omap_mpu_state_s
*mpu
, omap_clk clk
,
452 enum omap_dma_model model
);
453 struct soc_dma_s
*omap_dma4_init(target_phys_addr_t base
, qemu_irq
*irqs
,
454 struct omap_mpu_state_s
*mpu
, int fifo
,
455 int chans
, omap_clk iclk
, omap_clk fclk
);
456 void omap_dma_reset(struct soc_dma_s
*s
);
463 /* Only used in OMAP DMA 3.x gigacells */
467 imif
, /* omap16xx: ocp_t1 */
469 local
, /* omap16xx: ocp_t2 */
471 __omap_dma_port_last
,
479 } omap_dma_addressing_t
;
481 /* Only used in OMAP DMA 3.x gigacells */
482 struct omap_dma_lcd_channel_s
{
483 enum omap_dma_port src
;
484 target_phys_addr_t src_f1_top
;
485 target_phys_addr_t src_f1_bottom
;
486 target_phys_addr_t src_f2_top
;
487 target_phys_addr_t src_f2_bottom
;
489 /* Used in OMAP DMA 3.2 gigacell */
490 unsigned char brust_f1
;
491 unsigned char pack_f1
;
492 unsigned char data_type_f1
;
493 unsigned char brust_f2
;
494 unsigned char pack_f2
;
495 unsigned char data_type_f2
;
496 unsigned char end_prog
;
497 unsigned char repeat
;
498 unsigned char auto_init
;
499 unsigned char priority
;
501 unsigned char running
;
503 unsigned char omap_3_1_compatible_disable
;
505 unsigned char lch_type
;
506 int16_t element_index_f1
;
507 int16_t element_index_f2
;
508 int32_t frame_index_f1
;
509 int32_t frame_index_f2
;
510 uint16_t elements_f1
;
512 uint16_t elements_f2
;
514 omap_dma_addressing_t mode_f1
;
515 omap_dma_addressing_t mode_f2
;
517 /* Destination port is fixed. */
523 target_phys_addr_t phys_framebuffer
[2];
525 struct omap_mpu_state_s
*mpu
;
526 } *omap_dma_get_lcdch(struct soc_dma_s
*s
);
529 * DMA request numbers for OMAP1
530 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
532 # define OMAP_DMA_NO_DEVICE 0
533 # define OMAP_DMA_MCSI1_TX 1
534 # define OMAP_DMA_MCSI1_RX 2
535 # define OMAP_DMA_I2C_RX 3
536 # define OMAP_DMA_I2C_TX 4
537 # define OMAP_DMA_EXT_NDMA_REQ0 5
538 # define OMAP_DMA_EXT_NDMA_REQ1 6
539 # define OMAP_DMA_UWIRE_TX 7
540 # define OMAP_DMA_MCBSP1_TX 8
541 # define OMAP_DMA_MCBSP1_RX 9
542 # define OMAP_DMA_MCBSP3_TX 10
543 # define OMAP_DMA_MCBSP3_RX 11
544 # define OMAP_DMA_UART1_TX 12
545 # define OMAP_DMA_UART1_RX 13
546 # define OMAP_DMA_UART2_TX 14
547 # define OMAP_DMA_UART2_RX 15
548 # define OMAP_DMA_MCBSP2_TX 16
549 # define OMAP_DMA_MCBSP2_RX 17
550 # define OMAP_DMA_UART3_TX 18
551 # define OMAP_DMA_UART3_RX 19
552 # define OMAP_DMA_CAMERA_IF_RX 20
553 # define OMAP_DMA_MMC_TX 21
554 # define OMAP_DMA_MMC_RX 22
555 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
556 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
557 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
558 # define OMAP_DMA_USB_W2FC_RX0 26
559 # define OMAP_DMA_USB_W2FC_RX1 27
560 # define OMAP_DMA_USB_W2FC_RX2 28
561 # define OMAP_DMA_USB_W2FC_TX0 29
562 # define OMAP_DMA_USB_W2FC_TX1 30
563 # define OMAP_DMA_USB_W2FC_TX2 31
565 /* These are only for 1610 */
566 # define OMAP_DMA_CRYPTO_DES_IN 32
567 # define OMAP_DMA_SPI_TX 33
568 # define OMAP_DMA_SPI_RX 34
569 # define OMAP_DMA_CRYPTO_HASH 35
570 # define OMAP_DMA_CCP_ATTN 36
571 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
572 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
573 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
574 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
575 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
576 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
577 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
578 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
579 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
580 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
581 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
582 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
583 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
584 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
585 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
586 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
587 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
588 # define OMAP_DMA_MMC2_TX 54
589 # define OMAP_DMA_MMC2_RX 55
590 # define OMAP_DMA_CRYPTO_DES_OUT 56
593 * DMA request numbers for the OMAP2
595 # define OMAP24XX_DMA_NO_DEVICE 0
596 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
597 # define OMAP24XX_DMA_EXT_DMAREQ0 2
598 # define OMAP24XX_DMA_EXT_DMAREQ1 3
599 # define OMAP24XX_DMA_GPMC 4
600 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
601 # define OMAP24XX_DMA_DSS 6
602 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
603 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
604 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
605 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
606 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
607 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
608 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
609 # define OMAP24XX_DMA_EXT_DMAREQ2 14
610 # define OMAP24XX_DMA_EXT_DMAREQ3 15
611 # define OMAP24XX_DMA_EXT_DMAREQ4 16
612 # define OMAP24XX_DMA_EAC_AC_RD 17
613 # define OMAP24XX_DMA_EAC_AC_WR 18
614 # define OMAP24XX_DMA_EAC_MD_UL_RD 19
615 # define OMAP24XX_DMA_EAC_MD_UL_WR 20
616 # define OMAP24XX_DMA_EAC_MD_DL_RD 21
617 # define OMAP24XX_DMA_EAC_MD_DL_WR 22
618 # define OMAP24XX_DMA_EAC_BT_UL_RD 23
619 # define OMAP24XX_DMA_EAC_BT_UL_WR 24
620 # define OMAP24XX_DMA_EAC_BT_DL_RD 25
621 # define OMAP24XX_DMA_EAC_BT_DL_WR 26
622 # define OMAP24XX_DMA_I2C1_TX 27
623 # define OMAP24XX_DMA_I2C1_RX 28
624 # define OMAP24XX_DMA_I2C2_TX 29
625 # define OMAP24XX_DMA_I2C2_RX 30
626 # define OMAP24XX_DMA_MCBSP1_TX 31
627 # define OMAP24XX_DMA_MCBSP1_RX 32
628 # define OMAP24XX_DMA_MCBSP2_TX 33
629 # define OMAP24XX_DMA_MCBSP2_RX 34
630 # define OMAP24XX_DMA_SPI1_TX0 35
631 # define OMAP24XX_DMA_SPI1_RX0 36
632 # define OMAP24XX_DMA_SPI1_TX1 37
633 # define OMAP24XX_DMA_SPI1_RX1 38
634 # define OMAP24XX_DMA_SPI1_TX2 39
635 # define OMAP24XX_DMA_SPI1_RX2 40
636 # define OMAP24XX_DMA_SPI1_TX3 41
637 # define OMAP24XX_DMA_SPI1_RX3 42
638 # define OMAP24XX_DMA_SPI2_TX0 43
639 # define OMAP24XX_DMA_SPI2_RX0 44
640 # define OMAP24XX_DMA_SPI2_TX1 45
641 # define OMAP24XX_DMA_SPI2_RX1 46
643 # define OMAP24XX_DMA_UART1_TX 49
644 # define OMAP24XX_DMA_UART1_RX 50
645 # define OMAP24XX_DMA_UART2_TX 51
646 # define OMAP24XX_DMA_UART2_RX 52
647 # define OMAP24XX_DMA_UART3_TX 53
648 # define OMAP24XX_DMA_UART3_RX 54
649 # define OMAP24XX_DMA_USB_W2FC_TX0 55
650 # define OMAP24XX_DMA_USB_W2FC_RX0 56
651 # define OMAP24XX_DMA_USB_W2FC_TX1 57
652 # define OMAP24XX_DMA_USB_W2FC_RX1 58
653 # define OMAP24XX_DMA_USB_W2FC_TX2 59
654 # define OMAP24XX_DMA_USB_W2FC_RX2 60
655 # define OMAP24XX_DMA_MMC1_TX 61
656 # define OMAP24XX_DMA_MMC1_RX 62
657 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
658 # define OMAP24XX_DMA_EXT_DMAREQ5 64
661 struct omap_mpu_timer_s
;
662 struct omap_mpu_timer_s
*omap_mpu_timer_init(target_phys_addr_t base
,
663 qemu_irq irq
, omap_clk clk
);
666 struct omap_gp_timer_s
;
667 struct omap_gp_timer_s
*omap_gp_timer_init(struct omap_target_agent_s
*ta
,
668 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
);
669 void omap_gp_timer_reset(struct omap_gp_timer_s
*s
);
671 struct omap_watchdog_timer_s
;
672 struct omap_watchdog_timer_s
*omap_wd_timer_init(target_phys_addr_t base
,
673 qemu_irq irq
, omap_clk clk
);
675 struct omap_32khz_timer_s
;
676 struct omap_32khz_timer_s
*omap_os_timer_init(target_phys_addr_t base
,
677 qemu_irq irq
, omap_clk clk
);
679 /* OMAP2 sysctimer */
680 struct omap_synctimer_s
;
681 struct omap_synctimer_s
*omap_synctimer_init(struct omap_target_agent_s
*ta
,
682 struct omap_mpu_state_s
*mpu
, omap_clk fclk
, omap_clk iclk
);
683 void omap_synctimer_reset(struct omap_synctimer_s
*s
);
685 struct omap_tipb_bridge_s
;
686 struct omap_tipb_bridge_s
*omap_tipb_bridge_init(target_phys_addr_t base
,
687 qemu_irq abort_irq
, omap_clk clk
);
690 struct omap_uart_s
*omap_uart_init(target_phys_addr_t base
,
691 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
692 qemu_irq txdma
, qemu_irq rxdma
, CharDriverState
*chr
);
693 struct omap_uart_s
*omap2_uart_init(struct omap_target_agent_s
*ta
,
694 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
695 qemu_irq txdma
, qemu_irq rxdma
, CharDriverState
*chr
);
696 void omap_uart_reset(struct omap_uart_s
*s
);
697 void omap_uart_attach(struct omap_uart_s
*s
, CharDriverState
*chr
);
700 struct omap_mpuio_s
*omap_mpuio_init(target_phys_addr_t base
,
701 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
703 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
);
704 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
);
705 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
);
707 /* omap1 gpio module interface */
709 struct omap_gpio_s
*omap_gpio_init(target_phys_addr_t base
,
710 qemu_irq irq
, omap_clk clk
);
711 void omap_gpio_reset(struct omap_gpio_s
*s
);
712 qemu_irq
*omap_gpio_in_get(struct omap_gpio_s
*s
);
713 void omap_gpio_out_set(struct omap_gpio_s
*s
, int line
, qemu_irq handler
);
715 /* omap2 gpio interface */
717 struct omap_gpif_s
*omap2_gpio_init(struct omap_target_agent_s
*ta
,
718 qemu_irq
*irq
, omap_clk
*fclk
, omap_clk iclk
, int modules
);
719 void omap_gpif_reset(struct omap_gpif_s
*s
);
720 qemu_irq
*omap2_gpio_in_get(struct omap_gpif_s
*s
, int start
);
721 void omap2_gpio_out_set(struct omap_gpif_s
*s
, int line
, qemu_irq handler
);
724 uint16_t (*receive
)(void *opaque
);
725 void (*send
)(void *opaque
, uint16_t data
);
729 struct omap_uwire_s
*omap_uwire_init(target_phys_addr_t base
,
730 qemu_irq
*irq
, qemu_irq dma
, omap_clk clk
);
731 void omap_uwire_attach(struct omap_uwire_s
*s
,
732 uWireSlave
*slave
, int chipselect
);
736 struct omap_mcspi_s
*omap_mcspi_init(struct omap_target_agent_s
*ta
, int chnum
,
737 qemu_irq irq
, qemu_irq
*drq
, omap_clk fclk
, omap_clk iclk
);
738 void omap_mcspi_attach(struct omap_mcspi_s
*s
,
739 uint32_t (*txrx
)(void *opaque
, uint32_t, int), void *opaque
,
741 void omap_mcspi_reset(struct omap_mcspi_s
*s
);
744 struct omap_rtc_s
*omap_rtc_init(target_phys_addr_t base
,
745 qemu_irq
*irq
, omap_clk clk
);
750 /* The CPU can call this if it is generating the clock signal on the
751 * i2s port. The CODEC can ignore it if it is set up as a clock
752 * master and generates its own clock. */
753 void (*set_rate
)(void *opaque
, int in
, int out
);
755 void (*tx_swallow
)(void *opaque
);
772 struct omap_mcbsp_s
*omap_mcbsp_init(target_phys_addr_t base
,
773 qemu_irq
*irq
, qemu_irq
*dma
, omap_clk clk
);
774 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s
*s
, I2SCodec
*slave
);
777 struct omap_lpg_s
*omap_lpg_init(target_phys_addr_t base
, omap_clk clk
);
779 void omap_tap_init(struct omap_target_agent_s
*ta
,
780 struct omap_mpu_state_s
*mpu
);
783 struct omap_eac_s
*omap_eac_init(struct omap_target_agent_s
*ta
,
784 qemu_irq irq
, qemu_irq
*drq
, omap_clk fclk
, omap_clk iclk
);
787 struct omap_lcd_panel_s
;
788 void omap_lcdc_reset(struct omap_lcd_panel_s
*s
);
789 struct omap_lcd_panel_s
*omap_lcdc_init(target_phys_addr_t base
, qemu_irq irq
,
790 struct omap_dma_lcd_channel_s
*dma
,
791 ram_addr_t imif_base
, ram_addr_t emiff_base
, omap_clk clk
);
796 void (*write
)(void *opaque
, int dc
, uint16_t value
);
797 void (*block
)(void *opaque
, int dc
, void *buf
, size_t len
, int pitch
);
798 uint16_t (*read
)(void *opaque
, int dc
);
801 void omap_dss_reset(struct omap_dss_s
*s
);
802 struct omap_dss_s
*omap_dss_init(struct omap_target_agent_s
*ta
,
803 target_phys_addr_t l3_base
,
804 qemu_irq irq
, qemu_irq drq
,
805 omap_clk fck1
, omap_clk fck2
, omap_clk ck54m
,
806 omap_clk ick1
, omap_clk ick2
);
807 void omap_rfbi_attach(struct omap_dss_s
*s
, int cs
, struct rfbi_chip_s
*chip
);
811 struct omap_mmc_s
*omap_mmc_init(target_phys_addr_t base
,
812 BlockDriverState
*bd
,
813 qemu_irq irq
, qemu_irq dma
[], omap_clk clk
);
814 struct omap_mmc_s
*omap2_mmc_init(struct omap_target_agent_s
*ta
,
815 BlockDriverState
*bd
, qemu_irq irq
, qemu_irq dma
[],
816 omap_clk fclk
, omap_clk iclk
);
817 void omap_mmc_reset(struct omap_mmc_s
*s
);
818 void omap_mmc_handlers(struct omap_mmc_s
*s
, qemu_irq ro
, qemu_irq cover
);
819 void omap_mmc_enable(struct omap_mmc_s
*s
, int enable
);
823 struct omap_i2c_s
*omap_i2c_init(target_phys_addr_t base
,
824 qemu_irq irq
, qemu_irq
*dma
, omap_clk clk
);
825 struct omap_i2c_s
*omap2_i2c_init(struct omap_target_agent_s
*ta
,
826 qemu_irq irq
, qemu_irq
*dma
, omap_clk fclk
, omap_clk iclk
);
827 void omap_i2c_reset(struct omap_i2c_s
*s
);
828 i2c_bus
*omap_i2c_bus(struct omap_i2c_s
*s
);
830 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
831 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
832 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
833 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
834 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
835 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
836 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
837 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
839 # define cpu_is_omap15xx(cpu) \
840 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
841 # define cpu_is_omap16xx(cpu) \
842 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
843 # define cpu_is_omap24xx(cpu) \
844 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
846 # define cpu_class_omap1(cpu) \
847 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
848 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
849 # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
851 struct omap_mpu_state_s
{
852 enum omap_mpu_model
{
872 struct omap_dma_port_if_s
{
873 uint32_t (*read
[3])(struct omap_mpu_state_s
*s
,
874 target_phys_addr_t offset
);
875 void (*write
[3])(struct omap_mpu_state_s
*s
,
876 target_phys_addr_t offset
, uint32_t value
);
877 int (*addr_valid
)(struct omap_mpu_state_s
*s
,
878 target_phys_addr_t addr
);
879 } port
[__omap_dma_port_last
];
881 unsigned long sdram_size
;
882 unsigned long sram_size
;
884 /* MPUI-TIPB peripherals */
885 struct omap_uart_s
*uart
[3];
887 struct omap_gpio_s
*gpio
;
889 struct omap_mcbsp_s
*mcbsp1
;
890 struct omap_mcbsp_s
*mcbsp3
;
892 /* MPU public TIPB peripherals */
893 struct omap_32khz_timer_s
*os_timer
;
895 struct omap_mmc_s
*mmc
;
897 struct omap_mpuio_s
*mpuio
;
899 struct omap_uwire_s
*microwire
;
915 struct omap_i2c_s
*i2c
[2];
917 struct omap_rtc_s
*rtc
;
919 struct omap_mcbsp_s
*mcbsp2
;
921 struct omap_lpg_s
*led
[2];
923 /* MPU private TIPB peripherals */
924 struct omap_intr_handler_s
*ih
[2];
926 struct soc_dma_s
*dma
;
928 struct omap_mpu_timer_s
*timer
[3];
929 struct omap_watchdog_timer_s
*wdt
;
931 struct omap_lcd_panel_s
*lcd
;
933 uint32_t ulpd_pm_regs
[21];
934 int64_t ulpd_gauge_start
;
936 uint32_t func_mux_ctrl
[14];
937 uint32_t comp_mode_ctrl
[1];
938 uint32_t pull_dwn_ctrl
[4];
939 uint32_t gate_inh_ctrl
[1];
940 uint32_t voltage_ctrl
[1];
941 uint32_t test_dbg_ctrl
[1];
942 uint32_t mod_conf_ctrl
[1];
947 struct omap_tipb_bridge_s
*private_tipb
;
948 struct omap_tipb_bridge_s
*public_tipb
;
950 uint32_t tcmi_regs
[17];
962 uint16_t arm_idlect1
;
963 uint16_t arm_idlect2
;
969 uint16_t dsp_idlect1
;
970 uint16_t dsp_idlect2
;
974 /* OMAP2-only peripherals */
975 struct omap_l4_s
*l4
;
977 struct omap_gp_timer_s
*gptimer
[12];
978 struct omap_synctimer_s
*synctimer
;
980 struct omap_prcm_s
*prcm
;
981 struct omap_sdrc_s
*sdrc
;
982 struct omap_gpmc_s
*gpmc
;
983 struct omap_sysctl_s
*sysc
;
985 struct omap_gpif_s
*gpif
;
987 struct omap_mcspi_s
*mcspi
[2];
989 struct omap_dss_s
*dss
;
991 struct omap_eac_s
*eac
;
995 struct omap_mpu_state_s
*omap310_mpu_init(unsigned long sdram_size
,
999 struct omap_mpu_state_s
*omap2420_mpu_init(unsigned long sdram_size
,
1002 # if TARGET_PHYS_ADDR_BITS == 32
1003 # define OMAP_FMT_plx "%#08x"
1004 # elif TARGET_PHYS_ADDR_BITS == 64
1005 # define OMAP_FMT_plx "%#08" PRIx64
1007 # error TARGET_PHYS_ADDR_BITS undefined
1010 uint32_t omap_badwidth_read8(void *opaque
, target_phys_addr_t addr
);
1011 void omap_badwidth_write8(void *opaque
, target_phys_addr_t addr
,
1013 uint32_t omap_badwidth_read16(void *opaque
, target_phys_addr_t addr
);
1014 void omap_badwidth_write16(void *opaque
, target_phys_addr_t addr
,
1016 uint32_t omap_badwidth_read32(void *opaque
, target_phys_addr_t addr
);
1017 void omap_badwidth_write32(void *opaque
, target_phys_addr_t addr
,
1020 void omap_mpu_wakeup(void *opaque
, int irq
, int req
);
1022 # define OMAP_BAD_REG(paddr) \
1023 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
1024 __FUNCTION__, paddr)
1025 # define OMAP_RO_REG(paddr) \
1026 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1027 __FUNCTION__, paddr)
1029 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
1030 (Board-specifc tags are not here) */
1031 #define OMAP_TAG_CLOCK 0x4f01
1032 #define OMAP_TAG_MMC 0x4f02
1033 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1034 #define OMAP_TAG_USB 0x4f04
1035 #define OMAP_TAG_LCD 0x4f05
1036 #define OMAP_TAG_GPIO_SWITCH 0x4f06
1037 #define OMAP_TAG_UART 0x4f07
1038 #define OMAP_TAG_FBMEM 0x4f08
1039 #define OMAP_TAG_STI_CONSOLE 0x4f09
1040 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
1041 #define OMAP_TAG_PARTITION 0x4f0b
1042 #define OMAP_TAG_TEA5761 0x4f10
1043 #define OMAP_TAG_TMP105 0x4f11
1044 #define OMAP_TAG_BOOT_REASON 0x4f80
1045 #define OMAP_TAG_FLASH_PART_STR 0x4f81
1046 #define OMAP_TAG_VERSION_STR 0x4f82
1049 OMAP_GPIOSW_TYPE_COVER
= 0 << 4,
1050 OMAP_GPIOSW_TYPE_CONNECTION
= 1 << 4,
1051 OMAP_GPIOSW_TYPE_ACTIVITY
= 2 << 4,
1054 #define OMAP_GPIOSW_INVERTED 0x0001
1055 #define OMAP_GPIOSW_OUTPUT 0x0002
1057 # define TCMI_VERBOSE 1
1058 //# define MEM_VERBOSE 1
1060 # ifdef TCMI_VERBOSE
1061 # define OMAP_8B_REG(paddr) \
1062 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1063 __FUNCTION__, paddr)
1064 # define OMAP_16B_REG(paddr) \
1065 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1066 __FUNCTION__, paddr)
1067 # define OMAP_32B_REG(paddr) \
1068 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1069 __FUNCTION__, paddr)
1071 # define OMAP_8B_REG(paddr)
1072 # define OMAP_16B_REG(paddr)
1073 # define OMAP_32B_REG(paddr)
1076 # define OMAP_MPUI_REG_MASK 0x000007ff
1080 CPUReadMemoryFunc
* const *mem_read
;
1081 CPUWriteMemoryFunc
* const *mem_write
;
1086 static uint32_t io_readb(void *opaque
, target_phys_addr_t addr
)
1088 struct io_fn
*s
= opaque
;
1092 ret
= s
->mem_read
[0](s
->opaque
, addr
);
1095 fprintf(stderr
, "%08x ---> %02x\n", (uint32_t) addr
, ret
);
1098 static uint32_t io_readh(void *opaque
, target_phys_addr_t addr
)
1100 struct io_fn
*s
= opaque
;
1104 ret
= s
->mem_read
[1](s
->opaque
, addr
);
1107 fprintf(stderr
, "%08x ---> %04x\n", (uint32_t) addr
, ret
);
1110 static uint32_t io_readw(void *opaque
, target_phys_addr_t addr
)
1112 struct io_fn
*s
= opaque
;
1116 ret
= s
->mem_read
[2](s
->opaque
, addr
);
1119 fprintf(stderr
, "%08x ---> %08x\n", (uint32_t) addr
, ret
);
1122 static void io_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1124 struct io_fn
*s
= opaque
;
1127 fprintf(stderr
, "%08x <--- %02x\n", (uint32_t) addr
, value
);
1129 s
->mem_write
[0](s
->opaque
, addr
, value
);
1132 static void io_writeh(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1134 struct io_fn
*s
= opaque
;
1137 fprintf(stderr
, "%08x <--- %04x\n", (uint32_t) addr
, value
);
1139 s
->mem_write
[1](s
->opaque
, addr
, value
);
1142 static void io_writew(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1144 struct io_fn
*s
= opaque
;
1147 fprintf(stderr
, "%08x <--- %08x\n", (uint32_t) addr
, value
);
1149 s
->mem_write
[2](s
->opaque
, addr
, value
);
1153 static CPUReadMemoryFunc
* const io_readfn
[] = { io_readb
, io_readh
, io_readw
, };
1154 static CPUWriteMemoryFunc
* const io_writefn
[] = { io_writeb
, io_writeh
, io_writew
, };
1156 inline static int debug_register_io_memory(CPUReadMemoryFunc
* const *mem_read
,
1157 CPUWriteMemoryFunc
* const *mem_write
,
1160 struct io_fn
*s
= qemu_malloc(sizeof(struct io_fn
));
1162 s
->mem_read
= mem_read
;
1163 s
->mem_write
= mem_write
;
1166 return cpu_register_io_memory(io_readfn
, io_writefn
, s
);
1168 # define cpu_register_io_memory debug_register_io_memory
1171 /* Define when we want to reduce the number of IO regions registered. */
1172 /*# define L4_MUX_HACK*/
1174 #endif /* hw_omap_h */