2 * Texas Instruments OMAP processors.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 # define hw_omap_h "omap.h"
23 # define OMAP_EMIFS_BASE 0x00000000
24 # define OMAP2_Q0_BASE 0x00000000
25 # define OMAP_CS0_BASE 0x00000000
26 # define OMAP_CS1_BASE 0x04000000
27 # define OMAP_CS2_BASE 0x08000000
28 # define OMAP_CS3_BASE 0x0c000000
29 # define OMAP_EMIFF_BASE 0x10000000
30 # define OMAP_IMIF_BASE 0x20000000
31 # define OMAP_LOCALBUS_BASE 0x30000000
32 # define OMAP2_Q1_BASE 0x40000000
33 # define OMAP2_L4_BASE 0x48000000
34 # define OMAP2_SRAM_BASE 0x40200000
35 # define OMAP2_L3_BASE 0x68000000
36 # define OMAP2_Q2_BASE 0x80000000
37 # define OMAP2_Q3_BASE 0xc0000000
38 # define OMAP_MPUI_BASE 0xe1000000
40 # define OMAP730_SRAM_SIZE 0x00032000
41 # define OMAP15XX_SRAM_SIZE 0x00030000
42 # define OMAP16XX_SRAM_SIZE 0x00004000
43 # define OMAP1611_SRAM_SIZE 0x0003e800
44 # define OMAP242X_SRAM_SIZE 0x000a0000
45 # define OMAP243X_SRAM_SIZE 0x00010000
46 # define OMAP_CS0_SIZE 0x04000000
47 # define OMAP_CS1_SIZE 0x04000000
48 # define OMAP_CS2_SIZE 0x04000000
49 # define OMAP_CS3_SIZE 0x04000000
52 struct omap_mpu_state_s
;
53 typedef struct clk
*omap_clk
;
54 omap_clk
omap_findclk(struct omap_mpu_state_s
*mpu
, const char *name
);
55 void omap_clk_init(struct omap_mpu_state_s
*mpu
);
56 void omap_clk_adduser(struct clk
*clk
, qemu_irq user
);
57 void omap_clk_get(omap_clk clk
);
58 void omap_clk_put(omap_clk clk
);
59 void omap_clk_onoff(omap_clk clk
, int on
);
60 void omap_clk_canidle(omap_clk clk
, int can
);
61 void omap_clk_setrate(omap_clk clk
, int divide
, int multiply
);
62 int64_t omap_clk_getrate(omap_clk clk
);
63 void omap_clk_reparent(omap_clk clk
, omap_clk parent
);
65 /* OMAP2 l4 Interconnect */
67 struct omap_l4_region_s
{
68 target_phys_addr_t offset
;
72 struct omap_l4_agent_info_s
{
78 struct omap_target_agent_s
{
79 struct omap_l4_s
*bus
;
81 const struct omap_l4_region_s
*start
;
82 target_phys_addr_t base
;
87 struct omap_l4_s
*omap_l4_init(target_phys_addr_t base
, int ta_num
);
89 struct omap_target_agent_s
;
90 struct omap_target_agent_s
*omap_l4ta_get(
91 struct omap_l4_s
*bus
,
92 const struct omap_l4_region_s
*regions
,
93 const struct omap_l4_agent_info_s
*agents
,
95 target_phys_addr_t
omap_l4_attach(struct omap_target_agent_s
*ta
, int region
,
97 target_phys_addr_t
omap_l4_region_base(struct omap_target_agent_s
*ta
,
99 int l4_register_io_memory(CPUReadMemoryFunc
* const *mem_read
,
100 CPUWriteMemoryFunc
* const *mem_write
, void *opaque
);
102 /* OMAP interrupt controller */
103 struct omap_intr_handler_s
;
104 struct omap_intr_handler_s
*omap_inth_init(target_phys_addr_t base
,
105 unsigned long size
, unsigned char nbanks
, qemu_irq
**pins
,
106 qemu_irq parent_irq
, qemu_irq parent_fiq
, omap_clk clk
);
107 struct omap_intr_handler_s
*omap2_inth_init(target_phys_addr_t base
,
108 int size
, int nbanks
, qemu_irq
**pins
,
109 qemu_irq parent_irq
, qemu_irq parent_fiq
,
110 omap_clk fclk
, omap_clk iclk
);
111 void omap_inth_reset(struct omap_intr_handler_s
*s
);
112 qemu_irq
omap_inth_get_pin(struct omap_intr_handler_s
*s
, int n
);
114 /* OMAP2 SDRAM controller */
116 struct omap_sdrc_s
*omap_sdrc_init(target_phys_addr_t base
);
117 void omap_sdrc_reset(struct omap_sdrc_s
*s
);
119 /* OMAP2 general purpose memory controller */
121 struct omap_gpmc_s
*omap_gpmc_init(target_phys_addr_t base
, qemu_irq irq
);
122 void omap_gpmc_reset(struct omap_gpmc_s
*s
);
123 void omap_gpmc_attach(struct omap_gpmc_s
*s
, int cs
, MemoryRegion
*iomem
);
126 * Common IRQ numbers for level 1 interrupt handler
127 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
129 # define OMAP_INT_CAMERA 1
130 # define OMAP_INT_FIQ 3
131 # define OMAP_INT_RTDX 6
132 # define OMAP_INT_DSP_MMU_ABORT 7
133 # define OMAP_INT_HOST 8
134 # define OMAP_INT_ABORT 9
135 # define OMAP_INT_BRIDGE_PRIV 13
136 # define OMAP_INT_GPIO_BANK1 14
137 # define OMAP_INT_UART3 15
138 # define OMAP_INT_TIMER3 16
139 # define OMAP_INT_DMA_CH0_6 19
140 # define OMAP_INT_DMA_CH1_7 20
141 # define OMAP_INT_DMA_CH2_8 21
142 # define OMAP_INT_DMA_CH3 22
143 # define OMAP_INT_DMA_CH4 23
144 # define OMAP_INT_DMA_CH5 24
145 # define OMAP_INT_DMA_LCD 25
146 # define OMAP_INT_TIMER1 26
147 # define OMAP_INT_WD_TIMER 27
148 # define OMAP_INT_BRIDGE_PUB 28
149 # define OMAP_INT_TIMER2 30
150 # define OMAP_INT_LCD_CTRL 31
153 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
155 # define OMAP_INT_15XX_IH2_IRQ 0
156 # define OMAP_INT_15XX_LB_MMU 17
157 # define OMAP_INT_15XX_LOCAL_BUS 29
160 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
162 # define OMAP_INT_1510_SPI_TX 4
163 # define OMAP_INT_1510_SPI_RX 5
164 # define OMAP_INT_1510_DSP_MAILBOX1 10
165 # define OMAP_INT_1510_DSP_MAILBOX2 11
168 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
170 # define OMAP_INT_310_McBSP2_TX 4
171 # define OMAP_INT_310_McBSP2_RX 5
172 # define OMAP_INT_310_HSB_MAILBOX1 12
173 # define OMAP_INT_310_HSAB_MMU 18
176 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
178 # define OMAP_INT_1610_IH2_IRQ 0
179 # define OMAP_INT_1610_IH2_FIQ 2
180 # define OMAP_INT_1610_McBSP2_TX 4
181 # define OMAP_INT_1610_McBSP2_RX 5
182 # define OMAP_INT_1610_DSP_MAILBOX1 10
183 # define OMAP_INT_1610_DSP_MAILBOX2 11
184 # define OMAP_INT_1610_LCD_LINE 12
185 # define OMAP_INT_1610_GPTIMER1 17
186 # define OMAP_INT_1610_GPTIMER2 18
187 # define OMAP_INT_1610_SSR_FIFO_0 29
190 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
192 # define OMAP_INT_730_IH2_FIQ 0
193 # define OMAP_INT_730_IH2_IRQ 1
194 # define OMAP_INT_730_USB_NON_ISO 2
195 # define OMAP_INT_730_USB_ISO 3
196 # define OMAP_INT_730_ICR 4
197 # define OMAP_INT_730_EAC 5
198 # define OMAP_INT_730_GPIO_BANK1 6
199 # define OMAP_INT_730_GPIO_BANK2 7
200 # define OMAP_INT_730_GPIO_BANK3 8
201 # define OMAP_INT_730_McBSP2TX 10
202 # define OMAP_INT_730_McBSP2RX 11
203 # define OMAP_INT_730_McBSP2RX_OVF 12
204 # define OMAP_INT_730_LCD_LINE 14
205 # define OMAP_INT_730_GSM_PROTECT 15
206 # define OMAP_INT_730_TIMER3 16
207 # define OMAP_INT_730_GPIO_BANK5 17
208 # define OMAP_INT_730_GPIO_BANK6 18
209 # define OMAP_INT_730_SPGIO_WR 29
212 * Common IRQ numbers for level 2 interrupt handler
214 # define OMAP_INT_KEYBOARD 1
215 # define OMAP_INT_uWireTX 2
216 # define OMAP_INT_uWireRX 3
217 # define OMAP_INT_I2C 4
218 # define OMAP_INT_MPUIO 5
219 # define OMAP_INT_USB_HHC_1 6
220 # define OMAP_INT_McBSP3TX 10
221 # define OMAP_INT_McBSP3RX 11
222 # define OMAP_INT_McBSP1TX 12
223 # define OMAP_INT_McBSP1RX 13
224 # define OMAP_INT_UART1 14
225 # define OMAP_INT_UART2 15
226 # define OMAP_INT_USB_W2FC 20
227 # define OMAP_INT_1WIRE 21
228 # define OMAP_INT_OS_TIMER 22
229 # define OMAP_INT_OQN 23
230 # define OMAP_INT_GAUGE_32K 24
231 # define OMAP_INT_RTC_TIMER 25
232 # define OMAP_INT_RTC_ALARM 26
233 # define OMAP_INT_DSP_MMU 28
236 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
238 # define OMAP_INT_1510_BT_MCSI1TX 16
239 # define OMAP_INT_1510_BT_MCSI1RX 17
240 # define OMAP_INT_1510_SoSSI_MATCH 19
241 # define OMAP_INT_1510_MEM_STICK 27
242 # define OMAP_INT_1510_COM_SPI_RO 31
245 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
247 # define OMAP_INT_310_FAC 0
248 # define OMAP_INT_310_USB_HHC_2 7
249 # define OMAP_INT_310_MCSI1_FE 16
250 # define OMAP_INT_310_MCSI2_FE 17
251 # define OMAP_INT_310_USB_W2FC_ISO 29
252 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
253 # define OMAP_INT_310_McBSP2RX_OF 31
256 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
258 # define OMAP_INT_1610_FAC 0
259 # define OMAP_INT_1610_USB_HHC_2 7
260 # define OMAP_INT_1610_USB_OTG 8
261 # define OMAP_INT_1610_SoSSI 9
262 # define OMAP_INT_1610_BT_MCSI1TX 16
263 # define OMAP_INT_1610_BT_MCSI1RX 17
264 # define OMAP_INT_1610_SoSSI_MATCH 19
265 # define OMAP_INT_1610_MEM_STICK 27
266 # define OMAP_INT_1610_McBSP2RX_OF 31
267 # define OMAP_INT_1610_STI 32
268 # define OMAP_INT_1610_STI_WAKEUP 33
269 # define OMAP_INT_1610_GPTIMER3 34
270 # define OMAP_INT_1610_GPTIMER4 35
271 # define OMAP_INT_1610_GPTIMER5 36
272 # define OMAP_INT_1610_GPTIMER6 37
273 # define OMAP_INT_1610_GPTIMER7 38
274 # define OMAP_INT_1610_GPTIMER8 39
275 # define OMAP_INT_1610_GPIO_BANK2 40
276 # define OMAP_INT_1610_GPIO_BANK3 41
277 # define OMAP_INT_1610_MMC2 42
278 # define OMAP_INT_1610_CF 43
279 # define OMAP_INT_1610_WAKE_UP_REQ 46
280 # define OMAP_INT_1610_GPIO_BANK4 48
281 # define OMAP_INT_1610_SPI 49
282 # define OMAP_INT_1610_DMA_CH6 53
283 # define OMAP_INT_1610_DMA_CH7 54
284 # define OMAP_INT_1610_DMA_CH8 55
285 # define OMAP_INT_1610_DMA_CH9 56
286 # define OMAP_INT_1610_DMA_CH10 57
287 # define OMAP_INT_1610_DMA_CH11 58
288 # define OMAP_INT_1610_DMA_CH12 59
289 # define OMAP_INT_1610_DMA_CH13 60
290 # define OMAP_INT_1610_DMA_CH14 61
291 # define OMAP_INT_1610_DMA_CH15 62
292 # define OMAP_INT_1610_NAND 63
295 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
297 # define OMAP_INT_730_HW_ERRORS 0
298 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
299 # define OMAP_INT_730_CFCD 2
300 # define OMAP_INT_730_CFIREQ 3
301 # define OMAP_INT_730_I2C 4
302 # define OMAP_INT_730_PCC 5
303 # define OMAP_INT_730_MPU_EXT_NIRQ 6
304 # define OMAP_INT_730_SPI_100K_1 7
305 # define OMAP_INT_730_SYREN_SPI 8
306 # define OMAP_INT_730_VLYNQ 9
307 # define OMAP_INT_730_GPIO_BANK4 10
308 # define OMAP_INT_730_McBSP1TX 11
309 # define OMAP_INT_730_McBSP1RX 12
310 # define OMAP_INT_730_McBSP1RX_OF 13
311 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
312 # define OMAP_INT_730_UART_MODEM_1 15
313 # define OMAP_INT_730_MCSI 16
314 # define OMAP_INT_730_uWireTX 17
315 # define OMAP_INT_730_uWireRX 18
316 # define OMAP_INT_730_SMC_CD 19
317 # define OMAP_INT_730_SMC_IREQ 20
318 # define OMAP_INT_730_HDQ_1WIRE 21
319 # define OMAP_INT_730_TIMER32K 22
320 # define OMAP_INT_730_MMC_SDIO 23
321 # define OMAP_INT_730_UPLD 24
322 # define OMAP_INT_730_USB_HHC_1 27
323 # define OMAP_INT_730_USB_HHC_2 28
324 # define OMAP_INT_730_USB_GENI 29
325 # define OMAP_INT_730_USB_OTG 30
326 # define OMAP_INT_730_CAMERA_IF 31
327 # define OMAP_INT_730_RNG 32
328 # define OMAP_INT_730_DUAL_MODE_TIMER 33
329 # define OMAP_INT_730_DBB_RF_EN 34
330 # define OMAP_INT_730_MPUIO_KEYPAD 35
331 # define OMAP_INT_730_SHA1_MD5 36
332 # define OMAP_INT_730_SPI_100K_2 37
333 # define OMAP_INT_730_RNG_IDLE 38
334 # define OMAP_INT_730_MPUIO 39
335 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
336 # define OMAP_INT_730_LLPC_OE_FALLING 41
337 # define OMAP_INT_730_LLPC_OE_RISING 42
338 # define OMAP_INT_730_LLPC_VSYNC 43
339 # define OMAP_INT_730_WAKE_UP_REQ 46
340 # define OMAP_INT_730_DMA_CH6 53
341 # define OMAP_INT_730_DMA_CH7 54
342 # define OMAP_INT_730_DMA_CH8 55
343 # define OMAP_INT_730_DMA_CH9 56
344 # define OMAP_INT_730_DMA_CH10 57
345 # define OMAP_INT_730_DMA_CH11 58
346 # define OMAP_INT_730_DMA_CH12 59
347 # define OMAP_INT_730_DMA_CH13 60
348 # define OMAP_INT_730_DMA_CH14 61
349 # define OMAP_INT_730_DMA_CH15 62
350 # define OMAP_INT_730_NAND 63
353 * OMAP-24xx common IRQ numbers
355 # define OMAP_INT_24XX_STI 4
356 # define OMAP_INT_24XX_SYS_NIRQ 7
357 # define OMAP_INT_24XX_L3_IRQ 10
358 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
359 # define OMAP_INT_24XX_SDMA_IRQ0 12
360 # define OMAP_INT_24XX_SDMA_IRQ1 13
361 # define OMAP_INT_24XX_SDMA_IRQ2 14
362 # define OMAP_INT_24XX_SDMA_IRQ3 15
363 # define OMAP_INT_243X_MCBSP2_IRQ 16
364 # define OMAP_INT_243X_MCBSP3_IRQ 17
365 # define OMAP_INT_243X_MCBSP4_IRQ 18
366 # define OMAP_INT_243X_MCBSP5_IRQ 19
367 # define OMAP_INT_24XX_GPMC_IRQ 20
368 # define OMAP_INT_24XX_GUFFAW_IRQ 21
369 # define OMAP_INT_24XX_IVA_IRQ 22
370 # define OMAP_INT_24XX_EAC_IRQ 23
371 # define OMAP_INT_24XX_CAM_IRQ 24
372 # define OMAP_INT_24XX_DSS_IRQ 25
373 # define OMAP_INT_24XX_MAIL_U0_MPU 26
374 # define OMAP_INT_24XX_DSP_UMA 27
375 # define OMAP_INT_24XX_DSP_MMU 28
376 # define OMAP_INT_24XX_GPIO_BANK1 29
377 # define OMAP_INT_24XX_GPIO_BANK2 30
378 # define OMAP_INT_24XX_GPIO_BANK3 31
379 # define OMAP_INT_24XX_GPIO_BANK4 32
380 # define OMAP_INT_243X_GPIO_BANK5 33
381 # define OMAP_INT_24XX_MAIL_U3_MPU 34
382 # define OMAP_INT_24XX_WDT3 35
383 # define OMAP_INT_24XX_WDT4 36
384 # define OMAP_INT_24XX_GPTIMER1 37
385 # define OMAP_INT_24XX_GPTIMER2 38
386 # define OMAP_INT_24XX_GPTIMER3 39
387 # define OMAP_INT_24XX_GPTIMER4 40
388 # define OMAP_INT_24XX_GPTIMER5 41
389 # define OMAP_INT_24XX_GPTIMER6 42
390 # define OMAP_INT_24XX_GPTIMER7 43
391 # define OMAP_INT_24XX_GPTIMER8 44
392 # define OMAP_INT_24XX_GPTIMER9 45
393 # define OMAP_INT_24XX_GPTIMER10 46
394 # define OMAP_INT_24XX_GPTIMER11 47
395 # define OMAP_INT_24XX_GPTIMER12 48
396 # define OMAP_INT_24XX_PKA_IRQ 50
397 # define OMAP_INT_24XX_SHA1MD5_IRQ 51
398 # define OMAP_INT_24XX_RNG_IRQ 52
399 # define OMAP_INT_24XX_MG_IRQ 53
400 # define OMAP_INT_24XX_I2C1_IRQ 56
401 # define OMAP_INT_24XX_I2C2_IRQ 57
402 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
403 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
404 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
405 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
406 # define OMAP_INT_243X_MCBSP1_IRQ 64
407 # define OMAP_INT_24XX_MCSPI1_IRQ 65
408 # define OMAP_INT_24XX_MCSPI2_IRQ 66
409 # define OMAP_INT_24XX_SSI1_IRQ0 67
410 # define OMAP_INT_24XX_SSI1_IRQ1 68
411 # define OMAP_INT_24XX_SSI2_IRQ0 69
412 # define OMAP_INT_24XX_SSI2_IRQ1 70
413 # define OMAP_INT_24XX_SSI_GDD_IRQ 71
414 # define OMAP_INT_24XX_UART1_IRQ 72
415 # define OMAP_INT_24XX_UART2_IRQ 73
416 # define OMAP_INT_24XX_UART3_IRQ 74
417 # define OMAP_INT_24XX_USB_IRQ_GEN 75
418 # define OMAP_INT_24XX_USB_IRQ_NISO 76
419 # define OMAP_INT_24XX_USB_IRQ_ISO 77
420 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
421 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
422 # define OMAP_INT_24XX_USB_IRQ_OTG 80
423 # define OMAP_INT_24XX_VLYNQ_IRQ 81
424 # define OMAP_INT_24XX_MMC_IRQ 83
425 # define OMAP_INT_24XX_MS_IRQ 84
426 # define OMAP_INT_24XX_FAC_IRQ 85
427 # define OMAP_INT_24XX_MCSPI3_IRQ 91
428 # define OMAP_INT_243X_HS_USB_MC 92
429 # define OMAP_INT_243X_HS_USB_DMA 93
430 # define OMAP_INT_243X_CARKIT 94
431 # define OMAP_INT_34XX_GPTIMER12 95
434 enum omap_dma_model
{
442 struct soc_dma_s
*omap_dma_init(target_phys_addr_t base
, qemu_irq
*irqs
,
443 qemu_irq lcd_irq
, struct omap_mpu_state_s
*mpu
, omap_clk clk
,
444 enum omap_dma_model model
);
445 struct soc_dma_s
*omap_dma4_init(target_phys_addr_t base
, qemu_irq
*irqs
,
446 struct omap_mpu_state_s
*mpu
, int fifo
,
447 int chans
, omap_clk iclk
, omap_clk fclk
);
448 void omap_dma_reset(struct soc_dma_s
*s
);
455 /* Only used in OMAP DMA 3.x gigacells */
459 imif
, /* omap16xx: ocp_t1 */
461 local
, /* omap16xx: ocp_t2 */
463 __omap_dma_port_last
,
471 } omap_dma_addressing_t
;
473 /* Only used in OMAP DMA 3.x gigacells */
474 struct omap_dma_lcd_channel_s
{
475 enum omap_dma_port src
;
476 target_phys_addr_t src_f1_top
;
477 target_phys_addr_t src_f1_bottom
;
478 target_phys_addr_t src_f2_top
;
479 target_phys_addr_t src_f2_bottom
;
481 /* Used in OMAP DMA 3.2 gigacell */
482 unsigned char brust_f1
;
483 unsigned char pack_f1
;
484 unsigned char data_type_f1
;
485 unsigned char brust_f2
;
486 unsigned char pack_f2
;
487 unsigned char data_type_f2
;
488 unsigned char end_prog
;
489 unsigned char repeat
;
490 unsigned char auto_init
;
491 unsigned char priority
;
493 unsigned char running
;
495 unsigned char omap_3_1_compatible_disable
;
497 unsigned char lch_type
;
498 int16_t element_index_f1
;
499 int16_t element_index_f2
;
500 int32_t frame_index_f1
;
501 int32_t frame_index_f2
;
502 uint16_t elements_f1
;
504 uint16_t elements_f2
;
506 omap_dma_addressing_t mode_f1
;
507 omap_dma_addressing_t mode_f2
;
509 /* Destination port is fixed. */
515 target_phys_addr_t phys_framebuffer
[2];
517 struct omap_mpu_state_s
*mpu
;
518 } *omap_dma_get_lcdch(struct soc_dma_s
*s
);
521 * DMA request numbers for OMAP1
522 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
524 # define OMAP_DMA_NO_DEVICE 0
525 # define OMAP_DMA_MCSI1_TX 1
526 # define OMAP_DMA_MCSI1_RX 2
527 # define OMAP_DMA_I2C_RX 3
528 # define OMAP_DMA_I2C_TX 4
529 # define OMAP_DMA_EXT_NDMA_REQ0 5
530 # define OMAP_DMA_EXT_NDMA_REQ1 6
531 # define OMAP_DMA_UWIRE_TX 7
532 # define OMAP_DMA_MCBSP1_TX 8
533 # define OMAP_DMA_MCBSP1_RX 9
534 # define OMAP_DMA_MCBSP3_TX 10
535 # define OMAP_DMA_MCBSP3_RX 11
536 # define OMAP_DMA_UART1_TX 12
537 # define OMAP_DMA_UART1_RX 13
538 # define OMAP_DMA_UART2_TX 14
539 # define OMAP_DMA_UART2_RX 15
540 # define OMAP_DMA_MCBSP2_TX 16
541 # define OMAP_DMA_MCBSP2_RX 17
542 # define OMAP_DMA_UART3_TX 18
543 # define OMAP_DMA_UART3_RX 19
544 # define OMAP_DMA_CAMERA_IF_RX 20
545 # define OMAP_DMA_MMC_TX 21
546 # define OMAP_DMA_MMC_RX 22
547 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
548 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
549 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
550 # define OMAP_DMA_USB_W2FC_RX0 26
551 # define OMAP_DMA_USB_W2FC_RX1 27
552 # define OMAP_DMA_USB_W2FC_RX2 28
553 # define OMAP_DMA_USB_W2FC_TX0 29
554 # define OMAP_DMA_USB_W2FC_TX1 30
555 # define OMAP_DMA_USB_W2FC_TX2 31
557 /* These are only for 1610 */
558 # define OMAP_DMA_CRYPTO_DES_IN 32
559 # define OMAP_DMA_SPI_TX 33
560 # define OMAP_DMA_SPI_RX 34
561 # define OMAP_DMA_CRYPTO_HASH 35
562 # define OMAP_DMA_CCP_ATTN 36
563 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
564 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
565 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
566 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
567 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
568 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
569 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
570 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
571 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
572 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
573 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
574 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
575 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
576 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
577 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
578 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
579 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
580 # define OMAP_DMA_MMC2_TX 54
581 # define OMAP_DMA_MMC2_RX 55
582 # define OMAP_DMA_CRYPTO_DES_OUT 56
585 * DMA request numbers for the OMAP2
587 # define OMAP24XX_DMA_NO_DEVICE 0
588 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
589 # define OMAP24XX_DMA_EXT_DMAREQ0 2
590 # define OMAP24XX_DMA_EXT_DMAREQ1 3
591 # define OMAP24XX_DMA_GPMC 4
592 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
593 # define OMAP24XX_DMA_DSS 6
594 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
595 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
596 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
597 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
598 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
599 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
600 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
601 # define OMAP24XX_DMA_EXT_DMAREQ2 14
602 # define OMAP24XX_DMA_EXT_DMAREQ3 15
603 # define OMAP24XX_DMA_EXT_DMAREQ4 16
604 # define OMAP24XX_DMA_EAC_AC_RD 17
605 # define OMAP24XX_DMA_EAC_AC_WR 18
606 # define OMAP24XX_DMA_EAC_MD_UL_RD 19
607 # define OMAP24XX_DMA_EAC_MD_UL_WR 20
608 # define OMAP24XX_DMA_EAC_MD_DL_RD 21
609 # define OMAP24XX_DMA_EAC_MD_DL_WR 22
610 # define OMAP24XX_DMA_EAC_BT_UL_RD 23
611 # define OMAP24XX_DMA_EAC_BT_UL_WR 24
612 # define OMAP24XX_DMA_EAC_BT_DL_RD 25
613 # define OMAP24XX_DMA_EAC_BT_DL_WR 26
614 # define OMAP24XX_DMA_I2C1_TX 27
615 # define OMAP24XX_DMA_I2C1_RX 28
616 # define OMAP24XX_DMA_I2C2_TX 29
617 # define OMAP24XX_DMA_I2C2_RX 30
618 # define OMAP24XX_DMA_MCBSP1_TX 31
619 # define OMAP24XX_DMA_MCBSP1_RX 32
620 # define OMAP24XX_DMA_MCBSP2_TX 33
621 # define OMAP24XX_DMA_MCBSP2_RX 34
622 # define OMAP24XX_DMA_SPI1_TX0 35
623 # define OMAP24XX_DMA_SPI1_RX0 36
624 # define OMAP24XX_DMA_SPI1_TX1 37
625 # define OMAP24XX_DMA_SPI1_RX1 38
626 # define OMAP24XX_DMA_SPI1_TX2 39
627 # define OMAP24XX_DMA_SPI1_RX2 40
628 # define OMAP24XX_DMA_SPI1_TX3 41
629 # define OMAP24XX_DMA_SPI1_RX3 42
630 # define OMAP24XX_DMA_SPI2_TX0 43
631 # define OMAP24XX_DMA_SPI2_RX0 44
632 # define OMAP24XX_DMA_SPI2_TX1 45
633 # define OMAP24XX_DMA_SPI2_RX1 46
635 # define OMAP24XX_DMA_UART1_TX 49
636 # define OMAP24XX_DMA_UART1_RX 50
637 # define OMAP24XX_DMA_UART2_TX 51
638 # define OMAP24XX_DMA_UART2_RX 52
639 # define OMAP24XX_DMA_UART3_TX 53
640 # define OMAP24XX_DMA_UART3_RX 54
641 # define OMAP24XX_DMA_USB_W2FC_TX0 55
642 # define OMAP24XX_DMA_USB_W2FC_RX0 56
643 # define OMAP24XX_DMA_USB_W2FC_TX1 57
644 # define OMAP24XX_DMA_USB_W2FC_RX1 58
645 # define OMAP24XX_DMA_USB_W2FC_TX2 59
646 # define OMAP24XX_DMA_USB_W2FC_RX2 60
647 # define OMAP24XX_DMA_MMC1_TX 61
648 # define OMAP24XX_DMA_MMC1_RX 62
649 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
650 # define OMAP24XX_DMA_EXT_DMAREQ5 64
654 struct omap_gp_timer_s
;
655 struct omap_gp_timer_s
*omap_gp_timer_init(struct omap_target_agent_s
*ta
,
656 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
);
657 void omap_gp_timer_reset(struct omap_gp_timer_s
*s
);
659 /* OMAP2 sysctimer */
660 struct omap_synctimer_s
;
661 struct omap_synctimer_s
*omap_synctimer_init(struct omap_target_agent_s
*ta
,
662 struct omap_mpu_state_s
*mpu
, omap_clk fclk
, omap_clk iclk
);
663 void omap_synctimer_reset(struct omap_synctimer_s
*s
);
666 struct omap_uart_s
*omap_uart_init(target_phys_addr_t base
,
667 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
668 qemu_irq txdma
, qemu_irq rxdma
,
669 const char *label
, CharDriverState
*chr
);
670 struct omap_uart_s
*omap2_uart_init(struct omap_target_agent_s
*ta
,
671 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
672 qemu_irq txdma
, qemu_irq rxdma
,
673 const char *label
, CharDriverState
*chr
);
674 void omap_uart_reset(struct omap_uart_s
*s
);
675 void omap_uart_attach(struct omap_uart_s
*s
, CharDriverState
*chr
);
678 struct omap_mpuio_s
*omap_mpuio_init(target_phys_addr_t base
,
679 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
681 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
);
682 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
);
683 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
);
686 uint16_t (*receive
)(void *opaque
);
687 void (*send
)(void *opaque
, uint16_t data
);
691 struct omap_uwire_s
*omap_uwire_init(target_phys_addr_t base
,
692 qemu_irq
*irq
, qemu_irq dma
, omap_clk clk
);
693 void omap_uwire_attach(struct omap_uwire_s
*s
,
694 uWireSlave
*slave
, int chipselect
);
698 struct omap_mcspi_s
*omap_mcspi_init(struct omap_target_agent_s
*ta
, int chnum
,
699 qemu_irq irq
, qemu_irq
*drq
, omap_clk fclk
, omap_clk iclk
);
700 void omap_mcspi_attach(struct omap_mcspi_s
*s
,
701 uint32_t (*txrx
)(void *opaque
, uint32_t, int), void *opaque
,
703 void omap_mcspi_reset(struct omap_mcspi_s
*s
);
708 /* The CPU can call this if it is generating the clock signal on the
709 * i2s port. The CODEC can ignore it if it is set up as a clock
710 * master and generates its own clock. */
711 void (*set_rate
)(void *opaque
, int in
, int out
);
713 void (*tx_swallow
)(void *opaque
);
730 struct omap_mcbsp_s
*omap_mcbsp_init(target_phys_addr_t base
,
731 qemu_irq
*irq
, qemu_irq
*dma
, omap_clk clk
);
732 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s
*s
, I2SCodec
*slave
);
734 void omap_tap_init(struct omap_target_agent_s
*ta
,
735 struct omap_mpu_state_s
*mpu
);
738 struct omap_lcd_panel_s
;
739 void omap_lcdc_reset(struct omap_lcd_panel_s
*s
);
740 struct omap_lcd_panel_s
*omap_lcdc_init(target_phys_addr_t base
, qemu_irq irq
,
741 struct omap_dma_lcd_channel_s
*dma
,
742 ram_addr_t imif_base
, ram_addr_t emiff_base
, omap_clk clk
);
747 void (*write
)(void *opaque
, int dc
, uint16_t value
);
748 void (*block
)(void *opaque
, int dc
, void *buf
, size_t len
, int pitch
);
749 uint16_t (*read
)(void *opaque
, int dc
);
752 void omap_dss_reset(struct omap_dss_s
*s
);
753 struct omap_dss_s
*omap_dss_init(struct omap_target_agent_s
*ta
,
754 target_phys_addr_t l3_base
,
755 qemu_irq irq
, qemu_irq drq
,
756 omap_clk fck1
, omap_clk fck2
, omap_clk ck54m
,
757 omap_clk ick1
, omap_clk ick2
);
758 void omap_rfbi_attach(struct omap_dss_s
*s
, int cs
, struct rfbi_chip_s
*chip
);
762 struct omap_mmc_s
*omap_mmc_init(target_phys_addr_t base
,
763 BlockDriverState
*bd
,
764 qemu_irq irq
, qemu_irq dma
[], omap_clk clk
);
765 struct omap_mmc_s
*omap2_mmc_init(struct omap_target_agent_s
*ta
,
766 BlockDriverState
*bd
, qemu_irq irq
, qemu_irq dma
[],
767 omap_clk fclk
, omap_clk iclk
);
768 void omap_mmc_reset(struct omap_mmc_s
*s
);
769 void omap_mmc_handlers(struct omap_mmc_s
*s
, qemu_irq ro
, qemu_irq cover
);
770 void omap_mmc_enable(struct omap_mmc_s
*s
, int enable
);
774 struct omap_i2c_s
*omap_i2c_init(target_phys_addr_t base
,
775 qemu_irq irq
, qemu_irq
*dma
, omap_clk clk
);
776 struct omap_i2c_s
*omap2_i2c_init(struct omap_target_agent_s
*ta
,
777 qemu_irq irq
, qemu_irq
*dma
, omap_clk fclk
, omap_clk iclk
);
778 void omap_i2c_reset(struct omap_i2c_s
*s
);
779 i2c_bus
*omap_i2c_bus(struct omap_i2c_s
*s
);
781 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
782 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
783 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
784 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
785 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
786 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
787 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
788 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
790 # define cpu_is_omap15xx(cpu) \
791 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
792 # define cpu_is_omap16xx(cpu) \
793 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
794 # define cpu_is_omap24xx(cpu) \
795 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
797 # define cpu_class_omap1(cpu) \
798 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
799 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
800 # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
802 struct omap_mpu_state_s
{
803 enum omap_mpu_model
{
823 struct omap_dma_port_if_s
{
824 uint32_t (*read
[3])(struct omap_mpu_state_s
*s
,
825 target_phys_addr_t offset
);
826 void (*write
[3])(struct omap_mpu_state_s
*s
,
827 target_phys_addr_t offset
, uint32_t value
);
828 int (*addr_valid
)(struct omap_mpu_state_s
*s
,
829 target_phys_addr_t addr
);
830 } port
[__omap_dma_port_last
];
832 unsigned long sdram_size
;
833 unsigned long sram_size
;
835 /* MPUI-TIPB peripherals */
836 struct omap_uart_s
*uart
[3];
840 struct omap_mcbsp_s
*mcbsp1
;
841 struct omap_mcbsp_s
*mcbsp3
;
843 /* MPU public TIPB peripherals */
844 struct omap_32khz_timer_s
*os_timer
;
846 struct omap_mmc_s
*mmc
;
848 struct omap_mpuio_s
*mpuio
;
850 struct omap_uwire_s
*microwire
;
866 struct omap_i2c_s
*i2c
[2];
868 struct omap_rtc_s
*rtc
;
870 struct omap_mcbsp_s
*mcbsp2
;
872 struct omap_lpg_s
*led
[2];
874 /* MPU private TIPB peripherals */
875 struct omap_intr_handler_s
*ih
[2];
877 struct soc_dma_s
*dma
;
879 struct omap_mpu_timer_s
*timer
[3];
880 struct omap_watchdog_timer_s
*wdt
;
882 struct omap_lcd_panel_s
*lcd
;
884 uint32_t ulpd_pm_regs
[21];
885 int64_t ulpd_gauge_start
;
887 uint32_t func_mux_ctrl
[14];
888 uint32_t comp_mode_ctrl
[1];
889 uint32_t pull_dwn_ctrl
[4];
890 uint32_t gate_inh_ctrl
[1];
891 uint32_t voltage_ctrl
[1];
892 uint32_t test_dbg_ctrl
[1];
893 uint32_t mod_conf_ctrl
[1];
898 struct omap_tipb_bridge_s
*private_tipb
;
899 struct omap_tipb_bridge_s
*public_tipb
;
901 uint32_t tcmi_regs
[17];
913 uint16_t arm_idlect1
;
914 uint16_t arm_idlect2
;
920 uint16_t dsp_idlect1
;
921 uint16_t dsp_idlect2
;
925 /* OMAP2-only peripherals */
926 struct omap_l4_s
*l4
;
928 struct omap_gp_timer_s
*gptimer
[12];
929 struct omap_synctimer_s
*synctimer
;
931 struct omap_prcm_s
*prcm
;
932 struct omap_sdrc_s
*sdrc
;
933 struct omap_gpmc_s
*gpmc
;
934 struct omap_sysctl_s
*sysc
;
936 struct omap_mcspi_s
*mcspi
[2];
938 struct omap_dss_s
*dss
;
940 struct omap_eac_s
*eac
;
944 struct omap_mpu_state_s
*omap310_mpu_init(unsigned long sdram_size
,
948 struct omap_mpu_state_s
*omap2420_mpu_init(unsigned long sdram_size
,
951 # if TARGET_PHYS_ADDR_BITS == 32
952 # define OMAP_FMT_plx "%#08x"
953 # elif TARGET_PHYS_ADDR_BITS == 64
954 # define OMAP_FMT_plx "%#08" PRIx64
956 # error TARGET_PHYS_ADDR_BITS undefined
959 uint32_t omap_badwidth_read8(void *opaque
, target_phys_addr_t addr
);
960 void omap_badwidth_write8(void *opaque
, target_phys_addr_t addr
,
962 uint32_t omap_badwidth_read16(void *opaque
, target_phys_addr_t addr
);
963 void omap_badwidth_write16(void *opaque
, target_phys_addr_t addr
,
965 uint32_t omap_badwidth_read32(void *opaque
, target_phys_addr_t addr
);
966 void omap_badwidth_write32(void *opaque
, target_phys_addr_t addr
,
969 void omap_mpu_wakeup(void *opaque
, int irq
, int req
);
971 # define OMAP_BAD_REG(paddr) \
972 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
974 # define OMAP_RO_REG(paddr) \
975 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
978 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
979 (Board-specifc tags are not here) */
980 #define OMAP_TAG_CLOCK 0x4f01
981 #define OMAP_TAG_MMC 0x4f02
982 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
983 #define OMAP_TAG_USB 0x4f04
984 #define OMAP_TAG_LCD 0x4f05
985 #define OMAP_TAG_GPIO_SWITCH 0x4f06
986 #define OMAP_TAG_UART 0x4f07
987 #define OMAP_TAG_FBMEM 0x4f08
988 #define OMAP_TAG_STI_CONSOLE 0x4f09
989 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
990 #define OMAP_TAG_PARTITION 0x4f0b
991 #define OMAP_TAG_TEA5761 0x4f10
992 #define OMAP_TAG_TMP105 0x4f11
993 #define OMAP_TAG_BOOT_REASON 0x4f80
994 #define OMAP_TAG_FLASH_PART_STR 0x4f81
995 #define OMAP_TAG_VERSION_STR 0x4f82
998 OMAP_GPIOSW_TYPE_COVER
= 0 << 4,
999 OMAP_GPIOSW_TYPE_CONNECTION
= 1 << 4,
1000 OMAP_GPIOSW_TYPE_ACTIVITY
= 2 << 4,
1003 #define OMAP_GPIOSW_INVERTED 0x0001
1004 #define OMAP_GPIOSW_OUTPUT 0x0002
1006 # define TCMI_VERBOSE 1
1007 //# define MEM_VERBOSE 1
1009 # ifdef TCMI_VERBOSE
1010 # define OMAP_8B_REG(paddr) \
1011 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1012 __FUNCTION__, paddr)
1013 # define OMAP_16B_REG(paddr) \
1014 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1015 __FUNCTION__, paddr)
1016 # define OMAP_32B_REG(paddr) \
1017 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1018 __FUNCTION__, paddr)
1020 # define OMAP_8B_REG(paddr)
1021 # define OMAP_16B_REG(paddr)
1022 # define OMAP_32B_REG(paddr)
1025 # define OMAP_MPUI_REG_MASK 0x000007ff
1029 CPUReadMemoryFunc
* const *mem_read
;
1030 CPUWriteMemoryFunc
* const *mem_write
;
1035 static uint32_t io_readb(void *opaque
, target_phys_addr_t addr
)
1037 struct io_fn
*s
= opaque
;
1041 ret
= s
->mem_read
[0](s
->opaque
, addr
);
1044 fprintf(stderr
, "%08x ---> %02x\n", (uint32_t) addr
, ret
);
1047 static uint32_t io_readh(void *opaque
, target_phys_addr_t addr
)
1049 struct io_fn
*s
= opaque
;
1053 ret
= s
->mem_read
[1](s
->opaque
, addr
);
1056 fprintf(stderr
, "%08x ---> %04x\n", (uint32_t) addr
, ret
);
1059 static uint32_t io_readw(void *opaque
, target_phys_addr_t addr
)
1061 struct io_fn
*s
= opaque
;
1065 ret
= s
->mem_read
[2](s
->opaque
, addr
);
1068 fprintf(stderr
, "%08x ---> %08x\n", (uint32_t) addr
, ret
);
1071 static void io_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1073 struct io_fn
*s
= opaque
;
1076 fprintf(stderr
, "%08x <--- %02x\n", (uint32_t) addr
, value
);
1078 s
->mem_write
[0](s
->opaque
, addr
, value
);
1081 static void io_writeh(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1083 struct io_fn
*s
= opaque
;
1086 fprintf(stderr
, "%08x <--- %04x\n", (uint32_t) addr
, value
);
1088 s
->mem_write
[1](s
->opaque
, addr
, value
);
1091 static void io_writew(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
1093 struct io_fn
*s
= opaque
;
1096 fprintf(stderr
, "%08x <--- %08x\n", (uint32_t) addr
, value
);
1098 s
->mem_write
[2](s
->opaque
, addr
, value
);
1102 static CPUReadMemoryFunc
* const io_readfn
[] = { io_readb
, io_readh
, io_readw
, };
1103 static CPUWriteMemoryFunc
* const io_writefn
[] = { io_writeb
, io_writeh
, io_writew
, };
1105 inline static int debug_register_io_memory(CPUReadMemoryFunc
* const *mem_read
,
1106 CPUWriteMemoryFunc
* const *mem_write
,
1109 struct io_fn
*s
= g_malloc(sizeof(struct io_fn
));
1111 s
->mem_read
= mem_read
;
1112 s
->mem_write
= mem_write
;
1115 return cpu_register_io_memory(io_readfn
, io_writefn
, s
,
1116 DEVICE_NATIVE_ENDIAN
);
1118 # define cpu_register_io_memory debug_register_io_memory
1121 /* Define when we want to reduce the number of IO regions registered. */
1122 /*# define L4_MUX_HACK*/
1124 #endif /* hw_omap_h */