]> git.proxmox.com Git - qemu.git/blob - hw/omap1.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
OMAP STI/XTI console.
[qemu.git] / hw / omap1.c
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21 #include "hw.h"
22 #include "arm-misc.h"
23 #include "omap.h"
24 #include "sysemu.h"
25 #include "qemu-timer.h"
26 #include "qemu-char.h"
27 /* We use pc-style serial ports. */
28 #include "pc.h"
29
30 /* Should signal the TCMI/GPMC */
31 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
32 {
33 uint8_t ret;
34
35 OMAP_8B_REG(addr);
36 cpu_physical_memory_read(addr, (void *) &ret, 1);
37 return ret;
38 }
39
40 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
41 uint32_t value)
42 {
43 uint8_t val8 = value;
44
45 OMAP_8B_REG(addr);
46 cpu_physical_memory_write(addr, (void *) &val8, 1);
47 }
48
49 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
50 {
51 uint16_t ret;
52
53 OMAP_16B_REG(addr);
54 cpu_physical_memory_read(addr, (void *) &ret, 2);
55 return ret;
56 }
57
58 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
59 uint32_t value)
60 {
61 uint16_t val16 = value;
62
63 OMAP_16B_REG(addr);
64 cpu_physical_memory_write(addr, (void *) &val16, 2);
65 }
66
67 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
68 {
69 uint32_t ret;
70
71 OMAP_32B_REG(addr);
72 cpu_physical_memory_read(addr, (void *) &ret, 4);
73 return ret;
74 }
75
76 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
77 uint32_t value)
78 {
79 OMAP_32B_REG(addr);
80 cpu_physical_memory_write(addr, (void *) &value, 4);
81 }
82
83 /* Interrupt Handlers */
84 struct omap_intr_handler_bank_s {
85 uint32_t irqs;
86 uint32_t inputs;
87 uint32_t mask;
88 uint32_t fiq;
89 uint32_t sens_edge;
90 uint32_t swi;
91 unsigned char priority[32];
92 };
93
94 struct omap_intr_handler_s {
95 qemu_irq *pins;
96 qemu_irq parent_intr[2];
97 target_phys_addr_t base;
98 unsigned char nbanks;
99 int level_only;
100
101 /* state */
102 uint32_t new_agr[2];
103 int sir_intr[2];
104 int autoidle;
105 uint32_t mask;
106 struct omap_intr_handler_bank_s bank[];
107 };
108
109 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
110 {
111 int i, j, sir_intr, p_intr, p, f;
112 uint32_t level;
113 sir_intr = 0;
114 p_intr = 255;
115
116 /* Find the interrupt line with the highest dynamic priority.
117 * Note: 0 denotes the hightest priority.
118 * If all interrupts have the same priority, the default order is IRQ_N,
119 * IRQ_N-1,...,IRQ_0. */
120 for (j = 0; j < s->nbanks; ++j) {
121 level = s->bank[j].irqs & ~s->bank[j].mask &
122 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
123 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
124 level >>= f) {
125 p = s->bank[j].priority[i];
126 if (p <= p_intr) {
127 p_intr = p;
128 sir_intr = 32 * j + i;
129 }
130 f = ffs(level >> 1);
131 }
132 }
133 s->sir_intr[is_fiq] = sir_intr;
134 }
135
136 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
137 {
138 int i;
139 uint32_t has_intr = 0;
140
141 for (i = 0; i < s->nbanks; ++i)
142 has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
143 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
144
145 if (s->new_agr[is_fiq] & has_intr & s->mask) {
146 s->new_agr[is_fiq] = 0;
147 omap_inth_sir_update(s, is_fiq);
148 qemu_set_irq(s->parent_intr[is_fiq], 1);
149 }
150 }
151
152 #define INT_FALLING_EDGE 0
153 #define INT_LOW_LEVEL 1
154
155 static void omap_set_intr(void *opaque, int irq, int req)
156 {
157 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
158 uint32_t rise;
159
160 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
161 int n = irq & 31;
162
163 if (req) {
164 rise = ~bank->irqs & (1 << n);
165 if (~bank->sens_edge & (1 << n))
166 rise &= ~bank->inputs;
167
168 bank->inputs |= (1 << n);
169 if (rise) {
170 bank->irqs |= rise;
171 omap_inth_update(ih, 0);
172 omap_inth_update(ih, 1);
173 }
174 } else {
175 rise = bank->sens_edge & bank->irqs & (1 << n);
176 bank->irqs &= ~rise;
177 bank->inputs &= ~(1 << n);
178 }
179 }
180
181 /* Simplified version with no edge detection */
182 static void omap_set_intr_noedge(void *opaque, int irq, int req)
183 {
184 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
185 uint32_t rise;
186
187 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
188 int n = irq & 31;
189
190 if (req) {
191 rise = ~bank->inputs & (1 << n);
192 if (rise) {
193 bank->irqs |= bank->inputs |= rise;
194 omap_inth_update(ih, 0);
195 omap_inth_update(ih, 1);
196 }
197 } else
198 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
199 }
200
201 static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
202 {
203 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
204 int i, offset = addr - s->base;
205 int bank_no = offset >> 8;
206 int line_no;
207 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
208 offset &= 0xff;
209
210 switch (offset) {
211 case 0x00: /* ITR */
212 return bank->irqs;
213
214 case 0x04: /* MIR */
215 return bank->mask;
216
217 case 0x10: /* SIR_IRQ_CODE */
218 case 0x14: /* SIR_FIQ_CODE */
219 if (bank_no != 0)
220 break;
221 line_no = s->sir_intr[(offset - 0x10) >> 2];
222 bank = &s->bank[line_no >> 5];
223 i = line_no & 31;
224 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
225 bank->irqs &= ~(1 << i);
226 return line_no;
227
228 case 0x18: /* CONTROL_REG */
229 if (bank_no != 0)
230 break;
231 return 0;
232
233 case 0x1c: /* ILR0 */
234 case 0x20: /* ILR1 */
235 case 0x24: /* ILR2 */
236 case 0x28: /* ILR3 */
237 case 0x2c: /* ILR4 */
238 case 0x30: /* ILR5 */
239 case 0x34: /* ILR6 */
240 case 0x38: /* ILR7 */
241 case 0x3c: /* ILR8 */
242 case 0x40: /* ILR9 */
243 case 0x44: /* ILR10 */
244 case 0x48: /* ILR11 */
245 case 0x4c: /* ILR12 */
246 case 0x50: /* ILR13 */
247 case 0x54: /* ILR14 */
248 case 0x58: /* ILR15 */
249 case 0x5c: /* ILR16 */
250 case 0x60: /* ILR17 */
251 case 0x64: /* ILR18 */
252 case 0x68: /* ILR19 */
253 case 0x6c: /* ILR20 */
254 case 0x70: /* ILR21 */
255 case 0x74: /* ILR22 */
256 case 0x78: /* ILR23 */
257 case 0x7c: /* ILR24 */
258 case 0x80: /* ILR25 */
259 case 0x84: /* ILR26 */
260 case 0x88: /* ILR27 */
261 case 0x8c: /* ILR28 */
262 case 0x90: /* ILR29 */
263 case 0x94: /* ILR30 */
264 case 0x98: /* ILR31 */
265 i = (offset - 0x1c) >> 2;
266 return (bank->priority[i] << 2) |
267 (((bank->sens_edge >> i) & 1) << 1) |
268 ((bank->fiq >> i) & 1);
269
270 case 0x9c: /* ISR */
271 return 0x00000000;
272
273 }
274 OMAP_BAD_REG(addr);
275 return 0;
276 }
277
278 static void omap_inth_write(void *opaque, target_phys_addr_t addr,
279 uint32_t value)
280 {
281 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
282 int i, offset = addr - s->base;
283 int bank_no = offset >> 8;
284 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
285 offset &= 0xff;
286
287 switch (offset) {
288 case 0x00: /* ITR */
289 /* Important: ignore the clearing if the IRQ is level-triggered and
290 the input bit is 1 */
291 bank->irqs &= value | (bank->inputs & bank->sens_edge);
292 return;
293
294 case 0x04: /* MIR */
295 bank->mask = value;
296 omap_inth_update(s, 0);
297 omap_inth_update(s, 1);
298 return;
299
300 case 0x10: /* SIR_IRQ_CODE */
301 case 0x14: /* SIR_FIQ_CODE */
302 OMAP_RO_REG(addr);
303 break;
304
305 case 0x18: /* CONTROL_REG */
306 if (bank_no != 0)
307 break;
308 if (value & 2) {
309 qemu_set_irq(s->parent_intr[1], 0);
310 s->new_agr[1] = ~0;
311 omap_inth_update(s, 1);
312 }
313 if (value & 1) {
314 qemu_set_irq(s->parent_intr[0], 0);
315 s->new_agr[0] = ~0;
316 omap_inth_update(s, 0);
317 }
318 return;
319
320 case 0x1c: /* ILR0 */
321 case 0x20: /* ILR1 */
322 case 0x24: /* ILR2 */
323 case 0x28: /* ILR3 */
324 case 0x2c: /* ILR4 */
325 case 0x30: /* ILR5 */
326 case 0x34: /* ILR6 */
327 case 0x38: /* ILR7 */
328 case 0x3c: /* ILR8 */
329 case 0x40: /* ILR9 */
330 case 0x44: /* ILR10 */
331 case 0x48: /* ILR11 */
332 case 0x4c: /* ILR12 */
333 case 0x50: /* ILR13 */
334 case 0x54: /* ILR14 */
335 case 0x58: /* ILR15 */
336 case 0x5c: /* ILR16 */
337 case 0x60: /* ILR17 */
338 case 0x64: /* ILR18 */
339 case 0x68: /* ILR19 */
340 case 0x6c: /* ILR20 */
341 case 0x70: /* ILR21 */
342 case 0x74: /* ILR22 */
343 case 0x78: /* ILR23 */
344 case 0x7c: /* ILR24 */
345 case 0x80: /* ILR25 */
346 case 0x84: /* ILR26 */
347 case 0x88: /* ILR27 */
348 case 0x8c: /* ILR28 */
349 case 0x90: /* ILR29 */
350 case 0x94: /* ILR30 */
351 case 0x98: /* ILR31 */
352 i = (offset - 0x1c) >> 2;
353 bank->priority[i] = (value >> 2) & 0x1f;
354 bank->sens_edge &= ~(1 << i);
355 bank->sens_edge |= ((value >> 1) & 1) << i;
356 bank->fiq &= ~(1 << i);
357 bank->fiq |= (value & 1) << i;
358 return;
359
360 case 0x9c: /* ISR */
361 for (i = 0; i < 32; i ++)
362 if (value & (1 << i)) {
363 omap_set_intr(s, 32 * bank_no + i, 1);
364 return;
365 }
366 return;
367 }
368 OMAP_BAD_REG(addr);
369 }
370
371 static CPUReadMemoryFunc *omap_inth_readfn[] = {
372 omap_badwidth_read32,
373 omap_badwidth_read32,
374 omap_inth_read,
375 };
376
377 static CPUWriteMemoryFunc *omap_inth_writefn[] = {
378 omap_inth_write,
379 omap_inth_write,
380 omap_inth_write,
381 };
382
383 void omap_inth_reset(struct omap_intr_handler_s *s)
384 {
385 int i;
386
387 for (i = 0; i < s->nbanks; ++i){
388 s->bank[i].irqs = 0x00000000;
389 s->bank[i].mask = 0xffffffff;
390 s->bank[i].sens_edge = 0x00000000;
391 s->bank[i].fiq = 0x00000000;
392 s->bank[i].inputs = 0x00000000;
393 s->bank[i].swi = 0x00000000;
394 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
395
396 if (s->level_only)
397 s->bank[i].sens_edge = 0xffffffff;
398 }
399
400 s->new_agr[0] = ~0;
401 s->new_agr[1] = ~0;
402 s->sir_intr[0] = 0;
403 s->sir_intr[1] = 0;
404 s->autoidle = 0;
405 s->mask = ~0;
406
407 qemu_set_irq(s->parent_intr[0], 0);
408 qemu_set_irq(s->parent_intr[1], 0);
409 }
410
411 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
412 unsigned long size, unsigned char nbanks, qemu_irq **pins,
413 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
414 {
415 int iomemtype;
416 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
417 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
418 sizeof(struct omap_intr_handler_bank_s) * nbanks);
419
420 s->parent_intr[0] = parent_irq;
421 s->parent_intr[1] = parent_fiq;
422 s->base = base;
423 s->nbanks = nbanks;
424 s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
425 if (pins)
426 *pins = s->pins;
427
428 omap_inth_reset(s);
429
430 iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
431 omap_inth_writefn, s);
432 cpu_register_physical_memory(s->base, size, iomemtype);
433
434 return s;
435 }
436
437 static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
438 {
439 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
440 int offset = addr - s->base;
441 int bank_no, line_no;
442 struct omap_intr_handler_bank_s *bank = 0;
443
444 if ((offset & 0xf80) == 0x80) {
445 bank_no = (offset & 0x60) >> 5;
446 if (bank_no < s->nbanks) {
447 offset &= ~0x60;
448 bank = &s->bank[bank_no];
449 }
450 }
451
452 switch (offset) {
453 case 0x00: /* INTC_REVISION */
454 return 0x21;
455
456 case 0x10: /* INTC_SYSCONFIG */
457 return (s->autoidle >> 2) & 1;
458
459 case 0x14: /* INTC_SYSSTATUS */
460 return 1; /* RESETDONE */
461
462 case 0x40: /* INTC_SIR_IRQ */
463 return s->sir_intr[0];
464
465 case 0x44: /* INTC_SIR_FIQ */
466 return s->sir_intr[1];
467
468 case 0x48: /* INTC_CONTROL */
469 return (!s->mask) << 2; /* GLOBALMASK */
470
471 case 0x4c: /* INTC_PROTECTION */
472 return 0;
473
474 case 0x50: /* INTC_IDLE */
475 return s->autoidle & 3;
476
477 /* Per-bank registers */
478 case 0x80: /* INTC_ITR */
479 return bank->inputs;
480
481 case 0x84: /* INTC_MIR */
482 return bank->mask;
483
484 case 0x88: /* INTC_MIR_CLEAR */
485 case 0x8c: /* INTC_MIR_SET */
486 return 0;
487
488 case 0x90: /* INTC_ISR_SET */
489 return bank->swi;
490
491 case 0x94: /* INTC_ISR_CLEAR */
492 return 0;
493
494 case 0x98: /* INTC_PENDING_IRQ */
495 return bank->irqs & ~bank->mask & ~bank->fiq;
496
497 case 0x9c: /* INTC_PENDING_FIQ */
498 return bank->irqs & ~bank->mask & bank->fiq;
499
500 /* Per-line registers */
501 case 0x100 ... 0x300: /* INTC_ILR */
502 bank_no = (offset - 0x100) >> 7;
503 if (bank_no > s->nbanks)
504 break;
505 bank = &s->bank[bank_no];
506 line_no = (offset & 0x7f) >> 2;
507 return (bank->priority[line_no] << 2) |
508 ((bank->fiq >> line_no) & 1);
509 }
510 OMAP_BAD_REG(addr);
511 return 0;
512 }
513
514 static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
515 uint32_t value)
516 {
517 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
518 int offset = addr - s->base;
519 int bank_no, line_no;
520 struct omap_intr_handler_bank_s *bank = 0;
521
522 if ((offset & 0xf80) == 0x80) {
523 bank_no = (offset & 0x60) >> 5;
524 if (bank_no < s->nbanks) {
525 offset &= ~0x60;
526 bank = &s->bank[bank_no];
527 }
528 }
529
530 switch (offset) {
531 case 0x10: /* INTC_SYSCONFIG */
532 s->autoidle &= 4;
533 s->autoidle |= (value & 1) << 2;
534 if (value & 2) /* SOFTRESET */
535 omap_inth_reset(s);
536 return;
537
538 case 0x48: /* INTC_CONTROL */
539 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
540 if (value & 2) { /* NEWFIQAGR */
541 qemu_set_irq(s->parent_intr[1], 0);
542 s->new_agr[1] = ~0;
543 omap_inth_update(s, 1);
544 }
545 if (value & 1) { /* NEWIRQAGR */
546 qemu_set_irq(s->parent_intr[0], 0);
547 s->new_agr[0] = ~0;
548 omap_inth_update(s, 0);
549 }
550 return;
551
552 case 0x4c: /* INTC_PROTECTION */
553 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
554 * for every register, see Chapter 3 and 4 for privileged mode. */
555 if (value & 1)
556 fprintf(stderr, "%s: protection mode enable attempt\n",
557 __FUNCTION__);
558 return;
559
560 case 0x50: /* INTC_IDLE */
561 s->autoidle &= ~3;
562 s->autoidle |= value & 3;
563 return;
564
565 /* Per-bank registers */
566 case 0x84: /* INTC_MIR */
567 bank->mask = value;
568 omap_inth_update(s, 0);
569 omap_inth_update(s, 1);
570 return;
571
572 case 0x88: /* INTC_MIR_CLEAR */
573 bank->mask &= ~value;
574 omap_inth_update(s, 0);
575 omap_inth_update(s, 1);
576 return;
577
578 case 0x8c: /* INTC_MIR_SET */
579 bank->mask |= value;
580 return;
581
582 case 0x90: /* INTC_ISR_SET */
583 bank->irqs |= bank->swi |= value;
584 omap_inth_update(s, 0);
585 omap_inth_update(s, 1);
586 return;
587
588 case 0x94: /* INTC_ISR_CLEAR */
589 bank->swi &= ~value;
590 bank->irqs = bank->swi & bank->inputs;
591 return;
592
593 /* Per-line registers */
594 case 0x100 ... 0x300: /* INTC_ILR */
595 bank_no = (offset - 0x100) >> 7;
596 if (bank_no > s->nbanks)
597 break;
598 bank = &s->bank[bank_no];
599 line_no = (offset & 0x7f) >> 2;
600 bank->priority[line_no] = (value >> 2) & 0x3f;
601 bank->fiq &= ~(1 << line_no);
602 bank->fiq |= (value & 1) << line_no;
603 return;
604
605 case 0x00: /* INTC_REVISION */
606 case 0x14: /* INTC_SYSSTATUS */
607 case 0x40: /* INTC_SIR_IRQ */
608 case 0x44: /* INTC_SIR_FIQ */
609 case 0x80: /* INTC_ITR */
610 case 0x98: /* INTC_PENDING_IRQ */
611 case 0x9c: /* INTC_PENDING_FIQ */
612 OMAP_RO_REG(addr);
613 return;
614 }
615 OMAP_BAD_REG(addr);
616 }
617
618 static CPUReadMemoryFunc *omap2_inth_readfn[] = {
619 omap_badwidth_read32,
620 omap_badwidth_read32,
621 omap2_inth_read,
622 };
623
624 static CPUWriteMemoryFunc *omap2_inth_writefn[] = {
625 omap2_inth_write,
626 omap2_inth_write,
627 omap2_inth_write,
628 };
629
630 struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
631 int size, int nbanks, qemu_irq **pins,
632 qemu_irq parent_irq, qemu_irq parent_fiq,
633 omap_clk fclk, omap_clk iclk)
634 {
635 int iomemtype;
636 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
637 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
638 sizeof(struct omap_intr_handler_bank_s) * nbanks);
639
640 s->parent_intr[0] = parent_irq;
641 s->parent_intr[1] = parent_fiq;
642 s->base = base;
643 s->nbanks = nbanks;
644 s->level_only = 1;
645 s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
646 if (pins)
647 *pins = s->pins;
648
649 omap_inth_reset(s);
650
651 iomemtype = cpu_register_io_memory(0, omap2_inth_readfn,
652 omap2_inth_writefn, s);
653 cpu_register_physical_memory(s->base, size, iomemtype);
654
655 return s;
656 }
657
658 /* MPU OS timers */
659 struct omap_mpu_timer_s {
660 qemu_irq irq;
661 omap_clk clk;
662 target_phys_addr_t base;
663 uint32_t val;
664 int64_t time;
665 QEMUTimer *timer;
666 int64_t rate;
667 int it_ena;
668
669 int enable;
670 int ptv;
671 int ar;
672 int st;
673 uint32_t reset_val;
674 };
675
676 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
677 {
678 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
679
680 if (timer->st && timer->enable && timer->rate)
681 return timer->val - muldiv64(distance >> (timer->ptv + 1),
682 timer->rate, ticks_per_sec);
683 else
684 return timer->val;
685 }
686
687 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
688 {
689 timer->val = omap_timer_read(timer);
690 timer->time = qemu_get_clock(vm_clock);
691 }
692
693 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
694 {
695 int64_t expires;
696
697 if (timer->enable && timer->st && timer->rate) {
698 timer->val = timer->reset_val; /* Should skip this on clk enable */
699 expires = muldiv64(timer->val << (timer->ptv + 1),
700 ticks_per_sec, timer->rate);
701
702 /* If timer expiry would be sooner than in about 1 ms and
703 * auto-reload isn't set, then fire immediately. This is a hack
704 * to make systems like PalmOS run in acceptable time. PalmOS
705 * sets the interval to a very low value and polls the status bit
706 * in a busy loop when it wants to sleep just a couple of CPU
707 * ticks. */
708 if (expires > (ticks_per_sec >> 10) || timer->ar)
709 qemu_mod_timer(timer->timer, timer->time + expires);
710 else {
711 timer->val = 0;
712 timer->st = 0;
713 if (timer->it_ena)
714 /* Edge-triggered irq */
715 qemu_irq_pulse(timer->irq);
716 }
717 } else
718 qemu_del_timer(timer->timer);
719 }
720
721 static void omap_timer_tick(void *opaque)
722 {
723 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
724 omap_timer_sync(timer);
725
726 if (!timer->ar) {
727 timer->val = 0;
728 timer->st = 0;
729 }
730
731 if (timer->it_ena)
732 /* Edge-triggered irq */
733 qemu_irq_pulse(timer->irq);
734 omap_timer_update(timer);
735 }
736
737 static void omap_timer_clk_update(void *opaque, int line, int on)
738 {
739 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
740
741 omap_timer_sync(timer);
742 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
743 omap_timer_update(timer);
744 }
745
746 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
747 {
748 omap_clk_adduser(timer->clk,
749 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
750 timer->rate = omap_clk_getrate(timer->clk);
751 }
752
753 static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
754 {
755 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
756 int offset = addr - s->base;
757
758 switch (offset) {
759 case 0x00: /* CNTL_TIMER */
760 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
761
762 case 0x04: /* LOAD_TIM */
763 break;
764
765 case 0x08: /* READ_TIM */
766 return omap_timer_read(s);
767 }
768
769 OMAP_BAD_REG(addr);
770 return 0;
771 }
772
773 static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
774 uint32_t value)
775 {
776 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
777 int offset = addr - s->base;
778
779 switch (offset) {
780 case 0x00: /* CNTL_TIMER */
781 omap_timer_sync(s);
782 s->enable = (value >> 5) & 1;
783 s->ptv = (value >> 2) & 7;
784 s->ar = (value >> 1) & 1;
785 s->st = value & 1;
786 omap_timer_update(s);
787 return;
788
789 case 0x04: /* LOAD_TIM */
790 s->reset_val = value;
791 return;
792
793 case 0x08: /* READ_TIM */
794 OMAP_RO_REG(addr);
795 break;
796
797 default:
798 OMAP_BAD_REG(addr);
799 }
800 }
801
802 static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
803 omap_badwidth_read32,
804 omap_badwidth_read32,
805 omap_mpu_timer_read,
806 };
807
808 static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
809 omap_badwidth_write32,
810 omap_badwidth_write32,
811 omap_mpu_timer_write,
812 };
813
814 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
815 {
816 qemu_del_timer(s->timer);
817 s->enable = 0;
818 s->reset_val = 31337;
819 s->val = 0;
820 s->ptv = 0;
821 s->ar = 0;
822 s->st = 0;
823 s->it_ena = 1;
824 }
825
826 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
827 qemu_irq irq, omap_clk clk)
828 {
829 int iomemtype;
830 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
831 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
832
833 s->irq = irq;
834 s->clk = clk;
835 s->base = base;
836 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
837 omap_mpu_timer_reset(s);
838 omap_timer_clk_setup(s);
839
840 iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
841 omap_mpu_timer_writefn, s);
842 cpu_register_physical_memory(s->base, 0x100, iomemtype);
843
844 return s;
845 }
846
847 /* Watchdog timer */
848 struct omap_watchdog_timer_s {
849 struct omap_mpu_timer_s timer;
850 uint8_t last_wr;
851 int mode;
852 int free;
853 int reset;
854 };
855
856 static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
857 {
858 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
859 int offset = addr - s->timer.base;
860
861 switch (offset) {
862 case 0x00: /* CNTL_TIMER */
863 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
864 (s->timer.st << 7) | (s->free << 1);
865
866 case 0x04: /* READ_TIMER */
867 return omap_timer_read(&s->timer);
868
869 case 0x08: /* TIMER_MODE */
870 return s->mode << 15;
871 }
872
873 OMAP_BAD_REG(addr);
874 return 0;
875 }
876
877 static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
878 uint32_t value)
879 {
880 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
881 int offset = addr - s->timer.base;
882
883 switch (offset) {
884 case 0x00: /* CNTL_TIMER */
885 omap_timer_sync(&s->timer);
886 s->timer.ptv = (value >> 9) & 7;
887 s->timer.ar = (value >> 8) & 1;
888 s->timer.st = (value >> 7) & 1;
889 s->free = (value >> 1) & 1;
890 omap_timer_update(&s->timer);
891 break;
892
893 case 0x04: /* LOAD_TIMER */
894 s->timer.reset_val = value & 0xffff;
895 break;
896
897 case 0x08: /* TIMER_MODE */
898 if (!s->mode && ((value >> 15) & 1))
899 omap_clk_get(s->timer.clk);
900 s->mode |= (value >> 15) & 1;
901 if (s->last_wr == 0xf5) {
902 if ((value & 0xff) == 0xa0) {
903 if (s->mode) {
904 s->mode = 0;
905 omap_clk_put(s->timer.clk);
906 }
907 } else {
908 /* XXX: on T|E hardware somehow this has no effect,
909 * on Zire 71 it works as specified. */
910 s->reset = 1;
911 qemu_system_reset_request();
912 }
913 }
914 s->last_wr = value & 0xff;
915 break;
916
917 default:
918 OMAP_BAD_REG(addr);
919 }
920 }
921
922 static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
923 omap_badwidth_read16,
924 omap_wd_timer_read,
925 omap_badwidth_read16,
926 };
927
928 static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
929 omap_badwidth_write16,
930 omap_wd_timer_write,
931 omap_badwidth_write16,
932 };
933
934 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
935 {
936 qemu_del_timer(s->timer.timer);
937 if (!s->mode)
938 omap_clk_get(s->timer.clk);
939 s->mode = 1;
940 s->free = 1;
941 s->reset = 0;
942 s->timer.enable = 1;
943 s->timer.it_ena = 1;
944 s->timer.reset_val = 0xffff;
945 s->timer.val = 0;
946 s->timer.st = 0;
947 s->timer.ptv = 0;
948 s->timer.ar = 0;
949 omap_timer_update(&s->timer);
950 }
951
952 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
953 qemu_irq irq, omap_clk clk)
954 {
955 int iomemtype;
956 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
957 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
958
959 s->timer.irq = irq;
960 s->timer.clk = clk;
961 s->timer.base = base;
962 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
963 omap_wd_timer_reset(s);
964 omap_timer_clk_setup(&s->timer);
965
966 iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
967 omap_wd_timer_writefn, s);
968 cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
969
970 return s;
971 }
972
973 /* 32-kHz timer */
974 struct omap_32khz_timer_s {
975 struct omap_mpu_timer_s timer;
976 };
977
978 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
979 {
980 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
981 int offset = addr & OMAP_MPUI_REG_MASK;
982
983 switch (offset) {
984 case 0x00: /* TVR */
985 return s->timer.reset_val;
986
987 case 0x04: /* TCR */
988 return omap_timer_read(&s->timer);
989
990 case 0x08: /* CR */
991 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
992
993 default:
994 break;
995 }
996 OMAP_BAD_REG(addr);
997 return 0;
998 }
999
1000 static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
1001 uint32_t value)
1002 {
1003 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1004 int offset = addr & OMAP_MPUI_REG_MASK;
1005
1006 switch (offset) {
1007 case 0x00: /* TVR */
1008 s->timer.reset_val = value & 0x00ffffff;
1009 break;
1010
1011 case 0x04: /* TCR */
1012 OMAP_RO_REG(addr);
1013 break;
1014
1015 case 0x08: /* CR */
1016 s->timer.ar = (value >> 3) & 1;
1017 s->timer.it_ena = (value >> 2) & 1;
1018 if (s->timer.st != (value & 1) || (value & 2)) {
1019 omap_timer_sync(&s->timer);
1020 s->timer.enable = value & 1;
1021 s->timer.st = value & 1;
1022 omap_timer_update(&s->timer);
1023 }
1024 break;
1025
1026 default:
1027 OMAP_BAD_REG(addr);
1028 }
1029 }
1030
1031 static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
1032 omap_badwidth_read32,
1033 omap_badwidth_read32,
1034 omap_os_timer_read,
1035 };
1036
1037 static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
1038 omap_badwidth_write32,
1039 omap_badwidth_write32,
1040 omap_os_timer_write,
1041 };
1042
1043 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
1044 {
1045 qemu_del_timer(s->timer.timer);
1046 s->timer.enable = 0;
1047 s->timer.it_ena = 0;
1048 s->timer.reset_val = 0x00ffffff;
1049 s->timer.val = 0;
1050 s->timer.st = 0;
1051 s->timer.ptv = 0;
1052 s->timer.ar = 1;
1053 }
1054
1055 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
1056 qemu_irq irq, omap_clk clk)
1057 {
1058 int iomemtype;
1059 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
1060 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
1061
1062 s->timer.irq = irq;
1063 s->timer.clk = clk;
1064 s->timer.base = base;
1065 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1066 omap_os_timer_reset(s);
1067 omap_timer_clk_setup(&s->timer);
1068
1069 iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
1070 omap_os_timer_writefn, s);
1071 cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
1072
1073 return s;
1074 }
1075
1076 /* Ultra Low-Power Device Module */
1077 static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
1078 {
1079 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1080 int offset = addr - s->ulpd_pm_base;
1081 uint16_t ret;
1082
1083 switch (offset) {
1084 case 0x14: /* IT_STATUS */
1085 ret = s->ulpd_pm_regs[offset >> 2];
1086 s->ulpd_pm_regs[offset >> 2] = 0;
1087 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
1088 return ret;
1089
1090 case 0x18: /* Reserved */
1091 case 0x1c: /* Reserved */
1092 case 0x20: /* Reserved */
1093 case 0x28: /* Reserved */
1094 case 0x2c: /* Reserved */
1095 OMAP_BAD_REG(addr);
1096 case 0x00: /* COUNTER_32_LSB */
1097 case 0x04: /* COUNTER_32_MSB */
1098 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1099 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1100 case 0x10: /* GAUGING_CTRL */
1101 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1102 case 0x30: /* CLOCK_CTRL */
1103 case 0x34: /* SOFT_REQ */
1104 case 0x38: /* COUNTER_32_FIQ */
1105 case 0x3c: /* DPLL_CTRL */
1106 case 0x40: /* STATUS_REQ */
1107 /* XXX: check clk::usecount state for every clock */
1108 case 0x48: /* LOCL_TIME */
1109 case 0x4c: /* APLL_CTRL */
1110 case 0x50: /* POWER_CTRL */
1111 return s->ulpd_pm_regs[offset >> 2];
1112 }
1113
1114 OMAP_BAD_REG(addr);
1115 return 0;
1116 }
1117
1118 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
1119 uint16_t diff, uint16_t value)
1120 {
1121 if (diff & (1 << 4)) /* USB_MCLK_EN */
1122 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
1123 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
1124 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
1125 }
1126
1127 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
1128 uint16_t diff, uint16_t value)
1129 {
1130 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
1131 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
1132 if (diff & (1 << 1)) /* SOFT_COM_REQ */
1133 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
1134 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
1135 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
1136 if (diff & (1 << 3)) /* SOFT_USB_REQ */
1137 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
1138 }
1139
1140 static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
1141 uint32_t value)
1142 {
1143 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1144 int offset = addr - s->ulpd_pm_base;
1145 int64_t now, ticks;
1146 int div, mult;
1147 static const int bypass_div[4] = { 1, 2, 4, 4 };
1148 uint16_t diff;
1149
1150 switch (offset) {
1151 case 0x00: /* COUNTER_32_LSB */
1152 case 0x04: /* COUNTER_32_MSB */
1153 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1154 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1155 case 0x14: /* IT_STATUS */
1156 case 0x40: /* STATUS_REQ */
1157 OMAP_RO_REG(addr);
1158 break;
1159
1160 case 0x10: /* GAUGING_CTRL */
1161 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
1162 if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
1163 now = qemu_get_clock(vm_clock);
1164
1165 if (value & 1)
1166 s->ulpd_gauge_start = now;
1167 else {
1168 now -= s->ulpd_gauge_start;
1169
1170 /* 32-kHz ticks */
1171 ticks = muldiv64(now, 32768, ticks_per_sec);
1172 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
1173 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
1174 if (ticks >> 32) /* OVERFLOW_32K */
1175 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
1176
1177 /* High frequency ticks */
1178 ticks = muldiv64(now, 12000000, ticks_per_sec);
1179 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
1180 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
1181 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
1182 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
1183
1184 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1185 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
1186 }
1187 }
1188 s->ulpd_pm_regs[offset >> 2] = value;
1189 break;
1190
1191 case 0x18: /* Reserved */
1192 case 0x1c: /* Reserved */
1193 case 0x20: /* Reserved */
1194 case 0x28: /* Reserved */
1195 case 0x2c: /* Reserved */
1196 OMAP_BAD_REG(addr);
1197 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1198 case 0x38: /* COUNTER_32_FIQ */
1199 case 0x48: /* LOCL_TIME */
1200 case 0x50: /* POWER_CTRL */
1201 s->ulpd_pm_regs[offset >> 2] = value;
1202 break;
1203
1204 case 0x30: /* CLOCK_CTRL */
1205 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1206 s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
1207 omap_ulpd_clk_update(s, diff, value);
1208 break;
1209
1210 case 0x34: /* SOFT_REQ */
1211 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1212 s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
1213 omap_ulpd_req_update(s, diff, value);
1214 break;
1215
1216 case 0x3c: /* DPLL_CTRL */
1217 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1218 * omitted altogether, probably a typo. */
1219 /* This register has identical semantics with DPLL(1:3) control
1220 * registers, see omap_dpll_write() */
1221 diff = s->ulpd_pm_regs[offset >> 2] & value;
1222 s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
1223 if (diff & (0x3ff << 2)) {
1224 if (value & (1 << 4)) { /* PLL_ENABLE */
1225 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1226 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1227 } else {
1228 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1229 mult = 1;
1230 }
1231 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
1232 }
1233
1234 /* Enter the desired mode. */
1235 s->ulpd_pm_regs[offset >> 2] =
1236 (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
1237 ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
1238
1239 /* Act as if the lock is restored. */
1240 s->ulpd_pm_regs[offset >> 2] |= 2;
1241 break;
1242
1243 case 0x4c: /* APLL_CTRL */
1244 diff = s->ulpd_pm_regs[offset >> 2] & value;
1245 s->ulpd_pm_regs[offset >> 2] = value & 0xf;
1246 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
1247 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
1248 (value & (1 << 0)) ? "apll" : "dpll4"));
1249 break;
1250
1251 default:
1252 OMAP_BAD_REG(addr);
1253 }
1254 }
1255
1256 static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
1257 omap_badwidth_read16,
1258 omap_ulpd_pm_read,
1259 omap_badwidth_read16,
1260 };
1261
1262 static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
1263 omap_badwidth_write16,
1264 omap_ulpd_pm_write,
1265 omap_badwidth_write16,
1266 };
1267
1268 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
1269 {
1270 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
1271 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
1272 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
1273 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
1274 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
1275 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
1276 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
1277 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
1278 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
1279 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
1280 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
1281 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
1282 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
1283 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
1284 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
1285 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
1286 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
1287 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1288 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
1289 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
1290 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
1291 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
1292 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
1293 }
1294
1295 static void omap_ulpd_pm_init(target_phys_addr_t base,
1296 struct omap_mpu_state_s *mpu)
1297 {
1298 int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
1299 omap_ulpd_pm_writefn, mpu);
1300
1301 mpu->ulpd_pm_base = base;
1302 cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
1303 omap_ulpd_pm_reset(mpu);
1304 }
1305
1306 /* OMAP Pin Configuration */
1307 static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
1308 {
1309 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1310 int offset = addr - s->pin_cfg_base;
1311
1312 switch (offset) {
1313 case 0x00: /* FUNC_MUX_CTRL_0 */
1314 case 0x04: /* FUNC_MUX_CTRL_1 */
1315 case 0x08: /* FUNC_MUX_CTRL_2 */
1316 return s->func_mux_ctrl[offset >> 2];
1317
1318 case 0x0c: /* COMP_MODE_CTRL_0 */
1319 return s->comp_mode_ctrl[0];
1320
1321 case 0x10: /* FUNC_MUX_CTRL_3 */
1322 case 0x14: /* FUNC_MUX_CTRL_4 */
1323 case 0x18: /* FUNC_MUX_CTRL_5 */
1324 case 0x1c: /* FUNC_MUX_CTRL_6 */
1325 case 0x20: /* FUNC_MUX_CTRL_7 */
1326 case 0x24: /* FUNC_MUX_CTRL_8 */
1327 case 0x28: /* FUNC_MUX_CTRL_9 */
1328 case 0x2c: /* FUNC_MUX_CTRL_A */
1329 case 0x30: /* FUNC_MUX_CTRL_B */
1330 case 0x34: /* FUNC_MUX_CTRL_C */
1331 case 0x38: /* FUNC_MUX_CTRL_D */
1332 return s->func_mux_ctrl[(offset >> 2) - 1];
1333
1334 case 0x40: /* PULL_DWN_CTRL_0 */
1335 case 0x44: /* PULL_DWN_CTRL_1 */
1336 case 0x48: /* PULL_DWN_CTRL_2 */
1337 case 0x4c: /* PULL_DWN_CTRL_3 */
1338 return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
1339
1340 case 0x50: /* GATE_INH_CTRL_0 */
1341 return s->gate_inh_ctrl[0];
1342
1343 case 0x60: /* VOLTAGE_CTRL_0 */
1344 return s->voltage_ctrl[0];
1345
1346 case 0x70: /* TEST_DBG_CTRL_0 */
1347 return s->test_dbg_ctrl[0];
1348
1349 case 0x80: /* MOD_CONF_CTRL_0 */
1350 return s->mod_conf_ctrl[0];
1351 }
1352
1353 OMAP_BAD_REG(addr);
1354 return 0;
1355 }
1356
1357 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
1358 uint32_t diff, uint32_t value)
1359 {
1360 if (s->compat1509) {
1361 if (diff & (1 << 9)) /* BLUETOOTH */
1362 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
1363 (~value >> 9) & 1);
1364 if (diff & (1 << 7)) /* USB.CLKO */
1365 omap_clk_onoff(omap_findclk(s, "usb.clko"),
1366 (value >> 7) & 1);
1367 }
1368 }
1369
1370 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
1371 uint32_t diff, uint32_t value)
1372 {
1373 if (s->compat1509) {
1374 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1375 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
1376 (value >> 31) & 1);
1377 if (diff & (1 << 1)) /* CLK32K */
1378 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
1379 (~value >> 1) & 1);
1380 }
1381 }
1382
1383 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
1384 uint32_t diff, uint32_t value)
1385 {
1386 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1387 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
1388 omap_findclk(s, ((value >> 31) & 1) ?
1389 "ck_48m" : "armper_ck"));
1390 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1391 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
1392 omap_findclk(s, ((value >> 30) & 1) ?
1393 "ck_48m" : "armper_ck"));
1394 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1395 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
1396 omap_findclk(s, ((value >> 29) & 1) ?
1397 "ck_48m" : "armper_ck"));
1398 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1399 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
1400 omap_findclk(s, ((value >> 23) & 1) ?
1401 "ck_48m" : "armper_ck"));
1402 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1403 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
1404 omap_findclk(s, ((value >> 12) & 1) ?
1405 "ck_48m" : "armper_ck"));
1406 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1407 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
1408 }
1409
1410 static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
1411 uint32_t value)
1412 {
1413 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1414 int offset = addr - s->pin_cfg_base;
1415 uint32_t diff;
1416
1417 switch (offset) {
1418 case 0x00: /* FUNC_MUX_CTRL_0 */
1419 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1420 s->func_mux_ctrl[offset >> 2] = value;
1421 omap_pin_funcmux0_update(s, diff, value);
1422 return;
1423
1424 case 0x04: /* FUNC_MUX_CTRL_1 */
1425 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1426 s->func_mux_ctrl[offset >> 2] = value;
1427 omap_pin_funcmux1_update(s, diff, value);
1428 return;
1429
1430 case 0x08: /* FUNC_MUX_CTRL_2 */
1431 s->func_mux_ctrl[offset >> 2] = value;
1432 return;
1433
1434 case 0x0c: /* COMP_MODE_CTRL_0 */
1435 s->comp_mode_ctrl[0] = value;
1436 s->compat1509 = (value != 0x0000eaef);
1437 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
1438 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
1439 return;
1440
1441 case 0x10: /* FUNC_MUX_CTRL_3 */
1442 case 0x14: /* FUNC_MUX_CTRL_4 */
1443 case 0x18: /* FUNC_MUX_CTRL_5 */
1444 case 0x1c: /* FUNC_MUX_CTRL_6 */
1445 case 0x20: /* FUNC_MUX_CTRL_7 */
1446 case 0x24: /* FUNC_MUX_CTRL_8 */
1447 case 0x28: /* FUNC_MUX_CTRL_9 */
1448 case 0x2c: /* FUNC_MUX_CTRL_A */
1449 case 0x30: /* FUNC_MUX_CTRL_B */
1450 case 0x34: /* FUNC_MUX_CTRL_C */
1451 case 0x38: /* FUNC_MUX_CTRL_D */
1452 s->func_mux_ctrl[(offset >> 2) - 1] = value;
1453 return;
1454
1455 case 0x40: /* PULL_DWN_CTRL_0 */
1456 case 0x44: /* PULL_DWN_CTRL_1 */
1457 case 0x48: /* PULL_DWN_CTRL_2 */
1458 case 0x4c: /* PULL_DWN_CTRL_3 */
1459 s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
1460 return;
1461
1462 case 0x50: /* GATE_INH_CTRL_0 */
1463 s->gate_inh_ctrl[0] = value;
1464 return;
1465
1466 case 0x60: /* VOLTAGE_CTRL_0 */
1467 s->voltage_ctrl[0] = value;
1468 return;
1469
1470 case 0x70: /* TEST_DBG_CTRL_0 */
1471 s->test_dbg_ctrl[0] = value;
1472 return;
1473
1474 case 0x80: /* MOD_CONF_CTRL_0 */
1475 diff = s->mod_conf_ctrl[0] ^ value;
1476 s->mod_conf_ctrl[0] = value;
1477 omap_pin_modconf1_update(s, diff, value);
1478 return;
1479
1480 default:
1481 OMAP_BAD_REG(addr);
1482 }
1483 }
1484
1485 static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
1486 omap_badwidth_read32,
1487 omap_badwidth_read32,
1488 omap_pin_cfg_read,
1489 };
1490
1491 static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
1492 omap_badwidth_write32,
1493 omap_badwidth_write32,
1494 omap_pin_cfg_write,
1495 };
1496
1497 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
1498 {
1499 /* Start in Compatibility Mode. */
1500 mpu->compat1509 = 1;
1501 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
1502 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
1503 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
1504 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
1505 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
1506 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
1507 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
1508 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
1509 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
1510 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
1511 }
1512
1513 static void omap_pin_cfg_init(target_phys_addr_t base,
1514 struct omap_mpu_state_s *mpu)
1515 {
1516 int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
1517 omap_pin_cfg_writefn, mpu);
1518
1519 mpu->pin_cfg_base = base;
1520 cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
1521 omap_pin_cfg_reset(mpu);
1522 }
1523
1524 /* Device Identification, Die Identification */
1525 static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
1526 {
1527 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1528
1529 switch (addr) {
1530 case 0xfffe1800: /* DIE_ID_LSB */
1531 return 0xc9581f0e;
1532 case 0xfffe1804: /* DIE_ID_MSB */
1533 return 0xa8858bfa;
1534
1535 case 0xfffe2000: /* PRODUCT_ID_LSB */
1536 return 0x00aaaafc;
1537 case 0xfffe2004: /* PRODUCT_ID_MSB */
1538 return 0xcafeb574;
1539
1540 case 0xfffed400: /* JTAG_ID_LSB */
1541 switch (s->mpu_model) {
1542 case omap310:
1543 return 0x03310315;
1544 case omap1510:
1545 return 0x03310115;
1546 default:
1547 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
1548 }
1549 break;
1550
1551 case 0xfffed404: /* JTAG_ID_MSB */
1552 switch (s->mpu_model) {
1553 case omap310:
1554 return 0xfb57402f;
1555 case omap1510:
1556 return 0xfb47002f;
1557 default:
1558 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
1559 }
1560 break;
1561 }
1562
1563 OMAP_BAD_REG(addr);
1564 return 0;
1565 }
1566
1567 static void omap_id_write(void *opaque, target_phys_addr_t addr,
1568 uint32_t value)
1569 {
1570 OMAP_BAD_REG(addr);
1571 }
1572
1573 static CPUReadMemoryFunc *omap_id_readfn[] = {
1574 omap_badwidth_read32,
1575 omap_badwidth_read32,
1576 omap_id_read,
1577 };
1578
1579 static CPUWriteMemoryFunc *omap_id_writefn[] = {
1580 omap_badwidth_write32,
1581 omap_badwidth_write32,
1582 omap_id_write,
1583 };
1584
1585 static void omap_id_init(struct omap_mpu_state_s *mpu)
1586 {
1587 int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
1588 omap_id_writefn, mpu);
1589 cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
1590 cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
1591 if (!cpu_is_omap15xx(mpu))
1592 cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
1593 }
1594
1595 /* MPUI Control (Dummy) */
1596 static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
1597 {
1598 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1599 int offset = addr - s->mpui_base;
1600
1601 switch (offset) {
1602 case 0x00: /* CTRL */
1603 return s->mpui_ctrl;
1604 case 0x04: /* DEBUG_ADDR */
1605 return 0x01ffffff;
1606 case 0x08: /* DEBUG_DATA */
1607 return 0xffffffff;
1608 case 0x0c: /* DEBUG_FLAG */
1609 return 0x00000800;
1610 case 0x10: /* STATUS */
1611 return 0x00000000;
1612
1613 /* Not in OMAP310 */
1614 case 0x14: /* DSP_STATUS */
1615 case 0x18: /* DSP_BOOT_CONFIG */
1616 return 0x00000000;
1617 case 0x1c: /* DSP_MPUI_CONFIG */
1618 return 0x0000ffff;
1619 }
1620
1621 OMAP_BAD_REG(addr);
1622 return 0;
1623 }
1624
1625 static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
1626 uint32_t value)
1627 {
1628 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1629 int offset = addr - s->mpui_base;
1630
1631 switch (offset) {
1632 case 0x00: /* CTRL */
1633 s->mpui_ctrl = value & 0x007fffff;
1634 break;
1635
1636 case 0x04: /* DEBUG_ADDR */
1637 case 0x08: /* DEBUG_DATA */
1638 case 0x0c: /* DEBUG_FLAG */
1639 case 0x10: /* STATUS */
1640 /* Not in OMAP310 */
1641 case 0x14: /* DSP_STATUS */
1642 OMAP_RO_REG(addr);
1643 case 0x18: /* DSP_BOOT_CONFIG */
1644 case 0x1c: /* DSP_MPUI_CONFIG */
1645 break;
1646
1647 default:
1648 OMAP_BAD_REG(addr);
1649 }
1650 }
1651
1652 static CPUReadMemoryFunc *omap_mpui_readfn[] = {
1653 omap_badwidth_read32,
1654 omap_badwidth_read32,
1655 omap_mpui_read,
1656 };
1657
1658 static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
1659 omap_badwidth_write32,
1660 omap_badwidth_write32,
1661 omap_mpui_write,
1662 };
1663
1664 static void omap_mpui_reset(struct omap_mpu_state_s *s)
1665 {
1666 s->mpui_ctrl = 0x0003ff1b;
1667 }
1668
1669 static void omap_mpui_init(target_phys_addr_t base,
1670 struct omap_mpu_state_s *mpu)
1671 {
1672 int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
1673 omap_mpui_writefn, mpu);
1674
1675 mpu->mpui_base = base;
1676 cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
1677
1678 omap_mpui_reset(mpu);
1679 }
1680
1681 /* TIPB Bridges */
1682 struct omap_tipb_bridge_s {
1683 target_phys_addr_t base;
1684 qemu_irq abort;
1685
1686 int width_intr;
1687 uint16_t control;
1688 uint16_t alloc;
1689 uint16_t buffer;
1690 uint16_t enh_control;
1691 };
1692
1693 static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
1694 {
1695 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1696 int offset = addr - s->base;
1697
1698 switch (offset) {
1699 case 0x00: /* TIPB_CNTL */
1700 return s->control;
1701 case 0x04: /* TIPB_BUS_ALLOC */
1702 return s->alloc;
1703 case 0x08: /* MPU_TIPB_CNTL */
1704 return s->buffer;
1705 case 0x0c: /* ENHANCED_TIPB_CNTL */
1706 return s->enh_control;
1707 case 0x10: /* ADDRESS_DBG */
1708 case 0x14: /* DATA_DEBUG_LOW */
1709 case 0x18: /* DATA_DEBUG_HIGH */
1710 return 0xffff;
1711 case 0x1c: /* DEBUG_CNTR_SIG */
1712 return 0x00f8;
1713 }
1714
1715 OMAP_BAD_REG(addr);
1716 return 0;
1717 }
1718
1719 static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
1720 uint32_t value)
1721 {
1722 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1723 int offset = addr - s->base;
1724
1725 switch (offset) {
1726 case 0x00: /* TIPB_CNTL */
1727 s->control = value & 0xffff;
1728 break;
1729
1730 case 0x04: /* TIPB_BUS_ALLOC */
1731 s->alloc = value & 0x003f;
1732 break;
1733
1734 case 0x08: /* MPU_TIPB_CNTL */
1735 s->buffer = value & 0x0003;
1736 break;
1737
1738 case 0x0c: /* ENHANCED_TIPB_CNTL */
1739 s->width_intr = !(value & 2);
1740 s->enh_control = value & 0x000f;
1741 break;
1742
1743 case 0x10: /* ADDRESS_DBG */
1744 case 0x14: /* DATA_DEBUG_LOW */
1745 case 0x18: /* DATA_DEBUG_HIGH */
1746 case 0x1c: /* DEBUG_CNTR_SIG */
1747 OMAP_RO_REG(addr);
1748 break;
1749
1750 default:
1751 OMAP_BAD_REG(addr);
1752 }
1753 }
1754
1755 static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
1756 omap_badwidth_read16,
1757 omap_tipb_bridge_read,
1758 omap_tipb_bridge_read,
1759 };
1760
1761 static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
1762 omap_badwidth_write16,
1763 omap_tipb_bridge_write,
1764 omap_tipb_bridge_write,
1765 };
1766
1767 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1768 {
1769 s->control = 0xffff;
1770 s->alloc = 0x0009;
1771 s->buffer = 0x0000;
1772 s->enh_control = 0x000f;
1773 }
1774
1775 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
1776 qemu_irq abort_irq, omap_clk clk)
1777 {
1778 int iomemtype;
1779 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
1780 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
1781
1782 s->abort = abort_irq;
1783 s->base = base;
1784 omap_tipb_bridge_reset(s);
1785
1786 iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
1787 omap_tipb_bridge_writefn, s);
1788 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1789
1790 return s;
1791 }
1792
1793 /* Dummy Traffic Controller's Memory Interface */
1794 static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
1795 {
1796 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1797 int offset = addr - s->tcmi_base;
1798 uint32_t ret;
1799
1800 switch (offset) {
1801 case 0x00: /* IMIF_PRIO */
1802 case 0x04: /* EMIFS_PRIO */
1803 case 0x08: /* EMIFF_PRIO */
1804 case 0x0c: /* EMIFS_CONFIG */
1805 case 0x10: /* EMIFS_CS0_CONFIG */
1806 case 0x14: /* EMIFS_CS1_CONFIG */
1807 case 0x18: /* EMIFS_CS2_CONFIG */
1808 case 0x1c: /* EMIFS_CS3_CONFIG */
1809 case 0x24: /* EMIFF_MRS */
1810 case 0x28: /* TIMEOUT1 */
1811 case 0x2c: /* TIMEOUT2 */
1812 case 0x30: /* TIMEOUT3 */
1813 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1814 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1815 return s->tcmi_regs[offset >> 2];
1816
1817 case 0x20: /* EMIFF_SDRAM_CONFIG */
1818 ret = s->tcmi_regs[offset >> 2];
1819 s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1820 /* XXX: We can try using the VGA_DIRTY flag for this */
1821 return ret;
1822 }
1823
1824 OMAP_BAD_REG(addr);
1825 return 0;
1826 }
1827
1828 static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
1829 uint32_t value)
1830 {
1831 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1832 int offset = addr - s->tcmi_base;
1833
1834 switch (offset) {
1835 case 0x00: /* IMIF_PRIO */
1836 case 0x04: /* EMIFS_PRIO */
1837 case 0x08: /* EMIFF_PRIO */
1838 case 0x10: /* EMIFS_CS0_CONFIG */
1839 case 0x14: /* EMIFS_CS1_CONFIG */
1840 case 0x18: /* EMIFS_CS2_CONFIG */
1841 case 0x1c: /* EMIFS_CS3_CONFIG */
1842 case 0x20: /* EMIFF_SDRAM_CONFIG */
1843 case 0x24: /* EMIFF_MRS */
1844 case 0x28: /* TIMEOUT1 */
1845 case 0x2c: /* TIMEOUT2 */
1846 case 0x30: /* TIMEOUT3 */
1847 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1848 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1849 s->tcmi_regs[offset >> 2] = value;
1850 break;
1851 case 0x0c: /* EMIFS_CONFIG */
1852 s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
1853 break;
1854
1855 default:
1856 OMAP_BAD_REG(addr);
1857 }
1858 }
1859
1860 static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
1861 omap_badwidth_read32,
1862 omap_badwidth_read32,
1863 omap_tcmi_read,
1864 };
1865
1866 static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
1867 omap_badwidth_write32,
1868 omap_badwidth_write32,
1869 omap_tcmi_write,
1870 };
1871
1872 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1873 {
1874 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1875 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1876 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1877 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1878 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1879 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1880 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1881 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1882 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1883 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1884 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1885 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1886 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1887 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1888 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1889 }
1890
1891 static void omap_tcmi_init(target_phys_addr_t base,
1892 struct omap_mpu_state_s *mpu)
1893 {
1894 int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
1895 omap_tcmi_writefn, mpu);
1896
1897 mpu->tcmi_base = base;
1898 cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
1899 omap_tcmi_reset(mpu);
1900 }
1901
1902 /* Digital phase-locked loops control */
1903 static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
1904 {
1905 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1906 int offset = addr - s->base;
1907
1908 if (offset == 0x00) /* CTL_REG */
1909 return s->mode;
1910
1911 OMAP_BAD_REG(addr);
1912 return 0;
1913 }
1914
1915 static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
1916 uint32_t value)
1917 {
1918 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1919 uint16_t diff;
1920 int offset = addr - s->base;
1921 static const int bypass_div[4] = { 1, 2, 4, 4 };
1922 int div, mult;
1923
1924 if (offset == 0x00) { /* CTL_REG */
1925 /* See omap_ulpd_pm_write() too */
1926 diff = s->mode & value;
1927 s->mode = value & 0x2fff;
1928 if (diff & (0x3ff << 2)) {
1929 if (value & (1 << 4)) { /* PLL_ENABLE */
1930 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1931 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1932 } else {
1933 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1934 mult = 1;
1935 }
1936 omap_clk_setrate(s->dpll, div, mult);
1937 }
1938
1939 /* Enter the desired mode. */
1940 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1941
1942 /* Act as if the lock is restored. */
1943 s->mode |= 2;
1944 } else {
1945 OMAP_BAD_REG(addr);
1946 }
1947 }
1948
1949 static CPUReadMemoryFunc *omap_dpll_readfn[] = {
1950 omap_badwidth_read16,
1951 omap_dpll_read,
1952 omap_badwidth_read16,
1953 };
1954
1955 static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
1956 omap_badwidth_write16,
1957 omap_dpll_write,
1958 omap_badwidth_write16,
1959 };
1960
1961 static void omap_dpll_reset(struct dpll_ctl_s *s)
1962 {
1963 s->mode = 0x2002;
1964 omap_clk_setrate(s->dpll, 1, 1);
1965 }
1966
1967 static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
1968 omap_clk clk)
1969 {
1970 int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
1971 omap_dpll_writefn, s);
1972
1973 s->base = base;
1974 s->dpll = clk;
1975 omap_dpll_reset(s);
1976
1977 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1978 }
1979
1980 /* UARTs */
1981 struct omap_uart_s {
1982 SerialState *serial; /* TODO */
1983 struct omap_target_agent_s *ta;
1984 target_phys_addr_t base;
1985
1986 uint8_t eblr;
1987 uint8_t syscontrol;
1988 uint8_t wkup;
1989 uint8_t cfps;
1990 uint8_t mdr[2];
1991 uint8_t scr;
1992 };
1993
1994 void omap_uart_reset(struct omap_uart_s *s)
1995 {
1996 s->eblr = 0x00;
1997 s->syscontrol = 0;
1998 s->wkup = 0x3f;
1999 s->cfps = 0x69;
2000 }
2001
2002 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
2003 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2004 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2005 {
2006 struct omap_uart_s *s = (struct omap_uart_s *)
2007 qemu_mallocz(sizeof(struct omap_uart_s));
2008
2009 s->serial = serial_mm_init(base, 2, irq, chr ?: qemu_chr_open("null"), 1);
2010
2011 return s;
2012 }
2013
2014 static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
2015 {
2016 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
2017 int offset = addr - s->base;
2018
2019 switch (offset) {
2020 case 0x20: /* MDR1 */
2021 return s->mdr[0];
2022 case 0x24: /* MDR2 */
2023 return s->mdr[1];
2024 case 0x40: /* SCR */
2025 return s->scr;
2026 case 0x44: /* SSR */
2027 return 0x0;
2028 case 0x48: /* EBLR */
2029 return s->eblr;
2030 case 0x50: /* MVR */
2031 return 0x30;
2032 case 0x54: /* SYSC */
2033 return s->syscontrol;
2034 case 0x58: /* SYSS */
2035 return 1;
2036 case 0x5c: /* WER */
2037 return s->wkup;
2038 case 0x60: /* CFPS */
2039 return s->cfps;
2040 }
2041
2042 OMAP_BAD_REG(addr);
2043 return 0;
2044 }
2045
2046 static void omap_uart_write(void *opaque, target_phys_addr_t addr,
2047 uint32_t value)
2048 {
2049 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
2050 int offset = addr - s->base;
2051
2052 switch (offset) {
2053 case 0x20: /* MDR1 */
2054 s->mdr[0] = value & 0x7f;
2055 break;
2056 case 0x24: /* MDR2 */
2057 s->mdr[1] = value & 0xff;
2058 break;
2059 case 0x40: /* SCR */
2060 s->scr = value & 0xff;
2061 break;
2062 case 0x48: /* EBLR */
2063 s->eblr = value & 0xff;
2064 break;
2065 case 0x44: /* SSR */
2066 case 0x50: /* MVR */
2067 case 0x58: /* SYSS */
2068 OMAP_RO_REG(addr);
2069 break;
2070 case 0x54: /* SYSC */
2071 s->syscontrol = value & 0x1d;
2072 if (value & 2)
2073 omap_uart_reset(s);
2074 break;
2075 case 0x5c: /* WER */
2076 s->wkup = value & 0x7f;
2077 break;
2078 case 0x60: /* CFPS */
2079 s->cfps = value & 0xff;
2080 break;
2081 default:
2082 OMAP_BAD_REG(addr);
2083 }
2084 }
2085
2086 static CPUReadMemoryFunc *omap_uart_readfn[] = {
2087 omap_uart_read,
2088 omap_uart_read,
2089 omap_badwidth_read8,
2090 };
2091
2092 static CPUWriteMemoryFunc *omap_uart_writefn[] = {
2093 omap_uart_write,
2094 omap_uart_write,
2095 omap_badwidth_write8,
2096 };
2097
2098 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
2099 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2100 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2101 {
2102 target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
2103 struct omap_uart_s *s = omap_uart_init(base, irq,
2104 fclk, iclk, txdma, rxdma, chr);
2105 int iomemtype = cpu_register_io_memory(0, omap_uart_readfn,
2106 omap_uart_writefn, s);
2107
2108 s->ta = ta;
2109 s->base = base;
2110
2111 cpu_register_physical_memory(s->base + 0x20, 0x100, iomemtype);
2112
2113 return s;
2114 }
2115
2116 /* MPU Clock/Reset/Power Mode Control */
2117 static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
2118 {
2119 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2120 int offset = addr - s->clkm.mpu_base;
2121
2122 switch (offset) {
2123 case 0x00: /* ARM_CKCTL */
2124 return s->clkm.arm_ckctl;
2125
2126 case 0x04: /* ARM_IDLECT1 */
2127 return s->clkm.arm_idlect1;
2128
2129 case 0x08: /* ARM_IDLECT2 */
2130 return s->clkm.arm_idlect2;
2131
2132 case 0x0c: /* ARM_EWUPCT */
2133 return s->clkm.arm_ewupct;
2134
2135 case 0x10: /* ARM_RSTCT1 */
2136 return s->clkm.arm_rstct1;
2137
2138 case 0x14: /* ARM_RSTCT2 */
2139 return s->clkm.arm_rstct2;
2140
2141 case 0x18: /* ARM_SYSST */
2142 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
2143
2144 case 0x1c: /* ARM_CKOUT1 */
2145 return s->clkm.arm_ckout1;
2146
2147 case 0x20: /* ARM_CKOUT2 */
2148 break;
2149 }
2150
2151 OMAP_BAD_REG(addr);
2152 return 0;
2153 }
2154
2155 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
2156 uint16_t diff, uint16_t value)
2157 {
2158 omap_clk clk;
2159
2160 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
2161 if (value & (1 << 14))
2162 /* Reserved */;
2163 else {
2164 clk = omap_findclk(s, "arminth_ck");
2165 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2166 }
2167 }
2168 if (diff & (1 << 12)) { /* ARM_TIMXO */
2169 clk = omap_findclk(s, "armtim_ck");
2170 if (value & (1 << 12))
2171 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
2172 else
2173 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2174 }
2175 /* XXX: en_dspck */
2176 if (diff & (3 << 10)) { /* DSPMMUDIV */
2177 clk = omap_findclk(s, "dspmmu_ck");
2178 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
2179 }
2180 if (diff & (3 << 8)) { /* TCDIV */
2181 clk = omap_findclk(s, "tc_ck");
2182 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
2183 }
2184 if (diff & (3 << 6)) { /* DSPDIV */
2185 clk = omap_findclk(s, "dsp_ck");
2186 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
2187 }
2188 if (diff & (3 << 4)) { /* ARMDIV */
2189 clk = omap_findclk(s, "arm_ck");
2190 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
2191 }
2192 if (diff & (3 << 2)) { /* LCDDIV */
2193 clk = omap_findclk(s, "lcd_ck");
2194 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
2195 }
2196 if (diff & (3 << 0)) { /* PERDIV */
2197 clk = omap_findclk(s, "armper_ck");
2198 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
2199 }
2200 }
2201
2202 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
2203 uint16_t diff, uint16_t value)
2204 {
2205 omap_clk clk;
2206
2207 if (value & (1 << 11)) /* SETARM_IDLE */
2208 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
2209 if (!(value & (1 << 10))) /* WKUP_MODE */
2210 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2211
2212 #define SET_CANIDLE(clock, bit) \
2213 if (diff & (1 << bit)) { \
2214 clk = omap_findclk(s, clock); \
2215 omap_clk_canidle(clk, (value >> bit) & 1); \
2216 }
2217 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2218 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2219 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2220 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2221 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2222 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2223 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2224 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2225 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2226 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2227 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2228 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2229 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2230 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2231 }
2232
2233 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
2234 uint16_t diff, uint16_t value)
2235 {
2236 omap_clk clk;
2237
2238 #define SET_ONOFF(clock, bit) \
2239 if (diff & (1 << bit)) { \
2240 clk = omap_findclk(s, clock); \
2241 omap_clk_onoff(clk, (value >> bit) & 1); \
2242 }
2243 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2244 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2245 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2246 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2247 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2248 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2249 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2250 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2251 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2252 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2253 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2254 }
2255
2256 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
2257 uint16_t diff, uint16_t value)
2258 {
2259 omap_clk clk;
2260
2261 if (diff & (3 << 4)) { /* TCLKOUT */
2262 clk = omap_findclk(s, "tclk_out");
2263 switch ((value >> 4) & 3) {
2264 case 1:
2265 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
2266 omap_clk_onoff(clk, 1);
2267 break;
2268 case 2:
2269 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2270 omap_clk_onoff(clk, 1);
2271 break;
2272 default:
2273 omap_clk_onoff(clk, 0);
2274 }
2275 }
2276 if (diff & (3 << 2)) { /* DCLKOUT */
2277 clk = omap_findclk(s, "dclk_out");
2278 switch ((value >> 2) & 3) {
2279 case 0:
2280 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
2281 break;
2282 case 1:
2283 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
2284 break;
2285 case 2:
2286 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
2287 break;
2288 case 3:
2289 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2290 break;
2291 }
2292 }
2293 if (diff & (3 << 0)) { /* ACLKOUT */
2294 clk = omap_findclk(s, "aclk_out");
2295 switch ((value >> 0) & 3) {
2296 case 1:
2297 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2298 omap_clk_onoff(clk, 1);
2299 break;
2300 case 2:
2301 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
2302 omap_clk_onoff(clk, 1);
2303 break;
2304 case 3:
2305 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2306 omap_clk_onoff(clk, 1);
2307 break;
2308 default:
2309 omap_clk_onoff(clk, 0);
2310 }
2311 }
2312 }
2313
2314 static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
2315 uint32_t value)
2316 {
2317 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2318 int offset = addr - s->clkm.mpu_base;
2319 uint16_t diff;
2320 omap_clk clk;
2321 static const char *clkschemename[8] = {
2322 "fully synchronous", "fully asynchronous", "synchronous scalable",
2323 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2324 };
2325
2326 switch (offset) {
2327 case 0x00: /* ARM_CKCTL */
2328 diff = s->clkm.arm_ckctl ^ value;
2329 s->clkm.arm_ckctl = value & 0x7fff;
2330 omap_clkm_ckctl_update(s, diff, value);
2331 return;
2332
2333 case 0x04: /* ARM_IDLECT1 */
2334 diff = s->clkm.arm_idlect1 ^ value;
2335 s->clkm.arm_idlect1 = value & 0x0fff;
2336 omap_clkm_idlect1_update(s, diff, value);
2337 return;
2338
2339 case 0x08: /* ARM_IDLECT2 */
2340 diff = s->clkm.arm_idlect2 ^ value;
2341 s->clkm.arm_idlect2 = value & 0x07ff;
2342 omap_clkm_idlect2_update(s, diff, value);
2343 return;
2344
2345 case 0x0c: /* ARM_EWUPCT */
2346 diff = s->clkm.arm_ewupct ^ value;
2347 s->clkm.arm_ewupct = value & 0x003f;
2348 return;
2349
2350 case 0x10: /* ARM_RSTCT1 */
2351 diff = s->clkm.arm_rstct1 ^ value;
2352 s->clkm.arm_rstct1 = value & 0x0007;
2353 if (value & 9) {
2354 qemu_system_reset_request();
2355 s->clkm.cold_start = 0xa;
2356 }
2357 if (diff & ~value & 4) { /* DSP_RST */
2358 omap_mpui_reset(s);
2359 omap_tipb_bridge_reset(s->private_tipb);
2360 omap_tipb_bridge_reset(s->public_tipb);
2361 }
2362 if (diff & 2) { /* DSP_EN */
2363 clk = omap_findclk(s, "dsp_ck");
2364 omap_clk_canidle(clk, (~value >> 1) & 1);
2365 }
2366 return;
2367
2368 case 0x14: /* ARM_RSTCT2 */
2369 s->clkm.arm_rstct2 = value & 0x0001;
2370 return;
2371
2372 case 0x18: /* ARM_SYSST */
2373 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
2374 s->clkm.clocking_scheme = (value >> 11) & 7;
2375 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
2376 clkschemename[s->clkm.clocking_scheme]);
2377 }
2378 s->clkm.cold_start &= value & 0x3f;
2379 return;
2380
2381 case 0x1c: /* ARM_CKOUT1 */
2382 diff = s->clkm.arm_ckout1 ^ value;
2383 s->clkm.arm_ckout1 = value & 0x003f;
2384 omap_clkm_ckout1_update(s, diff, value);
2385 return;
2386
2387 case 0x20: /* ARM_CKOUT2 */
2388 default:
2389 OMAP_BAD_REG(addr);
2390 }
2391 }
2392
2393 static CPUReadMemoryFunc *omap_clkm_readfn[] = {
2394 omap_badwidth_read16,
2395 omap_clkm_read,
2396 omap_badwidth_read16,
2397 };
2398
2399 static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
2400 omap_badwidth_write16,
2401 omap_clkm_write,
2402 omap_badwidth_write16,
2403 };
2404
2405 static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
2406 {
2407 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2408 int offset = addr - s->clkm.dsp_base;
2409
2410 switch (offset) {
2411 case 0x04: /* DSP_IDLECT1 */
2412 return s->clkm.dsp_idlect1;
2413
2414 case 0x08: /* DSP_IDLECT2 */
2415 return s->clkm.dsp_idlect2;
2416
2417 case 0x14: /* DSP_RSTCT2 */
2418 return s->clkm.dsp_rstct2;
2419
2420 case 0x18: /* DSP_SYSST */
2421 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
2422 (s->env->halted << 6); /* Quite useless... */
2423 }
2424
2425 OMAP_BAD_REG(addr);
2426 return 0;
2427 }
2428
2429 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
2430 uint16_t diff, uint16_t value)
2431 {
2432 omap_clk clk;
2433
2434 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2435 }
2436
2437 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
2438 uint16_t diff, uint16_t value)
2439 {
2440 omap_clk clk;
2441
2442 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2443 }
2444
2445 static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
2446 uint32_t value)
2447 {
2448 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2449 int offset = addr - s->clkm.dsp_base;
2450 uint16_t diff;
2451
2452 switch (offset) {
2453 case 0x04: /* DSP_IDLECT1 */
2454 diff = s->clkm.dsp_idlect1 ^ value;
2455 s->clkm.dsp_idlect1 = value & 0x01f7;
2456 omap_clkdsp_idlect1_update(s, diff, value);
2457 break;
2458
2459 case 0x08: /* DSP_IDLECT2 */
2460 s->clkm.dsp_idlect2 = value & 0x0037;
2461 diff = s->clkm.dsp_idlect1 ^ value;
2462 omap_clkdsp_idlect2_update(s, diff, value);
2463 break;
2464
2465 case 0x14: /* DSP_RSTCT2 */
2466 s->clkm.dsp_rstct2 = value & 0x0001;
2467 break;
2468
2469 case 0x18: /* DSP_SYSST */
2470 s->clkm.cold_start &= value & 0x3f;
2471 break;
2472
2473 default:
2474 OMAP_BAD_REG(addr);
2475 }
2476 }
2477
2478 static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
2479 omap_badwidth_read16,
2480 omap_clkdsp_read,
2481 omap_badwidth_read16,
2482 };
2483
2484 static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
2485 omap_badwidth_write16,
2486 omap_clkdsp_write,
2487 omap_badwidth_write16,
2488 };
2489
2490 static void omap_clkm_reset(struct omap_mpu_state_s *s)
2491 {
2492 if (s->wdt && s->wdt->reset)
2493 s->clkm.cold_start = 0x6;
2494 s->clkm.clocking_scheme = 0;
2495 omap_clkm_ckctl_update(s, ~0, 0x3000);
2496 s->clkm.arm_ckctl = 0x3000;
2497 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
2498 s->clkm.arm_idlect1 = 0x0400;
2499 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
2500 s->clkm.arm_idlect2 = 0x0100;
2501 s->clkm.arm_ewupct = 0x003f;
2502 s->clkm.arm_rstct1 = 0x0000;
2503 s->clkm.arm_rstct2 = 0x0000;
2504 s->clkm.arm_ckout1 = 0x0015;
2505 s->clkm.dpll1_mode = 0x2002;
2506 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
2507 s->clkm.dsp_idlect1 = 0x0040;
2508 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
2509 s->clkm.dsp_idlect2 = 0x0000;
2510 s->clkm.dsp_rstct2 = 0x0000;
2511 }
2512
2513 static void omap_clkm_init(target_phys_addr_t mpu_base,
2514 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
2515 {
2516 int iomemtype[2] = {
2517 cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
2518 cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
2519 };
2520
2521 s->clkm.mpu_base = mpu_base;
2522 s->clkm.dsp_base = dsp_base;
2523 s->clkm.arm_idlect1 = 0x03ff;
2524 s->clkm.arm_idlect2 = 0x0100;
2525 s->clkm.dsp_idlect1 = 0x0002;
2526 omap_clkm_reset(s);
2527 s->clkm.cold_start = 0x3a;
2528
2529 cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
2530 cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
2531 }
2532
2533 /* MPU I/O */
2534 struct omap_mpuio_s {
2535 target_phys_addr_t base;
2536 qemu_irq irq;
2537 qemu_irq kbd_irq;
2538 qemu_irq *in;
2539 qemu_irq handler[16];
2540 qemu_irq wakeup;
2541
2542 uint16_t inputs;
2543 uint16_t outputs;
2544 uint16_t dir;
2545 uint16_t edge;
2546 uint16_t mask;
2547 uint16_t ints;
2548
2549 uint16_t debounce;
2550 uint16_t latch;
2551 uint8_t event;
2552
2553 uint8_t buttons[5];
2554 uint8_t row_latch;
2555 uint8_t cols;
2556 int kbd_mask;
2557 int clk;
2558 };
2559
2560 static void omap_mpuio_set(void *opaque, int line, int level)
2561 {
2562 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2563 uint16_t prev = s->inputs;
2564
2565 if (level)
2566 s->inputs |= 1 << line;
2567 else
2568 s->inputs &= ~(1 << line);
2569
2570 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
2571 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
2572 s->ints |= 1 << line;
2573 qemu_irq_raise(s->irq);
2574 /* TODO: wakeup */
2575 }
2576 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2577 (s->event >> 1) == line) /* PIN_SELECT */
2578 s->latch = s->inputs;
2579 }
2580 }
2581
2582 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
2583 {
2584 int i;
2585 uint8_t *row, rows = 0, cols = ~s->cols;
2586
2587 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
2588 if (*row & cols)
2589 rows |= i;
2590
2591 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
2592 s->row_latch = ~rows;
2593 }
2594
2595 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
2596 {
2597 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2598 int offset = addr & OMAP_MPUI_REG_MASK;
2599 uint16_t ret;
2600
2601 switch (offset) {
2602 case 0x00: /* INPUT_LATCH */
2603 return s->inputs;
2604
2605 case 0x04: /* OUTPUT_REG */
2606 return s->outputs;
2607
2608 case 0x08: /* IO_CNTL */
2609 return s->dir;
2610
2611 case 0x10: /* KBR_LATCH */
2612 return s->row_latch;
2613
2614 case 0x14: /* KBC_REG */
2615 return s->cols;
2616
2617 case 0x18: /* GPIO_EVENT_MODE_REG */
2618 return s->event;
2619
2620 case 0x1c: /* GPIO_INT_EDGE_REG */
2621 return s->edge;
2622
2623 case 0x20: /* KBD_INT */
2624 return (~s->row_latch & 0x1f) && !s->kbd_mask;
2625
2626 case 0x24: /* GPIO_INT */
2627 ret = s->ints;
2628 s->ints &= s->mask;
2629 if (ret)
2630 qemu_irq_lower(s->irq);
2631 return ret;
2632
2633 case 0x28: /* KBD_MASKIT */
2634 return s->kbd_mask;
2635
2636 case 0x2c: /* GPIO_MASKIT */
2637 return s->mask;
2638
2639 case 0x30: /* GPIO_DEBOUNCING_REG */
2640 return s->debounce;
2641
2642 case 0x34: /* GPIO_LATCH_REG */
2643 return s->latch;
2644 }
2645
2646 OMAP_BAD_REG(addr);
2647 return 0;
2648 }
2649
2650 static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
2651 uint32_t value)
2652 {
2653 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2654 int offset = addr & OMAP_MPUI_REG_MASK;
2655 uint16_t diff;
2656 int ln;
2657
2658 switch (offset) {
2659 case 0x04: /* OUTPUT_REG */
2660 diff = (s->outputs ^ value) & ~s->dir;
2661 s->outputs = value;
2662 while ((ln = ffs(diff))) {
2663 ln --;
2664 if (s->handler[ln])
2665 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2666 diff &= ~(1 << ln);
2667 }
2668 break;
2669
2670 case 0x08: /* IO_CNTL */
2671 diff = s->outputs & (s->dir ^ value);
2672 s->dir = value;
2673
2674 value = s->outputs & ~s->dir;
2675 while ((ln = ffs(diff))) {
2676 ln --;
2677 if (s->handler[ln])
2678 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2679 diff &= ~(1 << ln);
2680 }
2681 break;
2682
2683 case 0x14: /* KBC_REG */
2684 s->cols = value;
2685 omap_mpuio_kbd_update(s);
2686 break;
2687
2688 case 0x18: /* GPIO_EVENT_MODE_REG */
2689 s->event = value & 0x1f;
2690 break;
2691
2692 case 0x1c: /* GPIO_INT_EDGE_REG */
2693 s->edge = value;
2694 break;
2695
2696 case 0x28: /* KBD_MASKIT */
2697 s->kbd_mask = value & 1;
2698 omap_mpuio_kbd_update(s);
2699 break;
2700
2701 case 0x2c: /* GPIO_MASKIT */
2702 s->mask = value;
2703 break;
2704
2705 case 0x30: /* GPIO_DEBOUNCING_REG */
2706 s->debounce = value & 0x1ff;
2707 break;
2708
2709 case 0x00: /* INPUT_LATCH */
2710 case 0x10: /* KBR_LATCH */
2711 case 0x20: /* KBD_INT */
2712 case 0x24: /* GPIO_INT */
2713 case 0x34: /* GPIO_LATCH_REG */
2714 OMAP_RO_REG(addr);
2715 return;
2716
2717 default:
2718 OMAP_BAD_REG(addr);
2719 return;
2720 }
2721 }
2722
2723 static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
2724 omap_badwidth_read16,
2725 omap_mpuio_read,
2726 omap_badwidth_read16,
2727 };
2728
2729 static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
2730 omap_badwidth_write16,
2731 omap_mpuio_write,
2732 omap_badwidth_write16,
2733 };
2734
2735 static void omap_mpuio_reset(struct omap_mpuio_s *s)
2736 {
2737 s->inputs = 0;
2738 s->outputs = 0;
2739 s->dir = ~0;
2740 s->event = 0;
2741 s->edge = 0;
2742 s->kbd_mask = 0;
2743 s->mask = 0;
2744 s->debounce = 0;
2745 s->latch = 0;
2746 s->ints = 0;
2747 s->row_latch = 0x1f;
2748 s->clk = 1;
2749 }
2750
2751 static void omap_mpuio_onoff(void *opaque, int line, int on)
2752 {
2753 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2754
2755 s->clk = on;
2756 if (on)
2757 omap_mpuio_kbd_update(s);
2758 }
2759
2760 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
2761 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2762 omap_clk clk)
2763 {
2764 int iomemtype;
2765 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
2766 qemu_mallocz(sizeof(struct omap_mpuio_s));
2767
2768 s->base = base;
2769 s->irq = gpio_int;
2770 s->kbd_irq = kbd_int;
2771 s->wakeup = wakeup;
2772 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2773 omap_mpuio_reset(s);
2774
2775 iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
2776 omap_mpuio_writefn, s);
2777 cpu_register_physical_memory(s->base, 0x800, iomemtype);
2778
2779 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2780
2781 return s;
2782 }
2783
2784 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2785 {
2786 return s->in;
2787 }
2788
2789 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2790 {
2791 if (line >= 16 || line < 0)
2792 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
2793 s->handler[line] = handler;
2794 }
2795
2796 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2797 {
2798 if (row >= 5 || row < 0)
2799 cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
2800 __FUNCTION__, col, row);
2801
2802 if (down)
2803 s->buttons[row] |= 1 << col;
2804 else
2805 s->buttons[row] &= ~(1 << col);
2806
2807 omap_mpuio_kbd_update(s);
2808 }
2809
2810 /* General-Purpose I/O */
2811 struct omap_gpio_s {
2812 target_phys_addr_t base;
2813 qemu_irq irq;
2814 qemu_irq *in;
2815 qemu_irq handler[16];
2816
2817 uint16_t inputs;
2818 uint16_t outputs;
2819 uint16_t dir;
2820 uint16_t edge;
2821 uint16_t mask;
2822 uint16_t ints;
2823 uint16_t pins;
2824 };
2825
2826 static void omap_gpio_set(void *opaque, int line, int level)
2827 {
2828 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2829 uint16_t prev = s->inputs;
2830
2831 if (level)
2832 s->inputs |= 1 << line;
2833 else
2834 s->inputs &= ~(1 << line);
2835
2836 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
2837 (1 << line) & s->dir & ~s->mask) {
2838 s->ints |= 1 << line;
2839 qemu_irq_raise(s->irq);
2840 }
2841 }
2842
2843 static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
2844 {
2845 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2846 int offset = addr & OMAP_MPUI_REG_MASK;
2847
2848 switch (offset) {
2849 case 0x00: /* DATA_INPUT */
2850 return s->inputs & s->pins;
2851
2852 case 0x04: /* DATA_OUTPUT */
2853 return s->outputs;
2854
2855 case 0x08: /* DIRECTION_CONTROL */
2856 return s->dir;
2857
2858 case 0x0c: /* INTERRUPT_CONTROL */
2859 return s->edge;
2860
2861 case 0x10: /* INTERRUPT_MASK */
2862 return s->mask;
2863
2864 case 0x14: /* INTERRUPT_STATUS */
2865 return s->ints;
2866
2867 case 0x18: /* PIN_CONTROL (not in OMAP310) */
2868 OMAP_BAD_REG(addr);
2869 return s->pins;
2870 }
2871
2872 OMAP_BAD_REG(addr);
2873 return 0;
2874 }
2875
2876 static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
2877 uint32_t value)
2878 {
2879 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2880 int offset = addr & OMAP_MPUI_REG_MASK;
2881 uint16_t diff;
2882 int ln;
2883
2884 switch (offset) {
2885 case 0x00: /* DATA_INPUT */
2886 OMAP_RO_REG(addr);
2887 return;
2888
2889 case 0x04: /* DATA_OUTPUT */
2890 diff = (s->outputs ^ value) & ~s->dir;
2891 s->outputs = value;
2892 while ((ln = ffs(diff))) {
2893 ln --;
2894 if (s->handler[ln])
2895 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2896 diff &= ~(1 << ln);
2897 }
2898 break;
2899
2900 case 0x08: /* DIRECTION_CONTROL */
2901 diff = s->outputs & (s->dir ^ value);
2902 s->dir = value;
2903
2904 value = s->outputs & ~s->dir;
2905 while ((ln = ffs(diff))) {
2906 ln --;
2907 if (s->handler[ln])
2908 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2909 diff &= ~(1 << ln);
2910 }
2911 break;
2912
2913 case 0x0c: /* INTERRUPT_CONTROL */
2914 s->edge = value;
2915 break;
2916
2917 case 0x10: /* INTERRUPT_MASK */
2918 s->mask = value;
2919 break;
2920
2921 case 0x14: /* INTERRUPT_STATUS */
2922 s->ints &= ~value;
2923 if (!s->ints)
2924 qemu_irq_lower(s->irq);
2925 break;
2926
2927 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
2928 OMAP_BAD_REG(addr);
2929 s->pins = value;
2930 break;
2931
2932 default:
2933 OMAP_BAD_REG(addr);
2934 return;
2935 }
2936 }
2937
2938 /* *Some* sources say the memory region is 32-bit. */
2939 static CPUReadMemoryFunc *omap_gpio_readfn[] = {
2940 omap_badwidth_read16,
2941 omap_gpio_read,
2942 omap_badwidth_read16,
2943 };
2944
2945 static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
2946 omap_badwidth_write16,
2947 omap_gpio_write,
2948 omap_badwidth_write16,
2949 };
2950
2951 static void omap_gpio_reset(struct omap_gpio_s *s)
2952 {
2953 s->inputs = 0;
2954 s->outputs = ~0;
2955 s->dir = ~0;
2956 s->edge = ~0;
2957 s->mask = ~0;
2958 s->ints = 0;
2959 s->pins = ~0;
2960 }
2961
2962 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
2963 qemu_irq irq, omap_clk clk)
2964 {
2965 int iomemtype;
2966 struct omap_gpio_s *s = (struct omap_gpio_s *)
2967 qemu_mallocz(sizeof(struct omap_gpio_s));
2968
2969 s->base = base;
2970 s->irq = irq;
2971 s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
2972 omap_gpio_reset(s);
2973
2974 iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
2975 omap_gpio_writefn, s);
2976 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
2977
2978 return s;
2979 }
2980
2981 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
2982 {
2983 return s->in;
2984 }
2985
2986 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
2987 {
2988 if (line >= 16 || line < 0)
2989 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
2990 s->handler[line] = handler;
2991 }
2992
2993 /* MicroWire Interface */
2994 struct omap_uwire_s {
2995 target_phys_addr_t base;
2996 qemu_irq txirq;
2997 qemu_irq rxirq;
2998 qemu_irq txdrq;
2999
3000 uint16_t txbuf;
3001 uint16_t rxbuf;
3002 uint16_t control;
3003 uint16_t setup[5];
3004
3005 struct uwire_slave_s *chip[4];
3006 };
3007
3008 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
3009 {
3010 int chipselect = (s->control >> 10) & 3; /* INDEX */
3011 struct uwire_slave_s *slave = s->chip[chipselect];
3012
3013 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
3014 if (s->control & (1 << 12)) /* CS_CMD */
3015 if (slave && slave->send)
3016 slave->send(slave->opaque,
3017 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
3018 s->control &= ~(1 << 14); /* CSRB */
3019 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3020 * a DRQ. When is the level IRQ supposed to be reset? */
3021 }
3022
3023 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
3024 if (s->control & (1 << 12)) /* CS_CMD */
3025 if (slave && slave->receive)
3026 s->rxbuf = slave->receive(slave->opaque);
3027 s->control |= 1 << 15; /* RDRB */
3028 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3029 * a DRQ. When is the level IRQ supposed to be reset? */
3030 }
3031 }
3032
3033 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
3034 {
3035 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3036 int offset = addr & OMAP_MPUI_REG_MASK;
3037
3038 switch (offset) {
3039 case 0x00: /* RDR */
3040 s->control &= ~(1 << 15); /* RDRB */
3041 return s->rxbuf;
3042
3043 case 0x04: /* CSR */
3044 return s->control;
3045
3046 case 0x08: /* SR1 */
3047 return s->setup[0];
3048 case 0x0c: /* SR2 */
3049 return s->setup[1];
3050 case 0x10: /* SR3 */
3051 return s->setup[2];
3052 case 0x14: /* SR4 */
3053 return s->setup[3];
3054 case 0x18: /* SR5 */
3055 return s->setup[4];
3056 }
3057
3058 OMAP_BAD_REG(addr);
3059 return 0;
3060 }
3061
3062 static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
3063 uint32_t value)
3064 {
3065 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3066 int offset = addr & OMAP_MPUI_REG_MASK;
3067
3068 switch (offset) {
3069 case 0x00: /* TDR */
3070 s->txbuf = value; /* TD */
3071 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
3072 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
3073 (s->control & (1 << 12)))) { /* CS_CMD */
3074 s->control |= 1 << 14; /* CSRB */
3075 omap_uwire_transfer_start(s);
3076 }
3077 break;
3078
3079 case 0x04: /* CSR */
3080 s->control = value & 0x1fff;
3081 if (value & (1 << 13)) /* START */
3082 omap_uwire_transfer_start(s);
3083 break;
3084
3085 case 0x08: /* SR1 */
3086 s->setup[0] = value & 0x003f;
3087 break;
3088
3089 case 0x0c: /* SR2 */
3090 s->setup[1] = value & 0x0fc0;
3091 break;
3092
3093 case 0x10: /* SR3 */
3094 s->setup[2] = value & 0x0003;
3095 break;
3096
3097 case 0x14: /* SR4 */
3098 s->setup[3] = value & 0x0001;
3099 break;
3100
3101 case 0x18: /* SR5 */
3102 s->setup[4] = value & 0x000f;
3103 break;
3104
3105 default:
3106 OMAP_BAD_REG(addr);
3107 return;
3108 }
3109 }
3110
3111 static CPUReadMemoryFunc *omap_uwire_readfn[] = {
3112 omap_badwidth_read16,
3113 omap_uwire_read,
3114 omap_badwidth_read16,
3115 };
3116
3117 static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
3118 omap_badwidth_write16,
3119 omap_uwire_write,
3120 omap_badwidth_write16,
3121 };
3122
3123 static void omap_uwire_reset(struct omap_uwire_s *s)
3124 {
3125 s->control = 0;
3126 s->setup[0] = 0;
3127 s->setup[1] = 0;
3128 s->setup[2] = 0;
3129 s->setup[3] = 0;
3130 s->setup[4] = 0;
3131 }
3132
3133 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
3134 qemu_irq *irq, qemu_irq dma, omap_clk clk)
3135 {
3136 int iomemtype;
3137 struct omap_uwire_s *s = (struct omap_uwire_s *)
3138 qemu_mallocz(sizeof(struct omap_uwire_s));
3139
3140 s->base = base;
3141 s->txirq = irq[0];
3142 s->rxirq = irq[1];
3143 s->txdrq = dma;
3144 omap_uwire_reset(s);
3145
3146 iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
3147 omap_uwire_writefn, s);
3148 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3149
3150 return s;
3151 }
3152
3153 void omap_uwire_attach(struct omap_uwire_s *s,
3154 struct uwire_slave_s *slave, int chipselect)
3155 {
3156 if (chipselect < 0 || chipselect > 3) {
3157 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
3158 exit(-1);
3159 }
3160
3161 s->chip[chipselect] = slave;
3162 }
3163
3164 /* Pseudonoise Pulse-Width Light Modulator */
3165 static void omap_pwl_update(struct omap_mpu_state_s *s)
3166 {
3167 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
3168
3169 if (output != s->pwl.output) {
3170 s->pwl.output = output;
3171 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
3172 }
3173 }
3174
3175 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
3176 {
3177 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3178 int offset = addr & OMAP_MPUI_REG_MASK;
3179
3180 switch (offset) {
3181 case 0x00: /* PWL_LEVEL */
3182 return s->pwl.level;
3183 case 0x04: /* PWL_CTRL */
3184 return s->pwl.enable;
3185 }
3186 OMAP_BAD_REG(addr);
3187 return 0;
3188 }
3189
3190 static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
3191 uint32_t value)
3192 {
3193 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3194 int offset = addr & OMAP_MPUI_REG_MASK;
3195
3196 switch (offset) {
3197 case 0x00: /* PWL_LEVEL */
3198 s->pwl.level = value;
3199 omap_pwl_update(s);
3200 break;
3201 case 0x04: /* PWL_CTRL */
3202 s->pwl.enable = value & 1;
3203 omap_pwl_update(s);
3204 break;
3205 default:
3206 OMAP_BAD_REG(addr);
3207 return;
3208 }
3209 }
3210
3211 static CPUReadMemoryFunc *omap_pwl_readfn[] = {
3212 omap_pwl_read,
3213 omap_badwidth_read8,
3214 omap_badwidth_read8,
3215 };
3216
3217 static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
3218 omap_pwl_write,
3219 omap_badwidth_write8,
3220 omap_badwidth_write8,
3221 };
3222
3223 static void omap_pwl_reset(struct omap_mpu_state_s *s)
3224 {
3225 s->pwl.output = 0;
3226 s->pwl.level = 0;
3227 s->pwl.enable = 0;
3228 s->pwl.clk = 1;
3229 omap_pwl_update(s);
3230 }
3231
3232 static void omap_pwl_clk_update(void *opaque, int line, int on)
3233 {
3234 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3235
3236 s->pwl.clk = on;
3237 omap_pwl_update(s);
3238 }
3239
3240 static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3241 omap_clk clk)
3242 {
3243 int iomemtype;
3244
3245 omap_pwl_reset(s);
3246
3247 iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
3248 omap_pwl_writefn, s);
3249 cpu_register_physical_memory(base, 0x800, iomemtype);
3250
3251 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
3252 }
3253
3254 /* Pulse-Width Tone module */
3255 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
3256 {
3257 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3258 int offset = addr & OMAP_MPUI_REG_MASK;
3259
3260 switch (offset) {
3261 case 0x00: /* FRC */
3262 return s->pwt.frc;
3263 case 0x04: /* VCR */
3264 return s->pwt.vrc;
3265 case 0x08: /* GCR */
3266 return s->pwt.gcr;
3267 }
3268 OMAP_BAD_REG(addr);
3269 return 0;
3270 }
3271
3272 static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
3273 uint32_t value)
3274 {
3275 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3276 int offset = addr & OMAP_MPUI_REG_MASK;
3277
3278 switch (offset) {
3279 case 0x00: /* FRC */
3280 s->pwt.frc = value & 0x3f;
3281 break;
3282 case 0x04: /* VRC */
3283 if ((value ^ s->pwt.vrc) & 1) {
3284 if (value & 1)
3285 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
3286 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3287 ((omap_clk_getrate(s->pwt.clk) >> 3) /
3288 /* Pre-multiplexer divider */
3289 ((s->pwt.gcr & 2) ? 1 : 154) /
3290 /* Octave multiplexer */
3291 (2 << (value & 3)) *
3292 /* 101/107 divider */
3293 ((value & (1 << 2)) ? 101 : 107) *
3294 /* 49/55 divider */
3295 ((value & (1 << 3)) ? 49 : 55) *
3296 /* 50/63 divider */
3297 ((value & (1 << 4)) ? 50 : 63) *
3298 /* 80/127 divider */
3299 ((value & (1 << 5)) ? 80 : 127) /
3300 (107 * 55 * 63 * 127)));
3301 else
3302 printf("%s: silence!\n", __FUNCTION__);
3303 }
3304 s->pwt.vrc = value & 0x7f;
3305 break;
3306 case 0x08: /* GCR */
3307 s->pwt.gcr = value & 3;
3308 break;
3309 default:
3310 OMAP_BAD_REG(addr);
3311 return;
3312 }
3313 }
3314
3315 static CPUReadMemoryFunc *omap_pwt_readfn[] = {
3316 omap_pwt_read,
3317 omap_badwidth_read8,
3318 omap_badwidth_read8,
3319 };
3320
3321 static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
3322 omap_pwt_write,
3323 omap_badwidth_write8,
3324 omap_badwidth_write8,
3325 };
3326
3327 static void omap_pwt_reset(struct omap_mpu_state_s *s)
3328 {
3329 s->pwt.frc = 0;
3330 s->pwt.vrc = 0;
3331 s->pwt.gcr = 0;
3332 }
3333
3334 static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3335 omap_clk clk)
3336 {
3337 int iomemtype;
3338
3339 s->pwt.clk = clk;
3340 omap_pwt_reset(s);
3341
3342 iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
3343 omap_pwt_writefn, s);
3344 cpu_register_physical_memory(base, 0x800, iomemtype);
3345 }
3346
3347 /* Real-time Clock module */
3348 struct omap_rtc_s {
3349 target_phys_addr_t base;
3350 qemu_irq irq;
3351 qemu_irq alarm;
3352 QEMUTimer *clk;
3353
3354 uint8_t interrupts;
3355 uint8_t status;
3356 int16_t comp_reg;
3357 int running;
3358 int pm_am;
3359 int auto_comp;
3360 int round;
3361 struct tm alarm_tm;
3362 time_t alarm_ti;
3363
3364 struct tm current_tm;
3365 time_t ti;
3366 uint64_t tick;
3367 };
3368
3369 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
3370 {
3371 /* s->alarm is level-triggered */
3372 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
3373 }
3374
3375 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
3376 {
3377 s->alarm_ti = mktime(&s->alarm_tm);
3378 if (s->alarm_ti == -1)
3379 printf("%s: conversion failed\n", __FUNCTION__);
3380 }
3381
3382 static inline uint8_t omap_rtc_bcd(int num)
3383 {
3384 return ((num / 10) << 4) | (num % 10);
3385 }
3386
3387 static inline int omap_rtc_bin(uint8_t num)
3388 {
3389 return (num & 15) + 10 * (num >> 4);
3390 }
3391
3392 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
3393 {
3394 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3395 int offset = addr & OMAP_MPUI_REG_MASK;
3396 uint8_t i;
3397
3398 switch (offset) {
3399 case 0x00: /* SECONDS_REG */
3400 return omap_rtc_bcd(s->current_tm.tm_sec);
3401
3402 case 0x04: /* MINUTES_REG */
3403 return omap_rtc_bcd(s->current_tm.tm_min);
3404
3405 case 0x08: /* HOURS_REG */
3406 if (s->pm_am)
3407 return ((s->current_tm.tm_hour > 11) << 7) |
3408 omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
3409 else
3410 return omap_rtc_bcd(s->current_tm.tm_hour);
3411
3412 case 0x0c: /* DAYS_REG */
3413 return omap_rtc_bcd(s->current_tm.tm_mday);
3414
3415 case 0x10: /* MONTHS_REG */
3416 return omap_rtc_bcd(s->current_tm.tm_mon + 1);
3417
3418 case 0x14: /* YEARS_REG */
3419 return omap_rtc_bcd(s->current_tm.tm_year % 100);
3420
3421 case 0x18: /* WEEK_REG */
3422 return s->current_tm.tm_wday;
3423
3424 case 0x20: /* ALARM_SECONDS_REG */
3425 return omap_rtc_bcd(s->alarm_tm.tm_sec);
3426
3427 case 0x24: /* ALARM_MINUTES_REG */
3428 return omap_rtc_bcd(s->alarm_tm.tm_min);
3429
3430 case 0x28: /* ALARM_HOURS_REG */
3431 if (s->pm_am)
3432 return ((s->alarm_tm.tm_hour > 11) << 7) |
3433 omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
3434 else
3435 return omap_rtc_bcd(s->alarm_tm.tm_hour);
3436
3437 case 0x2c: /* ALARM_DAYS_REG */
3438 return omap_rtc_bcd(s->alarm_tm.tm_mday);
3439
3440 case 0x30: /* ALARM_MONTHS_REG */
3441 return omap_rtc_bcd(s->alarm_tm.tm_mon + 1);
3442
3443 case 0x34: /* ALARM_YEARS_REG */
3444 return omap_rtc_bcd(s->alarm_tm.tm_year % 100);
3445
3446 case 0x40: /* RTC_CTRL_REG */
3447 return (s->pm_am << 3) | (s->auto_comp << 2) |
3448 (s->round << 1) | s->running;
3449
3450 case 0x44: /* RTC_STATUS_REG */
3451 i = s->status;
3452 s->status &= ~0x3d;
3453 return i;
3454
3455 case 0x48: /* RTC_INTERRUPTS_REG */
3456 return s->interrupts;
3457
3458 case 0x4c: /* RTC_COMP_LSB_REG */
3459 return ((uint16_t) s->comp_reg) & 0xff;
3460
3461 case 0x50: /* RTC_COMP_MSB_REG */
3462 return ((uint16_t) s->comp_reg) >> 8;
3463 }
3464
3465 OMAP_BAD_REG(addr);
3466 return 0;
3467 }
3468
3469 static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
3470 uint32_t value)
3471 {
3472 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3473 int offset = addr & OMAP_MPUI_REG_MASK;
3474 struct tm new_tm;
3475 time_t ti[2];
3476
3477 switch (offset) {
3478 case 0x00: /* SECONDS_REG */
3479 #if ALMDEBUG
3480 printf("RTC SEC_REG <-- %02x\n", value);
3481 #endif
3482 s->ti -= s->current_tm.tm_sec;
3483 s->ti += omap_rtc_bin(value);
3484 return;
3485
3486 case 0x04: /* MINUTES_REG */
3487 #if ALMDEBUG
3488 printf("RTC MIN_REG <-- %02x\n", value);
3489 #endif
3490 s->ti -= s->current_tm.tm_min * 60;
3491 s->ti += omap_rtc_bin(value) * 60;
3492 return;
3493
3494 case 0x08: /* HOURS_REG */
3495 #if ALMDEBUG
3496 printf("RTC HRS_REG <-- %02x\n", value);
3497 #endif
3498 s->ti -= s->current_tm.tm_hour * 3600;
3499 if (s->pm_am) {
3500 s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600;
3501 s->ti += ((value >> 7) & 1) * 43200;
3502 } else
3503 s->ti += omap_rtc_bin(value & 0x3f) * 3600;
3504 return;
3505
3506 case 0x0c: /* DAYS_REG */
3507 #if ALMDEBUG
3508 printf("RTC DAY_REG <-- %02x\n", value);
3509 #endif
3510 s->ti -= s->current_tm.tm_mday * 86400;
3511 s->ti += omap_rtc_bin(value) * 86400;
3512 return;
3513
3514 case 0x10: /* MONTHS_REG */
3515 #if ALMDEBUG
3516 printf("RTC MTH_REG <-- %02x\n", value);
3517 #endif
3518 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3519 new_tm.tm_mon = omap_rtc_bin(value);
3520 ti[0] = mktime(&s->current_tm);
3521 ti[1] = mktime(&new_tm);
3522
3523 if (ti[0] != -1 && ti[1] != -1) {
3524 s->ti -= ti[0];
3525 s->ti += ti[1];
3526 } else {
3527 /* A less accurate version */
3528 s->ti -= s->current_tm.tm_mon * 2592000;
3529 s->ti += omap_rtc_bin(value) * 2592000;
3530 }
3531 return;
3532
3533 case 0x14: /* YEARS_REG */
3534 #if ALMDEBUG
3535 printf("RTC YRS_REG <-- %02x\n", value);
3536 #endif
3537 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3538 new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
3539 ti[0] = mktime(&s->current_tm);
3540 ti[1] = mktime(&new_tm);
3541
3542 if (ti[0] != -1 && ti[1] != -1) {
3543 s->ti -= ti[0];
3544 s->ti += ti[1];
3545 } else {
3546 /* A less accurate version */
3547 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
3548 s->ti += omap_rtc_bin(value) * 31536000;
3549 }
3550 return;
3551
3552 case 0x18: /* WEEK_REG */
3553 return; /* Ignored */
3554
3555 case 0x20: /* ALARM_SECONDS_REG */
3556 #if ALMDEBUG
3557 printf("ALM SEC_REG <-- %02x\n", value);
3558 #endif
3559 s->alarm_tm.tm_sec = omap_rtc_bin(value);
3560 omap_rtc_alarm_update(s);
3561 return;
3562
3563 case 0x24: /* ALARM_MINUTES_REG */
3564 #if ALMDEBUG
3565 printf("ALM MIN_REG <-- %02x\n", value);
3566 #endif
3567 s->alarm_tm.tm_min = omap_rtc_bin(value);
3568 omap_rtc_alarm_update(s);
3569 return;
3570
3571 case 0x28: /* ALARM_HOURS_REG */
3572 #if ALMDEBUG
3573 printf("ALM HRS_REG <-- %02x\n", value);
3574 #endif
3575 if (s->pm_am)
3576 s->alarm_tm.tm_hour =
3577 ((omap_rtc_bin(value & 0x3f)) % 12) +
3578 ((value >> 7) & 1) * 12;
3579 else
3580 s->alarm_tm.tm_hour = omap_rtc_bin(value);
3581 omap_rtc_alarm_update(s);
3582 return;
3583
3584 case 0x2c: /* ALARM_DAYS_REG */
3585 #if ALMDEBUG
3586 printf("ALM DAY_REG <-- %02x\n", value);
3587 #endif
3588 s->alarm_tm.tm_mday = omap_rtc_bin(value);
3589 omap_rtc_alarm_update(s);
3590 return;
3591
3592 case 0x30: /* ALARM_MONTHS_REG */
3593 #if ALMDEBUG
3594 printf("ALM MON_REG <-- %02x\n", value);
3595 #endif
3596 s->alarm_tm.tm_mon = omap_rtc_bin(value);
3597 omap_rtc_alarm_update(s);
3598 return;
3599
3600 case 0x34: /* ALARM_YEARS_REG */
3601 #if ALMDEBUG
3602 printf("ALM YRS_REG <-- %02x\n", value);
3603 #endif
3604 s->alarm_tm.tm_year = omap_rtc_bin(value);
3605 omap_rtc_alarm_update(s);
3606 return;
3607
3608 case 0x40: /* RTC_CTRL_REG */
3609 #if ALMDEBUG
3610 printf("RTC CONTROL <-- %02x\n", value);
3611 #endif
3612 s->pm_am = (value >> 3) & 1;
3613 s->auto_comp = (value >> 2) & 1;
3614 s->round = (value >> 1) & 1;
3615 s->running = value & 1;
3616 s->status &= 0xfd;
3617 s->status |= s->running << 1;
3618 return;
3619
3620 case 0x44: /* RTC_STATUS_REG */
3621 #if ALMDEBUG
3622 printf("RTC STATUSL <-- %02x\n", value);
3623 #endif
3624 s->status &= ~((value & 0xc0) ^ 0x80);
3625 omap_rtc_interrupts_update(s);
3626 return;
3627
3628 case 0x48: /* RTC_INTERRUPTS_REG */
3629 #if ALMDEBUG
3630 printf("RTC INTRS <-- %02x\n", value);
3631 #endif
3632 s->interrupts = value;
3633 return;
3634
3635 case 0x4c: /* RTC_COMP_LSB_REG */
3636 #if ALMDEBUG
3637 printf("RTC COMPLSB <-- %02x\n", value);
3638 #endif
3639 s->comp_reg &= 0xff00;
3640 s->comp_reg |= 0x00ff & value;
3641 return;
3642
3643 case 0x50: /* RTC_COMP_MSB_REG */
3644 #if ALMDEBUG
3645 printf("RTC COMPMSB <-- %02x\n", value);
3646 #endif
3647 s->comp_reg &= 0x00ff;
3648 s->comp_reg |= 0xff00 & (value << 8);
3649 return;
3650
3651 default:
3652 OMAP_BAD_REG(addr);
3653 return;
3654 }
3655 }
3656
3657 static CPUReadMemoryFunc *omap_rtc_readfn[] = {
3658 omap_rtc_read,
3659 omap_badwidth_read8,
3660 omap_badwidth_read8,
3661 };
3662
3663 static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
3664 omap_rtc_write,
3665 omap_badwidth_write8,
3666 omap_badwidth_write8,
3667 };
3668
3669 static void omap_rtc_tick(void *opaque)
3670 {
3671 struct omap_rtc_s *s = opaque;
3672
3673 if (s->round) {
3674 /* Round to nearest full minute. */
3675 if (s->current_tm.tm_sec < 30)
3676 s->ti -= s->current_tm.tm_sec;
3677 else
3678 s->ti += 60 - s->current_tm.tm_sec;
3679
3680 s->round = 0;
3681 }
3682
3683 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
3684
3685 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
3686 s->status |= 0x40;
3687 omap_rtc_interrupts_update(s);
3688 }
3689
3690 if (s->interrupts & 0x04)
3691 switch (s->interrupts & 3) {
3692 case 0:
3693 s->status |= 0x04;
3694 qemu_irq_pulse(s->irq);
3695 break;
3696 case 1:
3697 if (s->current_tm.tm_sec)
3698 break;
3699 s->status |= 0x08;
3700 qemu_irq_pulse(s->irq);
3701 break;
3702 case 2:
3703 if (s->current_tm.tm_sec || s->current_tm.tm_min)
3704 break;
3705 s->status |= 0x10;
3706 qemu_irq_pulse(s->irq);
3707 break;
3708 case 3:
3709 if (s->current_tm.tm_sec ||
3710 s->current_tm.tm_min || s->current_tm.tm_hour)
3711 break;
3712 s->status |= 0x20;
3713 qemu_irq_pulse(s->irq);
3714 break;
3715 }
3716
3717 /* Move on */
3718 if (s->running)
3719 s->ti ++;
3720 s->tick += 1000;
3721
3722 /*
3723 * Every full hour add a rough approximation of the compensation
3724 * register to the 32kHz Timer (which drives the RTC) value.
3725 */
3726 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
3727 s->tick += s->comp_reg * 1000 / 32768;
3728
3729 qemu_mod_timer(s->clk, s->tick);
3730 }
3731
3732 static void omap_rtc_reset(struct omap_rtc_s *s)
3733 {
3734 struct tm tm;
3735
3736 s->interrupts = 0;
3737 s->comp_reg = 0;
3738 s->running = 0;
3739 s->pm_am = 0;
3740 s->auto_comp = 0;
3741 s->round = 0;
3742 s->tick = qemu_get_clock(rt_clock);
3743 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
3744 s->alarm_tm.tm_mday = 0x01;
3745 s->status = 1 << 7;
3746 qemu_get_timedate(&tm, 0);
3747 s->ti = mktime(&tm);
3748
3749 omap_rtc_alarm_update(s);
3750 omap_rtc_tick(s);
3751 }
3752
3753 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
3754 qemu_irq *irq, omap_clk clk)
3755 {
3756 int iomemtype;
3757 struct omap_rtc_s *s = (struct omap_rtc_s *)
3758 qemu_mallocz(sizeof(struct omap_rtc_s));
3759
3760 s->base = base;
3761 s->irq = irq[0];
3762 s->alarm = irq[1];
3763 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
3764
3765 omap_rtc_reset(s);
3766
3767 iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
3768 omap_rtc_writefn, s);
3769 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3770
3771 return s;
3772 }
3773
3774 /* Multi-channel Buffered Serial Port interfaces */
3775 struct omap_mcbsp_s {
3776 target_phys_addr_t base;
3777 qemu_irq txirq;
3778 qemu_irq rxirq;
3779 qemu_irq txdrq;
3780 qemu_irq rxdrq;
3781
3782 uint16_t spcr[2];
3783 uint16_t rcr[2];
3784 uint16_t xcr[2];
3785 uint16_t srgr[2];
3786 uint16_t mcr[2];
3787 uint16_t pcr;
3788 uint16_t rcer[8];
3789 uint16_t xcer[8];
3790 int tx_rate;
3791 int rx_rate;
3792 int tx_req;
3793 int rx_req;
3794
3795 struct i2s_codec_s *codec;
3796 QEMUTimer *source_timer;
3797 QEMUTimer *sink_timer;
3798 };
3799
3800 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
3801 {
3802 int irq;
3803
3804 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
3805 case 0:
3806 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
3807 break;
3808 case 3:
3809 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
3810 break;
3811 default:
3812 irq = 0;
3813 break;
3814 }
3815
3816 if (irq)
3817 qemu_irq_pulse(s->rxirq);
3818
3819 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
3820 case 0:
3821 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
3822 break;
3823 case 3:
3824 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
3825 break;
3826 default:
3827 irq = 0;
3828 break;
3829 }
3830
3831 if (irq)
3832 qemu_irq_pulse(s->txirq);
3833 }
3834
3835 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
3836 {
3837 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3838 s->spcr[0] |= 1 << 2; /* RFULL */
3839 s->spcr[0] |= 1 << 1; /* RRDY */
3840 qemu_irq_raise(s->rxdrq);
3841 omap_mcbsp_intr_update(s);
3842 }
3843
3844 static void omap_mcbsp_source_tick(void *opaque)
3845 {
3846 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3847 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3848
3849 if (!s->rx_rate)
3850 return;
3851 if (s->rx_req)
3852 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
3853
3854 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
3855
3856 omap_mcbsp_rx_newdata(s);
3857 qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
3858 }
3859
3860 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3861 {
3862 if (!s->codec || !s->codec->rts)
3863 omap_mcbsp_source_tick(s);
3864 else if (s->codec->in.len) {
3865 s->rx_req = s->codec->in.len;
3866 omap_mcbsp_rx_newdata(s);
3867 }
3868 }
3869
3870 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
3871 {
3872 qemu_del_timer(s->source_timer);
3873 }
3874
3875 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
3876 {
3877 s->spcr[0] &= ~(1 << 1); /* RRDY */
3878 qemu_irq_lower(s->rxdrq);
3879 omap_mcbsp_intr_update(s);
3880 }
3881
3882 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3883 {
3884 s->spcr[1] |= 1 << 1; /* XRDY */
3885 qemu_irq_raise(s->txdrq);
3886 omap_mcbsp_intr_update(s);
3887 }
3888
3889 static void omap_mcbsp_sink_tick(void *opaque)
3890 {
3891 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3892 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3893
3894 if (!s->tx_rate)
3895 return;
3896 if (s->tx_req)
3897 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
3898
3899 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3900
3901 omap_mcbsp_tx_newdata(s);
3902 qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
3903 }
3904
3905 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3906 {
3907 if (!s->codec || !s->codec->cts)
3908 omap_mcbsp_sink_tick(s);
3909 else if (s->codec->out.size) {
3910 s->tx_req = s->codec->out.size;
3911 omap_mcbsp_tx_newdata(s);
3912 }
3913 }
3914
3915 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3916 {
3917 s->spcr[1] &= ~(1 << 1); /* XRDY */
3918 qemu_irq_lower(s->txdrq);
3919 omap_mcbsp_intr_update(s);
3920 if (s->codec && s->codec->cts)
3921 s->codec->tx_swallow(s->codec->opaque);
3922 }
3923
3924 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3925 {
3926 s->tx_req = 0;
3927 omap_mcbsp_tx_done(s);
3928 qemu_del_timer(s->sink_timer);
3929 }
3930
3931 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3932 {
3933 int prev_rx_rate, prev_tx_rate;
3934 int rx_rate = 0, tx_rate = 0;
3935 int cpu_rate = 1500000; /* XXX */
3936
3937 /* TODO: check CLKSTP bit */
3938 if (s->spcr[1] & (1 << 6)) { /* GRST */
3939 if (s->spcr[0] & (1 << 0)) { /* RRST */
3940 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3941 (s->pcr & (1 << 8))) { /* CLKRM */
3942 if (~s->pcr & (1 << 7)) /* SCLKME */
3943 rx_rate = cpu_rate /
3944 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3945 } else
3946 if (s->codec)
3947 rx_rate = s->codec->rx_rate;
3948 }
3949
3950 if (s->spcr[1] & (1 << 0)) { /* XRST */
3951 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3952 (s->pcr & (1 << 9))) { /* CLKXM */
3953 if (~s->pcr & (1 << 7)) /* SCLKME */
3954 tx_rate = cpu_rate /
3955 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3956 } else
3957 if (s->codec)
3958 tx_rate = s->codec->tx_rate;
3959 }
3960 }
3961 prev_tx_rate = s->tx_rate;
3962 prev_rx_rate = s->rx_rate;
3963 s->tx_rate = tx_rate;
3964 s->rx_rate = rx_rate;
3965
3966 if (s->codec)
3967 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3968
3969 if (!prev_tx_rate && tx_rate)
3970 omap_mcbsp_tx_start(s);
3971 else if (s->tx_rate && !tx_rate)
3972 omap_mcbsp_tx_stop(s);
3973
3974 if (!prev_rx_rate && rx_rate)
3975 omap_mcbsp_rx_start(s);
3976 else if (prev_tx_rate && !tx_rate)
3977 omap_mcbsp_rx_stop(s);
3978 }
3979
3980 static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
3981 {
3982 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3983 int offset = addr & OMAP_MPUI_REG_MASK;
3984 uint16_t ret;
3985
3986 switch (offset) {
3987 case 0x00: /* DRR2 */
3988 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3989 return 0x0000;
3990 /* Fall through. */
3991 case 0x02: /* DRR1 */
3992 if (s->rx_req < 2) {
3993 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
3994 omap_mcbsp_rx_done(s);
3995 } else {
3996 s->tx_req -= 2;
3997 if (s->codec && s->codec->in.len >= 2) {
3998 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3999 ret |= s->codec->in.fifo[s->codec->in.start ++];
4000 s->codec->in.len -= 2;
4001 } else
4002 ret = 0x0000;
4003 if (!s->tx_req)
4004 omap_mcbsp_rx_done(s);
4005 return ret;
4006 }
4007 return 0x0000;
4008
4009 case 0x04: /* DXR2 */
4010 case 0x06: /* DXR1 */
4011 return 0x0000;
4012
4013 case 0x08: /* SPCR2 */
4014 return s->spcr[1];
4015 case 0x0a: /* SPCR1 */
4016 return s->spcr[0];
4017 case 0x0c: /* RCR2 */
4018 return s->rcr[1];
4019 case 0x0e: /* RCR1 */
4020 return s->rcr[0];
4021 case 0x10: /* XCR2 */
4022 return s->xcr[1];
4023 case 0x12: /* XCR1 */
4024 return s->xcr[0];
4025 case 0x14: /* SRGR2 */
4026 return s->srgr[1];
4027 case 0x16: /* SRGR1 */
4028 return s->srgr[0];
4029 case 0x18: /* MCR2 */
4030 return s->mcr[1];
4031 case 0x1a: /* MCR1 */
4032 return s->mcr[0];
4033 case 0x1c: /* RCERA */
4034 return s->rcer[0];
4035 case 0x1e: /* RCERB */
4036 return s->rcer[1];
4037 case 0x20: /* XCERA */
4038 return s->xcer[0];
4039 case 0x22: /* XCERB */
4040 return s->xcer[1];
4041 case 0x24: /* PCR0 */
4042 return s->pcr;
4043 case 0x26: /* RCERC */
4044 return s->rcer[2];
4045 case 0x28: /* RCERD */
4046 return s->rcer[3];
4047 case 0x2a: /* XCERC */
4048 return s->xcer[2];
4049 case 0x2c: /* XCERD */
4050 return s->xcer[3];
4051 case 0x2e: /* RCERE */
4052 return s->rcer[4];
4053 case 0x30: /* RCERF */
4054 return s->rcer[5];
4055 case 0x32: /* XCERE */
4056 return s->xcer[4];
4057 case 0x34: /* XCERF */
4058 return s->xcer[5];
4059 case 0x36: /* RCERG */
4060 return s->rcer[6];
4061 case 0x38: /* RCERH */
4062 return s->rcer[7];
4063 case 0x3a: /* XCERG */
4064 return s->xcer[6];
4065 case 0x3c: /* XCERH */
4066 return s->xcer[7];
4067 }
4068
4069 OMAP_BAD_REG(addr);
4070 return 0;
4071 }
4072
4073 static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
4074 uint32_t value)
4075 {
4076 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4077 int offset = addr & OMAP_MPUI_REG_MASK;
4078
4079 switch (offset) {
4080 case 0x00: /* DRR2 */
4081 case 0x02: /* DRR1 */
4082 OMAP_RO_REG(addr);
4083 return;
4084
4085 case 0x04: /* DXR2 */
4086 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4087 return;
4088 /* Fall through. */
4089 case 0x06: /* DXR1 */
4090 if (s->tx_req > 1) {
4091 s->tx_req -= 2;
4092 if (s->codec && s->codec->cts) {
4093 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
4094 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
4095 }
4096 if (s->tx_req < 2)
4097 omap_mcbsp_tx_done(s);
4098 } else
4099 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4100 return;
4101
4102 case 0x08: /* SPCR2 */
4103 s->spcr[1] &= 0x0002;
4104 s->spcr[1] |= 0x03f9 & value;
4105 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
4106 if (~value & 1) /* XRST */
4107 s->spcr[1] &= ~6;
4108 omap_mcbsp_req_update(s);
4109 return;
4110 case 0x0a: /* SPCR1 */
4111 s->spcr[0] &= 0x0006;
4112 s->spcr[0] |= 0xf8f9 & value;
4113 if (value & (1 << 15)) /* DLB */
4114 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
4115 if (~value & 1) { /* RRST */
4116 s->spcr[0] &= ~6;
4117 s->rx_req = 0;
4118 omap_mcbsp_rx_done(s);
4119 }
4120 omap_mcbsp_req_update(s);
4121 return;
4122
4123 case 0x0c: /* RCR2 */
4124 s->rcr[1] = value & 0xffff;
4125 return;
4126 case 0x0e: /* RCR1 */
4127 s->rcr[0] = value & 0x7fe0;
4128 return;
4129 case 0x10: /* XCR2 */
4130 s->xcr[1] = value & 0xffff;
4131 return;
4132 case 0x12: /* XCR1 */
4133 s->xcr[0] = value & 0x7fe0;
4134 return;
4135 case 0x14: /* SRGR2 */
4136 s->srgr[1] = value & 0xffff;
4137 omap_mcbsp_req_update(s);
4138 return;
4139 case 0x16: /* SRGR1 */
4140 s->srgr[0] = value & 0xffff;
4141 omap_mcbsp_req_update(s);
4142 return;
4143 case 0x18: /* MCR2 */
4144 s->mcr[1] = value & 0x03e3;
4145 if (value & 3) /* XMCM */
4146 printf("%s: Tx channel selection mode enable attempt\n",
4147 __FUNCTION__);
4148 return;
4149 case 0x1a: /* MCR1 */
4150 s->mcr[0] = value & 0x03e1;
4151 if (value & 1) /* RMCM */
4152 printf("%s: Rx channel selection mode enable attempt\n",
4153 __FUNCTION__);
4154 return;
4155 case 0x1c: /* RCERA */
4156 s->rcer[0] = value & 0xffff;
4157 return;
4158 case 0x1e: /* RCERB */
4159 s->rcer[1] = value & 0xffff;
4160 return;
4161 case 0x20: /* XCERA */
4162 s->xcer[0] = value & 0xffff;
4163 return;
4164 case 0x22: /* XCERB */
4165 s->xcer[1] = value & 0xffff;
4166 return;
4167 case 0x24: /* PCR0 */
4168 s->pcr = value & 0x7faf;
4169 return;
4170 case 0x26: /* RCERC */
4171 s->rcer[2] = value & 0xffff;
4172 return;
4173 case 0x28: /* RCERD */
4174 s->rcer[3] = value & 0xffff;
4175 return;
4176 case 0x2a: /* XCERC */
4177 s->xcer[2] = value & 0xffff;
4178 return;
4179 case 0x2c: /* XCERD */
4180 s->xcer[3] = value & 0xffff;
4181 return;
4182 case 0x2e: /* RCERE */
4183 s->rcer[4] = value & 0xffff;
4184 return;
4185 case 0x30: /* RCERF */
4186 s->rcer[5] = value & 0xffff;
4187 return;
4188 case 0x32: /* XCERE */
4189 s->xcer[4] = value & 0xffff;
4190 return;
4191 case 0x34: /* XCERF */
4192 s->xcer[5] = value & 0xffff;
4193 return;
4194 case 0x36: /* RCERG */
4195 s->rcer[6] = value & 0xffff;
4196 return;
4197 case 0x38: /* RCERH */
4198 s->rcer[7] = value & 0xffff;
4199 return;
4200 case 0x3a: /* XCERG */
4201 s->xcer[6] = value & 0xffff;
4202 return;
4203 case 0x3c: /* XCERH */
4204 s->xcer[7] = value & 0xffff;
4205 return;
4206 }
4207
4208 OMAP_BAD_REG(addr);
4209 }
4210
4211 static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
4212 uint32_t value)
4213 {
4214 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4215 int offset = addr & OMAP_MPUI_REG_MASK;
4216
4217 if (offset == 0x04) { /* DXR */
4218 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4219 return;
4220 if (s->tx_req > 3) {
4221 s->tx_req -= 4;
4222 if (s->codec && s->codec->cts) {
4223 s->codec->out.fifo[s->codec->out.len ++] =
4224 (value >> 24) & 0xff;
4225 s->codec->out.fifo[s->codec->out.len ++] =
4226 (value >> 16) & 0xff;
4227 s->codec->out.fifo[s->codec->out.len ++] =
4228 (value >> 8) & 0xff;
4229 s->codec->out.fifo[s->codec->out.len ++] =
4230 (value >> 0) & 0xff;
4231 }
4232 if (s->tx_req < 4)
4233 omap_mcbsp_tx_done(s);
4234 } else
4235 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4236 return;
4237 }
4238
4239 omap_badwidth_write16(opaque, addr, value);
4240 }
4241
4242 static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
4243 omap_badwidth_read16,
4244 omap_mcbsp_read,
4245 omap_badwidth_read16,
4246 };
4247
4248 static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
4249 omap_badwidth_write16,
4250 omap_mcbsp_writeh,
4251 omap_mcbsp_writew,
4252 };
4253
4254 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
4255 {
4256 memset(&s->spcr, 0, sizeof(s->spcr));
4257 memset(&s->rcr, 0, sizeof(s->rcr));
4258 memset(&s->xcr, 0, sizeof(s->xcr));
4259 s->srgr[0] = 0x0001;
4260 s->srgr[1] = 0x2000;
4261 memset(&s->mcr, 0, sizeof(s->mcr));
4262 memset(&s->pcr, 0, sizeof(s->pcr));
4263 memset(&s->rcer, 0, sizeof(s->rcer));
4264 memset(&s->xcer, 0, sizeof(s->xcer));
4265 s->tx_req = 0;
4266 s->rx_req = 0;
4267 s->tx_rate = 0;
4268 s->rx_rate = 0;
4269 qemu_del_timer(s->source_timer);
4270 qemu_del_timer(s->sink_timer);
4271 }
4272
4273 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
4274 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
4275 {
4276 int iomemtype;
4277 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
4278 qemu_mallocz(sizeof(struct omap_mcbsp_s));
4279
4280 s->base = base;
4281 s->txirq = irq[0];
4282 s->rxirq = irq[1];
4283 s->txdrq = dma[0];
4284 s->rxdrq = dma[1];
4285 s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s);
4286 s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
4287 omap_mcbsp_reset(s);
4288
4289 iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
4290 omap_mcbsp_writefn, s);
4291 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4292
4293 return s;
4294 }
4295
4296 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
4297 {
4298 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4299
4300 if (s->rx_rate) {
4301 s->rx_req = s->codec->in.len;
4302 omap_mcbsp_rx_newdata(s);
4303 }
4304 }
4305
4306 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
4307 {
4308 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4309
4310 if (s->tx_rate) {
4311 s->tx_req = s->codec->out.size;
4312 omap_mcbsp_tx_newdata(s);
4313 }
4314 }
4315
4316 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
4317 {
4318 s->codec = slave;
4319 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
4320 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
4321 }
4322
4323 /* LED Pulse Generators */
4324 struct omap_lpg_s {
4325 target_phys_addr_t base;
4326 QEMUTimer *tm;
4327
4328 uint8_t control;
4329 uint8_t power;
4330 int64_t on;
4331 int64_t period;
4332 int clk;
4333 int cycle;
4334 };
4335
4336 static void omap_lpg_tick(void *opaque)
4337 {
4338 struct omap_lpg_s *s = opaque;
4339
4340 if (s->cycle)
4341 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on);
4342 else
4343 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on);
4344
4345 s->cycle = !s->cycle;
4346 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
4347 }
4348
4349 static void omap_lpg_update(struct omap_lpg_s *s)
4350 {
4351 int64_t on, period = 1, ticks = 1000;
4352 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
4353
4354 if (~s->control & (1 << 6)) /* LPGRES */
4355 on = 0;
4356 else if (s->control & (1 << 7)) /* PERM_ON */
4357 on = period;
4358 else {
4359 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
4360 256 / 32);
4361 on = (s->clk && s->power) ? muldiv64(ticks,
4362 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
4363 }
4364
4365 qemu_del_timer(s->tm);
4366 if (on == period && s->on < s->period)
4367 printf("%s: LED is on\n", __FUNCTION__);
4368 else if (on == 0 && s->on)
4369 printf("%s: LED is off\n", __FUNCTION__);
4370 else if (on && (on != s->on || period != s->period)) {
4371 s->cycle = 0;
4372 s->on = on;
4373 s->period = period;
4374 omap_lpg_tick(s);
4375 return;
4376 }
4377
4378 s->on = on;
4379 s->period = period;
4380 }
4381
4382 static void omap_lpg_reset(struct omap_lpg_s *s)
4383 {
4384 s->control = 0x00;
4385 s->power = 0x00;
4386 s->clk = 1;
4387 omap_lpg_update(s);
4388 }
4389
4390 static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
4391 {
4392 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4393 int offset = addr & OMAP_MPUI_REG_MASK;
4394
4395 switch (offset) {
4396 case 0x00: /* LCR */
4397 return s->control;
4398
4399 case 0x04: /* PMR */
4400 return s->power;
4401 }
4402
4403 OMAP_BAD_REG(addr);
4404 return 0;
4405 }
4406
4407 static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
4408 uint32_t value)
4409 {
4410 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4411 int offset = addr & OMAP_MPUI_REG_MASK;
4412
4413 switch (offset) {
4414 case 0x00: /* LCR */
4415 if (~value & (1 << 6)) /* LPGRES */
4416 omap_lpg_reset(s);
4417 s->control = value & 0xff;
4418 omap_lpg_update(s);
4419 return;
4420
4421 case 0x04: /* PMR */
4422 s->power = value & 0x01;
4423 omap_lpg_update(s);
4424 return;
4425
4426 default:
4427 OMAP_BAD_REG(addr);
4428 return;
4429 }
4430 }
4431
4432 static CPUReadMemoryFunc *omap_lpg_readfn[] = {
4433 omap_lpg_read,
4434 omap_badwidth_read8,
4435 omap_badwidth_read8,
4436 };
4437
4438 static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
4439 omap_lpg_write,
4440 omap_badwidth_write8,
4441 omap_badwidth_write8,
4442 };
4443
4444 static void omap_lpg_clk_update(void *opaque, int line, int on)
4445 {
4446 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4447
4448 s->clk = on;
4449 omap_lpg_update(s);
4450 }
4451
4452 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
4453 {
4454 int iomemtype;
4455 struct omap_lpg_s *s = (struct omap_lpg_s *)
4456 qemu_mallocz(sizeof(struct omap_lpg_s));
4457
4458 s->base = base;
4459 s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
4460
4461 omap_lpg_reset(s);
4462
4463 iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
4464 omap_lpg_writefn, s);
4465 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4466
4467 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
4468
4469 return s;
4470 }
4471
4472 /* MPUI Peripheral Bridge configuration */
4473 static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
4474 {
4475 if (addr == OMAP_MPUI_BASE) /* CMR */
4476 return 0xfe4d;
4477
4478 OMAP_BAD_REG(addr);
4479 return 0;
4480 }
4481
4482 static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
4483 omap_badwidth_read16,
4484 omap_mpui_io_read,
4485 omap_badwidth_read16,
4486 };
4487
4488 static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
4489 omap_badwidth_write16,
4490 omap_badwidth_write16,
4491 omap_badwidth_write16,
4492 };
4493
4494 static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
4495 {
4496 int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn,
4497 omap_mpui_io_writefn, mpu);
4498 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
4499 }
4500
4501 /* General chip reset */
4502 static void omap1_mpu_reset(void *opaque)
4503 {
4504 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4505
4506 omap_inth_reset(mpu->ih[0]);
4507 omap_inth_reset(mpu->ih[1]);
4508 omap_dma_reset(mpu->dma);
4509 omap_mpu_timer_reset(mpu->timer[0]);
4510 omap_mpu_timer_reset(mpu->timer[1]);
4511 omap_mpu_timer_reset(mpu->timer[2]);
4512 omap_wd_timer_reset(mpu->wdt);
4513 omap_os_timer_reset(mpu->os_timer);
4514 omap_lcdc_reset(mpu->lcd);
4515 omap_ulpd_pm_reset(mpu);
4516 omap_pin_cfg_reset(mpu);
4517 omap_mpui_reset(mpu);
4518 omap_tipb_bridge_reset(mpu->private_tipb);
4519 omap_tipb_bridge_reset(mpu->public_tipb);
4520 omap_dpll_reset(&mpu->dpll[0]);
4521 omap_dpll_reset(&mpu->dpll[1]);
4522 omap_dpll_reset(&mpu->dpll[2]);
4523 omap_uart_reset(mpu->uart[0]);
4524 omap_uart_reset(mpu->uart[1]);
4525 omap_uart_reset(mpu->uart[2]);
4526 omap_mmc_reset(mpu->mmc);
4527 omap_mpuio_reset(mpu->mpuio);
4528 omap_gpio_reset(mpu->gpio);
4529 omap_uwire_reset(mpu->microwire);
4530 omap_pwl_reset(mpu);
4531 omap_pwt_reset(mpu);
4532 omap_i2c_reset(mpu->i2c[0]);
4533 omap_rtc_reset(mpu->rtc);
4534 omap_mcbsp_reset(mpu->mcbsp1);
4535 omap_mcbsp_reset(mpu->mcbsp2);
4536 omap_mcbsp_reset(mpu->mcbsp3);
4537 omap_lpg_reset(mpu->led[0]);
4538 omap_lpg_reset(mpu->led[1]);
4539 omap_clkm_reset(mpu);
4540 cpu_reset(mpu->env);
4541 }
4542
4543 static const struct omap_map_s {
4544 target_phys_addr_t phys_dsp;
4545 target_phys_addr_t phys_mpu;
4546 uint32_t size;
4547 const char *name;
4548 } omap15xx_dsp_mm[] = {
4549 /* Strobe 0 */
4550 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
4551 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
4552 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
4553 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
4554 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
4555 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
4556 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
4557 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
4558 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
4559 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
4560 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
4561 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
4562 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
4563 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
4564 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
4565 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
4566 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
4567 /* Strobe 1 */
4568 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
4569
4570 { 0 }
4571 };
4572
4573 static void omap_setup_dsp_mapping(const struct omap_map_s *map)
4574 {
4575 int io;
4576
4577 for (; map->phys_dsp; map ++) {
4578 io = cpu_get_physical_page_desc(map->phys_mpu);
4579
4580 cpu_register_physical_memory(map->phys_dsp, map->size, io);
4581 }
4582 }
4583
4584 void omap_mpu_wakeup(void *opaque, int irq, int req)
4585 {
4586 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4587
4588 if (mpu->env->halted)
4589 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
4590 }
4591
4592 static const struct dma_irq_map omap1_dma_irq_map[] = {
4593 { 0, OMAP_INT_DMA_CH0_6 },
4594 { 0, OMAP_INT_DMA_CH1_7 },
4595 { 0, OMAP_INT_DMA_CH2_8 },
4596 { 0, OMAP_INT_DMA_CH3 },
4597 { 0, OMAP_INT_DMA_CH4 },
4598 { 0, OMAP_INT_DMA_CH5 },
4599 { 1, OMAP_INT_1610_DMA_CH6 },
4600 { 1, OMAP_INT_1610_DMA_CH7 },
4601 { 1, OMAP_INT_1610_DMA_CH8 },
4602 { 1, OMAP_INT_1610_DMA_CH9 },
4603 { 1, OMAP_INT_1610_DMA_CH10 },
4604 { 1, OMAP_INT_1610_DMA_CH11 },
4605 { 1, OMAP_INT_1610_DMA_CH12 },
4606 { 1, OMAP_INT_1610_DMA_CH13 },
4607 { 1, OMAP_INT_1610_DMA_CH14 },
4608 { 1, OMAP_INT_1610_DMA_CH15 }
4609 };
4610
4611 /* DMA ports for OMAP1 */
4612 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
4613 target_phys_addr_t addr)
4614 {
4615 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
4616 }
4617
4618 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
4619 target_phys_addr_t addr)
4620 {
4621 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
4622 }
4623
4624 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
4625 target_phys_addr_t addr)
4626 {
4627 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
4628 }
4629
4630 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
4631 target_phys_addr_t addr)
4632 {
4633 return addr >= 0xfffb0000 && addr < 0xffff0000;
4634 }
4635
4636 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
4637 target_phys_addr_t addr)
4638 {
4639 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
4640 }
4641
4642 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
4643 target_phys_addr_t addr)
4644 {
4645 return addr >= 0xe1010000 && addr < 0xe1020004;
4646 }
4647
4648 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
4649 DisplayState *ds, const char *core)
4650 {
4651 int i;
4652 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4653 qemu_mallocz(sizeof(struct omap_mpu_state_s));
4654 ram_addr_t imif_base, emiff_base;
4655 qemu_irq *cpu_irq;
4656 qemu_irq dma_irqs[6];
4657 int sdindex;
4658
4659 if (!core)
4660 core = "ti925t";
4661
4662 /* Core */
4663 s->mpu_model = omap310;
4664 s->env = cpu_init(core);
4665 if (!s->env) {
4666 fprintf(stderr, "Unable to find CPU definition\n");
4667 exit(1);
4668 }
4669 s->sdram_size = sdram_size;
4670 s->sram_size = OMAP15XX_SRAM_SIZE;
4671
4672 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4673
4674 /* Clocks */
4675 omap_clk_init(s);
4676
4677 /* Memory-mapped stuff */
4678 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
4679 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4680 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
4681 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4682
4683 omap_clkm_init(0xfffece00, 0xe1008000, s);
4684
4685 cpu_irq = arm_pic_init_cpu(s->env);
4686 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
4687 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
4688 omap_findclk(s, "arminth_ck"));
4689 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
4690 s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL,
4691 omap_findclk(s, "arminth_ck"));
4692
4693 for (i = 0; i < 6; i ++)
4694 dma_irqs[i] =
4695 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
4696 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
4697 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
4698
4699 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
4700 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
4701 s->port[imif ].addr_valid = omap_validate_imif_addr;
4702 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
4703 s->port[local ].addr_valid = omap_validate_local_addr;
4704 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
4705
4706 s->timer[0] = omap_mpu_timer_init(0xfffec500,
4707 s->irq[0][OMAP_INT_TIMER1],
4708 omap_findclk(s, "mputim_ck"));
4709 s->timer[1] = omap_mpu_timer_init(0xfffec600,
4710 s->irq[0][OMAP_INT_TIMER2],
4711 omap_findclk(s, "mputim_ck"));
4712 s->timer[2] = omap_mpu_timer_init(0xfffec700,
4713 s->irq[0][OMAP_INT_TIMER3],
4714 omap_findclk(s, "mputim_ck"));
4715
4716 s->wdt = omap_wd_timer_init(0xfffec800,
4717 s->irq[0][OMAP_INT_WD_TIMER],
4718 omap_findclk(s, "armwdt_ck"));
4719
4720 s->os_timer = omap_os_timer_init(0xfffb9000,
4721 s->irq[1][OMAP_INT_OS_TIMER],
4722 omap_findclk(s, "clk32-kHz"));
4723
4724 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
4725 omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base,
4726 omap_findclk(s, "lcd_ck"));
4727
4728 omap_ulpd_pm_init(0xfffe0800, s);
4729 omap_pin_cfg_init(0xfffe1000, s);
4730 omap_id_init(s);
4731
4732 omap_mpui_init(0xfffec900, s);
4733
4734 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
4735 s->irq[0][OMAP_INT_BRIDGE_PRIV],
4736 omap_findclk(s, "tipb_ck"));
4737 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
4738 s->irq[0][OMAP_INT_BRIDGE_PUB],
4739 omap_findclk(s, "tipb_ck"));
4740
4741 omap_tcmi_init(0xfffecc00, s);
4742
4743 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
4744 omap_findclk(s, "uart1_ck"),
4745 omap_findclk(s, "uart1_ck"),
4746 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
4747 serial_hds[0]);
4748 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
4749 omap_findclk(s, "uart2_ck"),
4750 omap_findclk(s, "uart2_ck"),
4751 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
4752 serial_hds[0] ? serial_hds[1] : 0);
4753 s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3],
4754 omap_findclk(s, "uart3_ck"),
4755 omap_findclk(s, "uart3_ck"),
4756 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
4757 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
4758
4759 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
4760 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
4761 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
4762
4763 sdindex = drive_get_index(IF_SD, 0, 0);
4764 if (sdindex == -1) {
4765 fprintf(stderr, "qemu: missing SecureDigital device\n");
4766 exit(1);
4767 }
4768 s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv,
4769 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
4770 omap_findclk(s, "mmc_ck"));
4771
4772 s->mpuio = omap_mpuio_init(0xfffb5000,
4773 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
4774 s->wakeup, omap_findclk(s, "clk32-kHz"));
4775
4776 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1],
4777 omap_findclk(s, "arm_gpio_ck"));
4778
4779 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
4780 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4781
4782 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
4783 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
4784
4785 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
4786 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
4787
4788 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
4789 omap_findclk(s, "clk32-kHz"));
4790
4791 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
4792 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4793 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
4794 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4795 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
4796 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4797
4798 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
4799 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
4800
4801 /* Register mappings not currenlty implemented:
4802 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4803 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4804 * USB W2FC fffb4000 - fffb47ff
4805 * Camera Interface fffb6800 - fffb6fff
4806 * USB Host fffba000 - fffba7ff
4807 * FAC fffba800 - fffbafff
4808 * HDQ/1-Wire fffbc000 - fffbc7ff
4809 * TIPB switches fffbc800 - fffbcfff
4810 * Mailbox fffcf000 - fffcf7ff
4811 * Local bus IF fffec100 - fffec1ff
4812 * Local bus MMU fffec200 - fffec2ff
4813 * DSP MMU fffed200 - fffed2ff
4814 */
4815
4816 omap_setup_dsp_mapping(omap15xx_dsp_mm);
4817 omap_setup_mpui_io(s);
4818
4819 qemu_register_reset(omap1_mpu_reset, s);
4820
4821 return s;
4822 }
Qemu copy for testing